A test device and test method for dynamic on-resistance of gallium nitride power device

Abstract

The present invention discloses a test device and a test method for the dynamic on-resistance of a gallium nitride device. The test device includes a direct current power supply, a first drive switch, a second drive switch, a third drive switch, a device under test, a first diode, a second diode, a load inductor, a first capacitor and a second capacitor; the drive switch and the device under test are both equipped with an isolated drive control module; the device also includes a DUT voltage detection unit and an inductor current detection unit. The test method includes determining the test requirements and test modes, setting the switch timing of the drive switch in each test stage, using the voltage detection unit and the current detection unit for continuous sampling, and determining the dynamic on-resistance of the device under test according to the sampled current and voltage. The present invention solves the problem that the prior art cannot effectively evaluate the influence of high voltage stress time on the dynamic on-resistance of gallium nitride devices in the state where the pre-charge is cleared, and can perform relevant tests in two modes, single pulse and continuous pulse, according to the test requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor device measurement, and in particular relates to a testing device and a testing method for the dynamic on-resistance of a gallium nitride power device. Background Art

[0002] As the switching power supply market continues to increase its demand for device energy density, GaN semiconductor devices are beginning to be more widely used in consumer products, automobiles, industry and other fields. At the same time, standardizing the relevant test methods and standards for GaN devices is crucial for semiconductor manufacturers to improve their product quality and reliability. Among them, GaN dynamic on-resistance evaluation is one of the key points that need to be standardized, mainly for the following three reasons:

[0003] 1. Dynamic on-resistance is a unique characteristic of GaN devices, which is manifested as a short-term recoverable increase in on-resistance after the device is subjected to high voltage stress. Currently, there is still a lack of standardized test standards. Due to the particularity of the test conditions required for this characteristic, the current general test equipment and methods for silicon-based switch tubes are not applicable to GaN switch devices;

[0004] 2. Since the production process of GaN devices is still immature compared to silicon-based devices, most manufacturers will use the GaN-on-Si process for cost considerations, which will lead to defects, cracks and dislocations in the epitaxial growth of chips, which will lead to an increase in the dynamic on-resistance of GaN.

[0005] 3. In the application of switching power supply equipment, engineers need to design based on the accurate relevant specifications provided by semiconductor manufacturers. Understanding the accurate dynamic on-resistance parameters is of great significance for selecting device specifications, evaluating system losses, selecting switching frequencies, and clarifying equipment cooling system requirements.

[0006] At present, the industry usually uses a test method based on a half-bridge double pulse structure to detect the dynamic on-resistance of GaN power devices. This structure is described in patents with publication numbers CN115575713A and CN218099379U. The above detection method has the following main defects:

[0007] 1. The high-voltage stress time of the device under test in this device is controlled by the interval time between double pulses. However, due to the natural decay of the inductor current between double pulses, the double pulse detection method cannot evaluate the dynamic on-resistance change of the device under test at the rated test current after a long period of stress voltage (more than milliseconds);

[0008] 2. The double pulse test device causes the device under test to capture charge under the action of high voltage stress before the test cycle starts, and the captured charge is not reset before the test, which will seriously affect the control variables in the dynamic on-resistance characteristic evaluation and thus affect the reliability of the test results. Charge reset can be achieved by turning on the device under test after connecting to the power supply and before the test cycle starts to release the captured charge in the conduction channel;

[0009] 3. The double pulse detection device cannot evaluate the performance of the device under test after the continuous pulse is interrupted, which is exactly the main use scenario of the device under test. Although this point has been solved in patent CN116223916A, the device requires multiple test power supplies, circuit components and a more complex control method.

[0010] The limitations of current test equipment and test methods will lead to inaccurate characteristic evaluation of the dynamic on-resistance of GaN devices, which in turn affects the reliability of GaN devices in switching power supply equipment. Summary of the invention

[0011] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a test device and a test method for the dynamic on-resistance of a gallium nitride power device, which can more accurately evaluate the change in the dynamic on-resistance of gallium nitride caused by long-term high-voltage stress when the pre-charge is cleared, and can be used for characteristic evaluation and testing in both single pulse and continuous pulse modes.

[0012] The first object of the present invention is to provide a test device for dynamic on-resistance of a gallium nitride power device, comprising a DC power supply, a first drive switch, a second drive switch, a third drive switch, a device under test, a first diode, a second diode, a load inductor, a first capacitor and a second capacitor;

[0013] The first drive switch is connected in series with the first diode to form a first bridge arm, the third drive switch is connected in series with the device under test to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, the positive and negative electrodes of the DC power supply are respectively connected to the high-side switch and the low-side switch of the full-bridge circuit; the full-bridge circuit works in the form of a constant current source under single pulse or continuous pulse, providing relevant necessary conditions for testing;

[0014] The two ends of the second driving switch are respectively connected to the negative end of the load inductor and the negative electrode of the DC power supply, so as to provide an additional charging bypass for initializing the inductor current. The two ends of the second diode are respectively connected to the negative end of the load inductor and the neutral point of the second bridge arm, so as to decouple the inductor voltage and the stress voltage of the device under test.

[0015] Preferably, the first capacitor and the second capacitor are connected in parallel with a DC power supply to filter and provide high-frequency switching current.

[0016] Preferably, the first drive switch, the second drive switch, the third drive switch and the device under test are all equipped with an isolated drive control module, and the isolated drive control module is used to control the on and off of the drive switch or the device under test.

[0017] Preferably, the device further comprises a DUT voltage detection unit arranged in parallel at both ends of the device under test;

[0018] The DUT voltage detection unit includes a voltage probe with a clamping function and a high-voltage voltage probe, wherein the clamping voltage probe and the high-voltage voltage probe are respectively used for real-time detection of the dynamic voltage of the device under test in the on state and the high-voltage stress in the off state.

[0019] Preferably, the device further comprises an inductor current detection unit arranged in series between the load inductor and the second diode;

[0020] The inductor current detection unit is used for real-time detection of the load inductor current and the current of the device under test in a state of being connected in series with the load inductor.

[0021] A second object of the present invention is to provide a method for testing the dynamic on-resistance of the gallium nitride power device, comprising the following steps:

[0022] S1. Determine test requirements and test modes;

[0023] S2. According to the test requirements and test mode determined in step S1, setting the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase;

[0024] S3, according to the switch timing of each test stage set in step S2, the corresponding DUT charge reset period, DUT charge capture period and DUT charge escape period are operated in sequence, and when entering the DUT charge escape period, the dynamic voltage and current of the device under test are continuously sampled using the DUT voltage detection unit and the inductor current detection unit to obtain the on-state voltage and on-state current of the device under test;

[0025] S4. Determine the dynamic on-resistance of the device under test according to the on-voltage and on-current obtained in step S3.

[0026] Preferably, in step S1, the test requirements include the magnitude of high voltage stress, the time of high voltage stress, the test current amplitude and the test switching frequency; and the test mode includes a single pulse mode and a continuous pulse mode.

[0027] Preferably, in step S2, the test phase includes a DUT charge resetting period, a DUT charge capturing period and a DUT charge escape period.

[0028] Preferably, in step S2, when the test mode determined in step S1 is the single pulse mode, the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase is set as follows:

[0029] DUT charge reset period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch;

[0030] DUT charge capture period: turn on the third drive switch and turn off the device under test, while the first drive switch and the second drive switch remain turned off;

[0031] Turning on the first drive switch and the second drive switch, and keeping the third drive switch turned on and the device under test turned off;

[0032] DUT charge escape period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch.

[0033] Preferably, in step S2, when the test mode determined in step S1 is the continuous pulse mode, the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase is set as follows:

[0034] DUT charge reset period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch;

[0035] Keep the device under test turned on, and turn on the first drive switch, while the second drive switch and the third drive switch remain turned off;

[0036] DUT charge capture period: keep the second drive switch off, and continuously turn on and off the first drive switch, the third drive switch and the device under test at the test switching frequency; the PWM switch signal of the device under test is the same as that of the first drive switch, complementary to the third drive switch, and leaves appropriate dead time according to the device specifications. The dead time is determined by the switching characteristics of the device under test, and the PWM duty cycle is set to 0.5;

[0037] DUT charge escape period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] (1) The present invention provides an additional current bypass for inductor charging and discharging by controlling the first drive switch and the second drive switch, thereby solving the problem of limited high-voltage stress evaluation time caused by the natural decay of the inductor current between the double pulses in the double pulse test method, so that the dynamic on-resistance can be tested under long-term high-voltage stress, which is of great significance for understanding the maximum dynamic on-resistance increase of the device, the saturation charge capture amount and the degree of device defects.

[0040] (2) The present invention applies a full-bridge structure, so that the device under test can be turned on during the initialization period of the inductor current, and the captured charge is reset through the device conduction channel, ensuring that the dynamic on-resistance test of the device under test in single pulse and continuous pulse modes is carried out when the pre-charge is cleared, thereby ensuring the accuracy of the test initial conditions and control variables.

[0041] (3) The present invention uses a full-bridge structure to continuously turn on and off the device under test at a preset switching frequency and time, so that the change in dynamic on-resistance of the device under test after continuous operation at different switching voltages, switching currents and switching frequencies can be observed. At the same time, a single power supply and a relatively simple control method are used to evaluate the characteristics in both single pulse and continuous pulse modes, which has the advantages of low cost and easy use. The results have positive reference significance for semiconductor manufacturers and switching power supply equipment manufacturers. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic diagram of the structure of a test device for dynamic on-resistance of a gallium nitride power device provided by an embodiment of the present invention;

[0043] Figure 2 A timing waveform diagram of related signals in a single pulse mode of the test method provided by an embodiment of the present invention;

[0044] Figure 3 A timing waveform diagram of related signals in a continuous pulse mode of the test method provided by an embodiment of the present invention;

[0045] Figure 4 An example diagram of the measured waveform of the test method provided in the embodiment of the present invention in single pulse mode, with a test current of 10A, a high voltage stress of 400V, and a high voltage stress time of 10 microseconds;

[0046] Figure 5 The test method provided in the embodiment of the present invention is a graph showing the evaluation results of the dynamic on-resistance of the device under test GS66516T under different high voltage stress times in single pulse mode;

[0047] Figure 6An example diagram of the measured waveform of the test method provided in the embodiment of the present invention under the continuous pulse mode, with a high voltage stress of 400V, a test current of 10A, a switching frequency of 100kHz, and a high voltage stress time of 100 microseconds;

[0048] Figure 7 This is a graph showing evaluation results of the dynamic on-resistance of the device under test GS66516T at different continuous pulse times in the continuous pulse mode according to the test method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will be combined with the accompanying drawings of the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0050] Example 1

[0051] like Figure 1 As shown, an embodiment of the present invention provides a test device for the dynamic on-resistance of a gallium nitride power device, specifically comprising: a DC power supply, a first drive switch S1, a second drive switch S2, a third drive switch S3, a device under test S4, a first diode D1, a second diode D2, a load inductor L, a first capacitor C1 and a second capacitor C2; the first drive switch S1 is connected in series with the first diode D1 to form a first bridge arm, the third drive switch S3 is connected in series with the device under test S4 to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, and the positive and negative electrodes of the DC power supply are respectively connected to the high-side switch and the low-side switch of the full-bridge circuit. The positive end of the load inductor is connected to the neutral point of the first bridge arm. On the basis of the full-bridge circuit, the test device further introduces a second drive switch S2 and a second diode D2. The two ends of the second drive switch S2 are respectively connected to the negative end of the load inductor L and the negative electrode of the DC power supply to provide an additional current bypass for inductor current initialization. The two ends of the second diode D2 are connected to the negative end of the load inductor L and the neutral point of the second bridge arm respectively, which plays a role in decoupling the inductor voltage and the stress voltage of the device under test. The first capacitor C1 and the second capacitor C2 are connected in parallel with the DC power supply to play a role in filtering and providing high-frequency switching current.

[0052] The first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4 are all equipped with an isolated drive control module. The first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4 correspond to the isolated drive control module 1, the isolated drive control module 2, the isolated drive control module 3 and the isolated drive control module 4 respectively. The isolated drive control module 1, the isolated drive control module 2, the isolated drive control module 3 and the isolated drive control module 4 are respectively used to control the on and off of the first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4.

[0053] The device also includes a DUT voltage detection unit arranged in parallel at both ends of the device under test S4 and an inductor current detection unit arranged in series between the load inductor L and the second diode D2;

[0054] The DUT voltage detection unit includes a voltage probe with a clamping function and a high-voltage voltage probe, and the clamping voltage probe and the high-voltage voltage probe are used to detect the dynamic voltage of the device under test in the on state and the high-voltage stress in the off state in real time. The purpose of using the clamping voltage probe to test the on-voltage is to reduce the sampling quantization error caused by the excessive peak-to-peak value of the voltage of the device under test during the switching process.

[0055] The inductor current detection unit is used for real-time detection of the load inductor current and the current of the device under test in a state of being connected in series with the load inductor.

[0056] The DC power supply is a voltage-stabilized power supply whose rated value can meet the high voltage stress and test current amplitude requirements of the device under test.

[0057] In the embodiment of the present invention, the first drive switch S1 and the second drive switch S2 can use silicon-based MOSFET switch tubes to control the inductor current, and the third drive switch S3 uses the same gallium nitride device as the device under test S4 to ensure the uniformity of the bridge arm switch energy. The first diode D1 and the second diode D2 preferably use surface-mount silicon carbide Schottky diodes to minimize parasitic capacitance and stray inductance in the circuit, reduce current and voltage oscillations during the switching process, and increase the effective area of ​​dynamic on-resistance sampling.

[0058] Example 2

[0059] The embodiment of the present invention provides a method for testing the dynamic on-resistance of a gallium nitride power device based on the testing device provided in embodiment 1, which specifically includes the following steps:

[0060] S1. Determine test requirements and test modes; the test requirements include high voltage stress magnitude, high voltage stress time, test current amplitude and test switch frequency; the test modes include single pulse mode and continuous pulse mode;

[0061] S2. According to the test requirements and test mode determined in step S1, the switch timing of the first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4 in each test phase is set. The test phase includes a DUT charge reset period, a DUT charge capture period and a DUT charge escape period;

[0062] like Figure 2 As shown, when the test mode determined in step S1 is the single pulse mode, the switch timing of the first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4 in each test phase is set to:

[0063] DUT charge reset period: turn on the device under test S4, and turn off the first drive switch S1, the second drive switch S2, and the third drive switch S3; the device under test enters the charge reset period, during which the charge captured in the device defect will be released and cleared through the conduction channel. In this stage, it is recommended to leave enough charge initialization time according to the device specifications to ensure the accuracy of the test;

[0064] DUT charge capture period: turn on the third drive switch S3, turn off the device under test S4, and keep the first drive switch S1 and the second drive switch S2 turned off; the device under test enters the charge capture period, during which the charge that has not achieved energy level transition will be captured in the device defects and accumulate over time. The duration of the high voltage stress period is determined by the test requirements;

[0065] The first drive switch S1 and the second drive switch S2 are turned on, and the third drive switch S3 is kept on and the device under test S4 is turned off; at this time, the measurement circuit enters the current initialization stage, the DC power supply charges the load inductor, and the load current increases linearly. During this period, since the device under test is still under high voltage stress, the current initialization stage still belongs to the charge capture period.

[0066] DUT charge escape period: turn on the device under test S4, turn off the first drive switch S1, the second drive switch S2 and the third drive switch S3. The load current flows in a closed loop through the first diode D1, the second diode D2 and the device under test S4. At this time, the device under test S4 is in the charge escape period, and the charge captured in the DUT charge capture period is released through the conduction channel. During this period, the voltage detection unit and the current detection unit are used to sample the conduction voltage and current of the device under test.

[0067] like Figure 3 As shown, when the test mode determined in step S1 is the continuous pulse mode, the switch timing of the first drive switch S1, the second drive switch S2, the third drive switch S3 and the device under test S4 in each test phase is set to:

[0068] DUT charge reset period: turn on the device under test S4, and turn off the first drive switch S1, the second drive switch S2, and the third drive switch S3; the device under test enters the charge reset period, during which the charge captured in the device defect will be released and cleared through the conduction channel. In this stage, it is recommended to leave enough charge initialization time according to the device specifications to ensure the accuracy of the test;

[0069] Keep the device under test S4 turned on, and turn on the first drive switch S1, while the second drive switch S2 and the third drive switch S3 remain turned off; at this time, the measurement circuit enters the current initialization stage, the DC power supply charges the load inductor, and the load current increases linearly. The duration of the current initialization stage is determined by the inductance size and the test requirements. The initialization ends after the load current reaches the required amplitude. During this period, since the conduction channel of the device under test is in the open state, no charge is captured;

[0070] DUT charge capture period: keep the second drive switch S2 off, and continuously open and close the first drive switch S1, the third drive switch S3 and the device under test S4 at the test switch frequency; the PWM switch signal of the device under test S4 is the same as that of the first drive switch S1, complementary to the third drive switch S3, and reserves appropriate dead time according to the device specifications, and the duty cycle is set to 0.5; during this period, the device under test is in the charge capture period, and the length of time is determined by the test requirements.

[0071] DUT charge escape period: turn on the device under test S4, turn off the first drive switch S1, the second drive switch S2 and the third drive switch S3, and the device under test S4 enters the charge escape period; the on-state voltage and current sampling method of the device under test in the charge escape period is the same as that in the single pulse mode.

[0072] The on-state voltage sampling of the device under test S4 during the DUT charge escape period in the single pulse mode and the continuous pulse mode should use the voltage probe with a clamping function in the DUT voltage detection unit to reduce the sampling quantization error caused by the excessive peak-to-peak voltage of the device under test S4 during the switching process. Since the load inductor L and the device under test S4 are in series, the inductor current is the same as the on-state current of the device under test S4, and the current sampling of the device under test S4 can be performed through the inductor current detection unit. Since most gallium nitride devices use chip packaging, the current sampling method can reduce the switching current and voltage oscillations caused by the stray inductance introduced by the device current detection link, thereby improving the accuracy of sampling and dynamic on-state resistance evaluation, and reducing the difficulty of PCB design and the cost of using the device.

[0073] S3, according to the switch timing of each test phase set in step S2, respectively operate to enter the DUT charge reset period, DUT charge capture period and DUT charge escape period in sequence, and when entering the DUT charge escape period, use the DUT voltage detection unit and the inductor current detection unit to continuously sample the dynamic voltage and current of the device under test S4, respectively, to obtain the on-state voltage and on-state current of the device under test S4. The length of the continuous sampling time can refer to the switching cycle of the device under test in actual application;

[0074] S4, determining the dynamic on-resistance of the device under test S4 according to the on-voltage and on-current obtained in step S3. To evaluate the dynamic on-resistance of the device under test during the charge escape period, it is necessary to plot the dynamic change of the resistance value during this period according to the ratio of the continuously sampled current and voltage.

[0075] The test performance of the test device and test method provided in the embodiments of the present invention is verified below.

[0076] In the actual circuit test, the first drive switch S1 and the second drive switch S2 use MOSFET switch tubes (IPB65R110CFD7 650V / 22A) from Infineon, and the third drive switch unit S3 and the device under test S4 use gallium nitride switch tubes (GS66516T 650V / 60A) from GaN Systems. The first diode D1 and the second diode D2 use silicon carbide diodes (C4D10120E1.2kV / 33A) from Cree. The isolated drive control module uses the Si8271 isolation gate drive IC from Silicon Labs as the control chip. The clamp voltage probe of the DUT voltage detection unit uses the clamp voltage probe (CLP1500V15A1) from Springburo.

[0077] The test method provided by the present invention is in single pulse mode, with a test current of 10A, a high voltage stress of 400V, and a high voltage stress time of 10 microseconds. Figure 4 As shown, in Figure 4 In, V gs1 Refers to the gate voltage of the first drive switch S1, V gs4 Refers to the gate voltage of the device under test S4, V ds4 Refers to the voltage across the device S4 under test observed by the high-voltage probe, V ds4_Clamp Refers to the voltage across the device S4 under test observed by the clamp voltage probe. Figure 4 It can be seen that before t1, the test is in the DUT charge reset period, and the gate voltage V gs4At t1, the test enters the DUT charge capture period, and the gate voltage V gs4 is 0V, the device under test S4 is turned off, the third drive switch S3 is turned on, and the voltage V across the device under test S4 is ds4 The DC power supply voltage is 400V, the clamping voltage V ds4_Clamp The preset value is 2.5V. At t2, the test enters the inductor current initialization time, the first drive switch S1 and the second drive switch S2 are turned on, the inductor starts to charge, and the inductor current I L At t3, the charge capture period of the device under test S4 reaches the preset time of 10 microseconds, the test current reaches the preset value of 10A, the device under test S4 is turned on, and the test enters the DUT charge escape period. The conduction voltage V ds4_Clamp and the inductor current I L Sampling and calculating the dynamic on-resistance ratio, at this time, the device under test S4 is connected in series with the load inductor L, and the inductor current I L Equal to the on-state current of the device under test.

[0078] Figure 5 The test method provided by the present invention is used in single pulse mode to evaluate the dynamic on-resistance of the device under test GS66516T under different high voltage stress times. The test requirements of this embodiment are that the high stress time is 100 microseconds to 100 milliseconds, the test current is 10A, and the high voltage stress is 100V to 400V. Figure 5 The dynamic on-resistance R of the device S4 under test is shown when the charge escape period is 1 microsecond. ds (1μs) and rated resistance R dc ratio. Figure 5 The results show that when the high-voltage stress time is from 100 microseconds to 1 millisecond and the stress voltage is 400V, the increase in dynamic on-resistance compared to the rated resistance does not exceed 5%; when the stress time is from 1 millisecond to 10 milliseconds and the stress voltage is 400V, the dynamic on-resistance increases by about 24%; when the stress time is from 40 milliseconds to 100 milliseconds and the stress voltage is 400V, the increase ratio of dynamic on-resistance compared to the rated resistance gradually decreases, indicating that the number of trapped charges may have approached the saturation level. In addition, for stress voltages of 200V and 300V, the dynamic on-resistance of the device under test also shows a similar trend, while when the stress voltage is 100V, the growth rate of dynamic on-resistance under high-voltage stress time is relatively slow. Semiconductor manufacturers can refer to the test results of such embodiments to improve the epitaxial process and enhance product quality and reliability.

[0079] Figure 6The test method provided in the embodiment of the present invention is in the continuous pulse mode, the high voltage stress is 400V, the test current is 10A, the switching frequency is 250kHz, and the high voltage stress time is 100 microseconds. The measured waveform example diagram is shown in Figure 6 In, V gs1 Refers to the gate voltage of the first drive switch S1, V gs4 Refers to the gate voltage of the device under test S4, V ds4 Refers to the voltage across the device S4 under test observed by the high-voltage probe, V ds4_Clamp Refers to the voltage across the device S4 under test observed by the clamp voltage probe. Figure 6 It can be seen that before t1, the test is in the DUT charge reset period, and the gate voltage V gs4 6V, the device under test S4 is turned on, and the pre-charge is cleared. In the interval t0 to t1, the test enters the current initialization stage, the first drive switch S1 is turned on, and the gate voltage V gs1 The inductor is charged to 6V, and the current increases to 10A. In the interval t1 to t2, the test enters the DUT charge capture period. The circuit works in the full-bridge constant current source mode with a switching frequency of 250kHz. The switch voltage V ds4 The peak-to-peak value is the DC power supply voltage of 400V, the inductor current I L The average value is 10A. At t3, the charge capture period of the device under test S4 reaches the preset time of 100 microseconds, the device under test S4 is turned on, and the test enters the DUT charge escape period. The conduction voltage V ds4_Clamp and the inductor current I L Sampling and calculating the dynamic on-resistance ratio, at this time, the device under test S4 is connected in series with the load inductor, and the inductor current I L Equal to the conduction current of device S4 under test.

[0080] Figure 7 The test method provided by the present invention is a graph showing the evaluation results of the dynamic on-resistance of the device under test GS66516T under continuous pulse mode at different continuous switching times. The test requirements of this embodiment are high stress time of 100 microseconds to 100 milliseconds, test current of 10A, high voltage stress of 100V to 400V, and switching frequency of 250kHz. Figure 7 The dynamic on-resistance R of the device under test when the charge escape period is 1 microsecond ds (1μs) and rated resistance R dc The ratio of Figure 5The comparison of the results shows that after continuous operation, the increase in the dynamic on-resistance of the device S4 under test at the same charge capture time is more significant, indicating that the switching process causes a more obvious charge capture phenomenon than the normal high-voltage stress, and this phenomenon becomes more significant on a time scale of 10 milliseconds to 100 milliseconds. Switching power supply equipment manufacturers can refer to the test results of such embodiments to select appropriate device specifications, estimate system losses, and clarify the cooling system requirements of the equipment.

[0081] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for testing the dynamic on-resistance of a gallium nitride power device, characterized in that: The test method is implemented by a test device for dynamic on-resistance of a gallium nitride power device, and the test device for dynamic on-resistance of a gallium nitride power device includes a direct current power supply, a first drive switch, a second drive switch, a third drive switch, a device under test, a first diode, a second diode, a load inductor, a first capacitor, and a second capacitor; The first drive switch is connected in series with the first diode to form a first bridge arm, the third drive switch is connected in series with the device under test to form a second bridge arm, the first bridge arm and the second bridge arm are connected in parallel to form a full-bridge circuit, and the positive and negative electrodes of the DC power supply are respectively connected to the high-side switch and the low-side switch of the full-bridge circuit; One end of the load inductor is connected to the neutral point of the first bridge arm; Two ends of the second driving switch are respectively connected to the other end of the load inductor and the negative electrode of the DC power supply, so as to provide an additional charging bypass for initializing the inductor current; Two ends of the second diode are respectively connected to the other end of the load inductor and the neutral point of the second bridge arm, so as to decouple the inductor voltage and the stress voltage of the device under test; The first capacitor and the second capacitor are connected in parallel with the DC power supply to filter and provide high-frequency switching current; The method for testing the dynamic on-resistance of a gallium nitride power device comprises the following steps: S1. Determine test requirements and test modes; The test requirements include the magnitude of high voltage stress, the duration of high voltage stress, the test current amplitude and the test switching frequency; the test modes include a single pulse mode and a continuous pulse mode; S2. According to the test requirements and test mode determined in step S1, setting the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase; The test phase includes a DUT charge reset period, a DUT charge capture period, and a DUT charge escape period; When the test mode determined in step S1 is the single pulse mode, the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase is set as follows: DUT charge reset period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch; DUT charge capture period: turn on the third drive switch and turn off the device under test, while the first drive switch and the second drive switch remain turned off; Turning on the first drive switch and the second drive switch, and keeping the third drive switch turned on and the device under test turned off; DUT charge escape period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch; S3, according to the switch timing of each test stage set in step S2, the corresponding DUT charge reset period, DUT charge capture period and DUT charge escape period are operated in sequence, and when entering the DUT charge escape period, the dynamic voltage and current of the device under test are continuously sampled using the DUT voltage detection unit and the inductor current detection unit to obtain the on-state voltage and on-state current of the device under test; S4. Determine the dynamic on-resistance of the device under test according to the on-voltage and on-current obtained in step S3.

2. The method for testing the dynamic on-resistance of a gallium nitride power device according to claim 1, characterized in that: The first drive switch, the second drive switch, the third drive switch and the device under test are all equipped with an isolated drive control module, and the isolated drive control module is used to control the on and off of the drive switch or the device under test.

3. The method for testing the dynamic on-resistance of a gallium nitride power device according to claim 1, characterized in that: The device also includes a DUT voltage detection unit arranged in parallel at both ends of the device under test; The DUT voltage detection unit includes a clamping voltage probe with a clamping function and a high-voltage voltage probe, wherein the clamping voltage probe and the high-voltage voltage probe are respectively used for real-time detection of the dynamic voltage of the device under test in the on state and the high-voltage stress in the off state.

4. The method for testing the dynamic on-resistance of a gallium nitride power device according to claim 1, characterized in that: The device also includes an inductor current detection unit arranged in series between the load inductor and the second diode; The inductor current detection unit is used to detect the load inductor current and the current of the device under test in real time.

5. The method for testing the dynamic on-resistance of a gallium nitride power device according to claim 1, characterized in that: In step S2, when the test mode determined in step S1 is the continuous pulse mode, the switch timing of the first drive switch, the second drive switch, the third drive switch and the device under test in each test phase is set as follows: DUT charge reset period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch; Keep the device under test turned on, turn on the first drive switch, and keep the second drive switch and the third drive switch turned off; DUT charge capture period: keep the second drive switch off, and continuously turn on and off the first drive switch, the third drive switch and the device under test at the test switch frequency; the PWM switch signal of the device under test is the same as that of the first drive switch, complementary to the third drive switch, and leaves appropriate dead time according to the device specifications, and the duty cycle is set to 0.5; DUT charge escape period: turn on the device under test, and turn off the first drive switch, the second drive switch, and the third drive switch.

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