Display screen, crack detection method and display

Abstract

The embodiments of the present application provide a display screen, a crack detection method, and a display, comprising: a signal source chip, a crack detection signal circuit partially arranged at the edge of the display screen, multiple pixel rows, a switch tube corresponding to each pixel row, and a gate drive circuit corresponding to each pixel row; the signal source chip is used to output a third clock signal when crack detection is performed on the edge of the display screen, and transmit the third clock signal to the first end of each switch tube through the crack detection signal circuit; the signal source chip is also used to output a first control signal to the control end of each switch tube when crack detection is performed on the edge of the display screen; the switch tube is used to output the third clock signal to the clock signal end of the gate drive circuit connected to itself by conducting between its first and second ends when its control end receives the first control signal. This improves the service life of the display product.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display screen, a crack detection method, and a display. Background Art

[0002] In current OLED (Organic Light-Emitting Diode) display screens, cracks are prone to occur on the edges due to process, materials, usage scenarios, etc. If cracks on the edges of OLED display screens cannot be detected in time, it may affect the service life of the display product. Summary of the Invention

[0003] The purpose of the embodiments of the present application is to provide a display screen, a crack detection method, and a display to extend the service life of the display product. The specific technical solution is as follows:

[0004] In a first aspect, an embodiment of the present application provides a display screen, comprising:

[0005] A signal source chip, a crack detection signal circuit partially arranged at the edge of the display screen, a plurality of pixel rows, a switch tube corresponding to each pixel row, and a gate drive circuit corresponding to each pixel row;

[0006] For each pixel row, the crack detection signal output end of the signal source chip is connected to the first end of the switch tube corresponding to the pixel row through the crack detection signal circuit, and the second end of the switch tube corresponding to the pixel row is connected to the clock signal end of the gate drive circuit corresponding to the pixel row;

[0007] For each pixel row, the pixel row is connected to the output terminal of its corresponding gate drive circuit;

[0008] The signal source chip is configured to output a third clock signal through its own crack detection signal output terminal when crack detection is performed on the edge of the display screen, and transmit the third clock signal to the first terminal of each of the switching transistors through the crack detection signal circuit;

[0009] The signal source chip is further configured to output a first control signal to the control end of each of the switch tubes through its own control signal output end when crack detection is performed on the edge of the display screen;

[0010] The switch tube is used to output the third clock signal to the clock signal end of the gate drive circuit connected to itself by conducting between its first end and second end when its control end receives the first control signal.

[0011] In a possible implementation, the crack detection signal circuit includes a first crack detection signal sub-circuit and a second crack detection signal sub-circuit;

[0012] The first crack detection signal sub-circuit and the second crack detection signal sub-circuit are arranged in the crack detection area of ​​the display screen; the crack detection area is located at the edge and the middle of the display screen, the fourth part of the crack detection area is located on the side where the signal source chip is located, the first part of the crack detection area is located on the side away from the signal source chip, the second part, the third part and the fifth part of the crack detection area are perpendicular to the first part and the fourth part, and the second part and the third part are located on both sides of the display screen, and the fifth part is located in the middle of the display screen.

[0013] In a possible implementation, the switch tube includes a first sub-switch tube and a second sub-switch tube, and the gate drive circuit includes a first gate drive sub-circuit and a second gate drive sub-circuit;

[0014] In the row direction of the display screen, for each pixel row, a first gate driving sub-circuit and a first sub-switch tube corresponding to the pixel row are provided on one side of the pixel row, and a second gate driving sub-circuit and a second sub-switch tube corresponding to the pixel row are provided on the other side of the pixel row;

[0015] For each pixel row, the crack detection signal output end of the signal source chip is connected to the first end of the first sub-switch tube corresponding to the pixel row through the first crack detection signal sub-circuit, and the second end of the first sub-switch tube corresponding to the pixel row is connected to the clock signal end of the first gate drive sub-circuit corresponding to the pixel row. The crack detection signal output end of the signal source chip is connected to the first end of the second sub-switch tube corresponding to the pixel row through the second crack detection signal sub-circuit, and the second end of the second sub-switch tube corresponding to the pixel row is connected to the clock signal end of the second gate drive sub-circuit corresponding to the pixel row.

[0016] For each pixel row, one side of the pixel row is connected to the output end of the first gate driving sub-circuit corresponding to the pixel row, and the other side of the pixel row is connected to the output end of the second gate driving sub-circuit corresponding to the pixel row;

[0017] The signal source chip is specifically configured to output a third clock signal through its own crack detection signal output terminal when crack detection is performed on the edge of the display screen, transmit the third clock signal to the first terminal of each of the first sub-switching transistors through the first crack detection signal sub-circuit, and transmit the third clock signal to the first terminal of each of the second sub-switching transistors through the second crack detection signal sub-circuit;

[0018] The signal source chip is further specifically configured to output a first control signal to the control end of each of the first sub-switching tubes and the control end of each of the second sub-switching tubes through its own control signal output end when crack detection is performed on the edge of the display screen;

[0019] The first sub-switch tube is configured to output the third clock signal to the clock signal terminal of the first gate drive sub-circuit connected to the first sub-switch tube by conducting between the first terminal and the second terminal when the control terminal thereof receives the first control signal;

[0020] The second sub-switch tube is used to output the third clock signal to the clock signal end of the second gate drive sub-circuit connected to itself by conducting between its first end and second end when its control end receives the first control signal.

[0021] In a possible implementation, the display screen further includes a first clock signal circuit and a second clock signal circuit;

[0022] For each pixel row, the first clock signal output terminal of the signal source chip is connected to the clock signal terminal of the first gate driving sub-circuit corresponding to the pixel row through the first clock signal circuit, and the second clock signal output terminal of the signal source chip is connected to the clock signal terminal of the second gate driving sub-circuit corresponding to the pixel row through the second clock signal circuit;

[0023] The signal source chip is further configured to, when the display screen is operating normally, output a first clock signal through its own first clock signal output terminal, and transmit the first clock signal to the clock signal terminal of each of the first gate drive sub-circuits through the first clock signal circuit; output a second clock signal through its own second clock signal output terminal, and transmit the second clock signal to the clock signal terminal of each of the second gate drive sub-circuits through the second clock signal circuit;

[0024] The first clock signal and the second clock signal are the same clock signal.

[0025] In one possible implementation,

[0026] The signal source chip is further configured to output a second control signal to the control end of each of the first sub-switching tubes and the control end of each of the second sub-switching tubes through its own control signal output end when the display screen is operating normally, so as to disconnect the first end and the second end of each of the first sub-switching tubes and disconnect the first end and the second end of each of the second sub-switching tubes.

[0027] In a possible implementation manner, the third clock signal is the same clock signal as the first clock signal and the second clock signal.

[0028] In a possible implementation manner, the third clock signal is a positive phase clock signal GCK, the first clock signal is a positive phase clock signal GCK, and the second clock signal is a positive phase clock signal GCK;

[0029] or;

[0030] The third clock signal is an inverted clock signal GCB, the first clock signal is an inverted clock signal GCB, and the second clock signal is an inverted clock signal GCB.

[0031] In one possible implementation,

[0032] The signal source chip is further used to perform high-impedance processing on the first clock signal output end and the second clock signal output end when crack detection is performed on the edge of the display screen.

[0033] In one possible implementation,

[0034] The signal source chip is further used to perform high-impedance processing on the crack detection signal output end when the display screen is working normally.

[0035] In one possible implementation,

[0036] The first end of the first crack detection signal sub-circuit is connected to the first voltage terminal of the signal source chip, and the second end of the first crack detection signal sub-circuit is connected to the crack detection signal output terminal of the signal source chip;

[0037] The first end of the second crack detection signal sub-circuit is connected to the second voltage terminal of the signal source chip, and the second end of the second crack detection signal sub-circuit is connected to the crack detection signal output terminal of the signal source chip;

[0038] A potential difference is formed between the crack detection signal output terminal and the first voltage terminal;

[0039] A potential difference is formed between the crack detection signal output terminal and the second voltage terminal.

[0040] In a second aspect, an embodiment of the present application provides a crack detection method for detecting a display screen according to any one of the first aspects above, the method comprising:

[0041] Obtaining the current display brightness of each pixel row of the display screen and the normal display brightness of the display screen;

[0042] When there is a brightness difference between the display brightness of the Nth row of pixels and the N+1th row of pixels, and the brightness difference is greater than a preset difference threshold, or when there is a brightness difference between pixel units in the same row of pixels, or when the current display brightness of the display screen is uniform but there is a brightness difference between the current display brightness of the display screen and the normal display brightness of the display screen, it is determined that a crack has occurred at the edge of the display screen; wherein N is an integer not less than 1.

[0043] In a third aspect, an embodiment of the present application provides a display, comprising a display screen as described in any one of the first aspects above.

[0044] Beneficial effects of the embodiments of the present application:

[0045] The embodiments of the present application provide a display screen, a crack detection method, and a display. The display screen includes: a signal source chip, a crack detection signal circuit partially arranged at the edge of the display screen, a plurality of pixel rows, a switch tube corresponding to each pixel row, and a gate drive circuit corresponding to each pixel row; for each pixel row, the crack detection signal output end of the signal source chip is connected to the first end of the switch tube corresponding to the pixel row through the crack detection signal circuit, and the second end of the switch tube corresponding to the pixel row is connected to the clock signal end of the gate drive circuit corresponding to the pixel row; for each pixel row, the pixel row is connected to the output of the gate drive circuit corresponding to itself. end connection; a signal source chip, used to output a third clock signal through its own crack detection signal output end when crack detection is performed on the edge of the display screen, and transmit the third clock signal to the first end of each switch tube through the crack detection signal line; the signal source chip is also used to output a first control signal to the control end of each switch tube through its own control signal output end when crack detection is performed on the edge of the display screen; the switch tube is used to, when receiving the first control signal at its own control end, conduct between its own first end and second end, and output the third clock signal to the clock signal end of the gate drive circuit connected to itself. When a crack occurs on the edge of the display screen, the crack detection signal circuit also breaks. Only the normal part of the crack detection signal circuit before the break position can receive the third clock signal. The part of the crack detection signal circuit after the break position cannot receive the third clock signal, and therefore cannot transmit the third clock signal to the switch tube connected to itself. The gate drive circuit connected to these switch tubes will also not receive the third clock signal and cannot generate a normal output signal. The display screen will display abnormally. By observing the abnormal display of the display screen, the crack on the edge of the display screen can be detected, and timely measures can be taken to carry out maintenance, thereby ensuring the normal use of the display product and improving the service life of the display product.

[0046] Of course, it is not necessary to achieve all the advantages described above at the same time when implementing any product or method of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0048] Figure 1a A schematic diagram of the first structure of a display screen provided in an embodiment of the present application;

[0049] Figure 1b A second structural diagram of a display screen provided in an embodiment of the present application;

[0050] Figure 2 A third structural diagram of a display screen provided in an embodiment of the present application;

[0051] Figure 3a A fourth structural diagram of a display screen provided in an embodiment of the present application;

[0052] Figure 3b A fifth structural diagram of a display screen provided in an embodiment of the present application;

[0053] Figure 3c A sixth structural diagram of a display screen provided in an embodiment of the present application;

[0054] Figure 3d A seventh structural diagram of a display screen provided in an embodiment of the present application;

[0055] Figure 3e This is a schematic diagram of an eighth structure of a display screen provided in an embodiment of the present application;

[0056] Figure 3f A ninth structural diagram of a display screen provided in an embodiment of the present application;

[0057] Figure 3g A tenth structural diagram of a display screen provided in an embodiment of the present application;

[0058] Figure 4 This is a schematic diagram of the eleventh structure of the display screen provided in an embodiment of the present application;

[0059] Figure 5 This is a twelfth structural diagram of the display screen provided in an embodiment of the present application;

[0060] Figure 6A schematic diagram of a process flow of a crack detection method provided in an embodiment of the present application;

[0061] Figure 7 A schematic diagram of the structure of a display provided in an embodiment of the present application;

[0062] Figure 8 A schematic structural diagram of a pixel circuit in related art;

[0063] Figure 9a for Figure 3b A schematic diagram of the display state of the display screen shown;

[0064] Figure 9b for Figure 3c A schematic diagram of the display status of the display screen is shown. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0066] In current OLED (Organic Light-Emitting Diode) display screens, cracks are prone to appearing on the edges due to factors such as process, materials, and usage scenarios. If cracks on the edges of OLED display screens cannot be detected in time, the service life of the display product may be affected.

[0067] OLED foldable displays are particularly prone to cracking in their bend zones after tens of thousands of folds. To evaluate the performance of OLED foldable display products in this zone, it's necessary to precisely locate the cracks to see if they occur within the bend zone. Related technologies typically employ resistance detection and bright line detection to detect cracks along the edges of OLED foldable displays. However, these methods can only detect the presence of cracks, but cannot pinpoint their location, resulting in low crack detection accuracy.

[0068] In order to solve at least one of the above problems, embodiments of the present application provide a display screen, a crack detection method, and a display.

[0069] First, the display screen 1 provided in the embodiment of the present application is described in detail, see Figure 1a , the display screen 1 includes:

[0070] A signal source chip 11, a crack detection (PCD, Panel Crack Detection) signal circuit 12 partially arranged at the edge of the display screen 1, a plurality of pixel rows 13, a switch tube 14 corresponding to each pixel row 13, and a gate drive circuit 15 corresponding to each pixel row 13;

[0071] For each pixel row 13, the crack detection signal output terminal PCD-Output of the signal source chip 11 is connected to the first terminal of the switch tube 14 corresponding to the pixel row 13 through the crack detection signal circuit 12, and the second terminal of the switch tube 14 corresponding to the pixel row 13 is connected to the clock signal terminal of the gate drive circuit 15 corresponding to the pixel row 13;

[0072] For each pixel row 13, the pixel row 13 is connected to the output end of the gate driving circuit 15 corresponding to itself;

[0073] The signal source chip 11 is configured to output a third clock signal through its own crack detection signal output terminal PCD-Output when crack detection is performed on the edge of the display screen 1, and transmit the third clock signal to the first terminal of each of the switch tubes 14 through the crack detection signal circuit 12;

[0074] The signal source chip 11 is further configured to output a first control signal to the control end of each of the switch tubes 14 through its own control signal output end when crack detection is performed on the edge of the display screen 1 ;

[0075] The switch tube 14 is used to output the third clock signal to the clock signal terminal of the gate drive circuit 15 connected to itself by conducting between its first terminal and second terminal when its control terminal receives the first control signal.

[0076] The third clock signal is the same as the clock signal used by the gate drive circuit 15 when the display screen 1 is operating normally (crack detection is not performed on the edge of the display screen 1), except that the third clock signal is output by the crack detection signal output terminal PCD-Output of the signal source chip 11. The clock signal used by the gate drive circuit 15 when the display screen 1 is operating normally can be output by the clock signal output terminal of the signal source chip 11.

[0077] When crack detection is performed on the edge of the display screen 1, the clock signal output end of the signal source chip 11 can be subjected to high impedance processing (HiZ, High Impedance Zone). The crack detection signal output end PCD-Output is responsible for outputting the clock signal required by the gate drive circuit 15. The crack detection signal circuit 12 and the conduction of each switch tube 14 are then used to detect whether a crack occurs on the edge of the display screen 1.

[0078] A high-impedance state occurs when a signal in a circuit has no low-impedance path to either VDD (the positive power supply) or VSS (the negative power supply). Because the impedance of the signal's path to either VDD or VSS is so high, neither VDD or VSS can affect it, leaving the signal's voltage level floating in the air. This is called a high-impedance state (HiZ).

[0079] If the edge of the display screen 1 is cracked, the crack detection signal circuit 12 is also broken. Figure 1b , only the normal crack detection signal line in front of the fracture position can receive the third clock signal, and the crack detection signal line behind the fracture position cannot receive the third clock signal, and cannot transmit the third clock signal to the switch tube 14 connected to itself. The gate drive circuit 15 connected to these switch tubes 14 will also not receive the third clock signal, and cannot generate a normal output signal Gout to the corresponding pixel row 13 (the output signal Gout of the output end of the gate drive circuit 15 is given to the gate scanning signal Gate line of the corresponding pixel row 13, and the gate scanning signal Gate line is used to provide the gate scanning signal Gate to each pixel circuit of the pixel row 13), and the display screen 1 displays abnormally.

[0080] If there is no crack on the edge of the display screen 1, the crack detection signal circuit 12 will not be broken. The third clock signal can replace the clock signal used by the gate drive circuit 15 when the display screen 1 is working normally. The gate drive circuit 15 corresponding to each row of pixels 13 can normally generate the output signal Gout, and the display screen 1 displays normally.

[0081] When the display screen 1 is operating normally, each switch tube 14 is in the off state under the control of the signal source chip 11, and the crack detection signal output terminal PCD-Output is subjected to high-impedance processing, and the clock signal used by the gate drive circuit 15 is normally output by the clock signal output terminal. That is to say, the working state of the display screen 1 at this time is the same as the working state of the display screen in the related art.

[0082] In an embodiment of the present application, when a crack occurs at the edge of the display screen 1, the crack detection signal circuit 12 also breaks. Only the normal part of the crack detection signal circuit before the break position can receive the third clock signal, and the part of the crack detection signal circuit after the break position cannot receive the third clock signal, and therefore cannot transmit the third clock signal to the switch tube 14 connected to itself. The gate drive circuit 15 connected to these switch tubes 14 will also not receive the third clock signal, and cannot generate a normal output signal Gout to the corresponding pixel row 13. The display screen 1 displays abnormally. By observing the abnormal display of the display screen 1, the crack at the edge of the display screen 1 is detected, and timely measures are taken to perform maintenance, thereby ensuring the normal use of the display product and improving the service life of the display product.

[0083] In one possible implementation, see Figure 2 , the crack detection signal circuit 12 includes a first crack detection signal sub-circuit 121 and a second crack detection signal sub-circuit 122;

[0084] The first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122 are arranged in the crack detection area 16 of the display screen 1; the crack detection area 16 is located at the edge and the middle of the display screen 1, the fourth part 164 of the crack detection area 16 is located on the side where the signal source chip 11 is located, the first part 161 of the crack detection area 16 is located on the side away from the signal source chip 11, the second part 162, the third part 163, and the fifth part 165 of the crack detection area 16 are perpendicular to the first part 161 and the fourth part 164, and the second part 162 and the third part 163 are located on both sides of the display screen 1, and the fifth part 165 is located in the middle of the display screen 1.

[0085] The crack detection signal output terminal PCD-Output of the signal source chip 11 is respectively connected to the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122, and the part of the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122 connected to the crack detection signal output terminal PCD-Output is set in the middle position of the display screen to ensure the equality of the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122, and ensure the equality of the two signal transmissions.

[0086] In one possible implementation, see Figure 3a The switch tube 14 includes a first sub-switch tube 141 and a second sub-switch tube 142 , and the gate drive circuit 15 includes a first gate drive sub-circuit 151 and a second gate drive sub-circuit 152 ;

[0087] In the row direction of the display screen 1, for each pixel row 13, a first gate driving sub-circuit 151 and a first sub-switch transistor 141 are provided on one side of the pixel row 13, and a second gate driving sub-circuit 152 and a second sub-switch transistor 142 are provided on the other side of the pixel row 13;

[0088] For each pixel row 13, the crack detection signal output terminal PCD-Output of the signal source chip 11 is connected to the first end of the first sub-switch tube 141 corresponding to the pixel row 13 through the first crack detection signal sub-circuit 121, and the second end of the first sub-switch tube 141 corresponding to the pixel row 13 is connected to the clock signal end of the first gate drive sub-circuit 151 corresponding to the pixel row 13. The crack detection signal output terminal PCD-Output of the signal source chip 11 is connected to the first end of the second sub-switch tube 142 corresponding to the pixel row 13 through the second crack detection signal sub-circuit 122, and the second end of the second sub-switch tube 142 corresponding to the pixel row 13 is connected to the clock signal end of the second gate drive sub-circuit 152 corresponding to the pixel row 13;

[0089] For each pixel row 13, one side of the pixel row 13 is connected to the output end of the first gate driving sub-circuit 151 corresponding to the pixel row 13, and the other side of the pixel row 13 is connected to the output end of the second gate driving sub-circuit 152 corresponding to the pixel row 13;

[0090] The signal source chip 11 is specifically configured to output a third clock signal through its own crack detection signal output terminal PCD-Output when crack detection is performed on the edge of the display screen 1, transmit the third clock signal to the first terminal of each of the first sub-switches 141 through the first crack detection signal sub-circuit 121, and transmit the third clock signal to the first terminal of each of the second sub-switches 142 through the second crack detection signal sub-circuit 122;

[0091] The signal source chip 11 is further specifically configured to output a first control signal to the control end of each of the first sub-switches 141 and the control end of each of the second sub-switches 142 through its own control signal output end when crack detection is performed on the edge of the display screen 1;

[0092] The first sub-switch tube 141 is configured to output the third clock signal to the clock signal terminal of the first gate drive sub-circuit 151 connected to the first sub-switch tube 141 by conducting between the first terminal and the second terminal when the first sub-switch tube 141 receives the first control signal at the control terminal thereof;

[0093] The second sub-switch tube 142 is used to output the third clock signal to the clock signal terminal of the second gate drive sub-circuit 152 connected to itself by conducting between its first terminal and second terminal when its control terminal receives the first control signal.

[0094] In one example, if a crack occurs in the second portion 162 of the crack detection region 16, and no crack occurs in the first portion 161 or the third portion 163 of the crack detection region 16, then the first crack detection signal sub-circuit 121 is broken. Figure 3b Only the normal first crack detection signal sub-circuit before the fracture position can receive the third clock signal, and the first crack detection signal sub-circuit after the fracture position cannot receive the third clock signal, and thus cannot transmit the third clock signal to the first sub-switch tube 141 connected to itself. The first gate drive circuit 151 connected to these first sub-switch tubes 141 will also not receive the third clock signal, and cannot generate a normal output signal Gout to the corresponding pixel row 13 (the output signal Gout of the output end of the first gate drive circuit 151 and the second gate drive circuit 152 is given to the gate scanning signal Gate line of the corresponding pixel row 13, and the gate scanning signal Gate line is used to provide the gate scanning signal Gate to each pixel circuit of the pixel row 13). The structural diagram of the pixel circuit can be seen in FIG. Figure 8 (Using a pixel circuit with a 7T1C structure as an illustration, there are 7 transistors TFT, Thin-Film Transistor, and 1 capacitor C). In the pixel circuits of these pixel rows 13 that cannot receive the normal output signal Gout, the data voltage Data cannot be written into the N2 node. The N2 node is at a negative voltage when not charged. After the positive data voltage Data is written into the N2 node, the negative voltage of the N2 node is raised toward zero voltage. If the data voltage Data cannot be written into the N2 node, the N2 node is in a negative voltage state, and the T2 transistor is opened more completely. Therefore, the brightness of the display area where these pixel rows 13 that cannot receive the normal output signal Gout are located is abnormally high. Figure 8 In the figure, VDD is the positive voltage terminal of the power supply, and VSS is the negative voltage terminal of the power supply.

[0095] However, since no cracks occur in the first part 161 and the third part 163 of the crack detection area 16, the second crack detection signal sub-circuit 122 is not broken, and the third clock signal can still be transmitted to each second sub-switch tube 142 through the second crack detection signal sub-circuit 122. The second gate drive sub-circuit 152 corresponding to each row of pixels 13 can receive the third clock signal and normally generate the output signal Gout (in the row direction of the display screen 1, in the order from the third part 163 to the second part 162, the output signal Gout gradually decays on the gate scanning signal Gate line).

[0096] Furthermore, in the row direction of the display screen 1, for each pixel row 13, the pixel row 13 and its corresponding first gate driver sub-circuit 151 and first sub-switch tube 141 are arranged in the same row, and the pixel row 13 and its corresponding second gate driver sub-circuit 152 and second sub-switch tube 142 are arranged in the same row. Therefore, in the row direction of the display screen 1, in the order from the third portion 163 to the second portion 162, the display area after the break position of the first crack detection signal sub-circuit 121 gradually brightens (the area near the third portion 163 displays normally, and the area near the second portion 162 has abnormally high brightness). The display area before the break position of the first crack detection signal sub-circuit 121 displays normally. At this time, the display screen 1 will have a dividing line, which can be seen in FIG. Figure 9a Below the dividing line is a display area that gradually brightens in the order from the third part 163 to the second part 162, and above the dividing line is a display area that displays normally. The specific location where the crack occurs can be known through this dividing line. The position of the dividing line corresponding to the second part 162 is the specific location where the crack occurs.

[0097] In one example, if a crack occurs in the third portion 163 of the crack detection region 16, and no crack occurs in the first portion 161 or the second portion 162 of the crack detection region 16, then the second crack detection signal sub-circuit 122 is broken. Figure 3c, only the normal second crack detection signal sub-circuit before the fracture position can receive the third clock signal, and the second crack detection signal sub-circuit after the fracture position cannot receive the third clock signal, and thus cannot transmit the third clock signal to the second sub-switch tube 142 connected to itself. The second gate drive circuit 152 connected to these second sub-switch tubes 142 will also not receive the third clock signal, and cannot generate a normal output signal Gout to the corresponding pixel row 13 (the output signal Gout of the output end of the first gate drive circuit 151 and the second gate drive circuit 152 is given to the gate scanning signal Gate line of the corresponding pixel row 13, and the gate scanning signal Gate line is used to provide the gate scanning signal Gate to each pixel circuit of the pixel row 13). The structural diagram of the pixel circuit can be seen in Figure 8 In the pixel circuits of these pixel rows 13 that cannot receive the normal output signal Gout, the data voltage Data cannot be written into the N2 node. The N2 node is at a negative voltage when not charged. After the positive data voltage Data is written into the N2 node, the negative voltage of the N2 node is raised toward zero voltage. If the data voltage Data cannot be written into the N2 node, the N2 node is in a negative voltage state, and the T2 transistor is opened more completely. Therefore, the brightness of the display area where these pixel rows 13 that cannot receive the normal output signal Gout are located is abnormally high.

[0098] However, since no cracks occur in the first part 161 and the second part 162 of the crack detection area 16, the first crack detection signal sub-circuit 121 is not broken, and the third clock signal can still be transmitted to each first sub-switch tube 141 through the first crack detection signal sub-circuit 121. The first gate driving sub-circuit 151 corresponding to each row of pixel rows 13 can receive the third clock signal and generate the output signal Gout normally. In the row direction of the display screen 1, for each row of pixel rows 13, the pixel row 13 and its corresponding first gate driving sub-circuit 151 and first sub-switch tube 141 are arranged on the same row, and the pixel row 13 and its corresponding second gate driving sub-circuit 152 and second sub-switch tube 142 are arranged on the same row.

[0099] Therefore, in the row direction of the display screen 1, in the order from the second part 162 to the third part 163, the display area after the break position of the second crack detection signal sub-circuit 122 gradually becomes brighter (the area close to the second part 162 is displayed normally, and the area close to the third part 163 is abnormally brighter), and the display area before the break position of the second crack detection signal sub-circuit 122 is displayed normally. At this time, the display screen 1 will have a dividing line, which can be seen Figure 9bBelow the dividing line is a display area that gradually brightens in the order from the second part 162 to the third part 163, and above the dividing line is a display area that displays normally. The specific location of the crack can be known through this dividing line.

[0100] In one example, if cracks occur in both the second portion 162 and the third portion 163 of the crack detection region 16, and no cracks occur in the first portion 161 of the crack detection region 16, then both the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122 are broken. Figure 3d , the normal first crack detection signal sub-circuit before the first fracture position can receive the third clock signal, and the normal first crack detection signal sub-circuit after the first fracture position cannot receive the third clock signal; the normal second crack detection signal sub-circuit before the second fracture position can receive the third clock signal, and the normal second crack detection signal sub-circuit after the second fracture position cannot receive the third clock signal. In the row direction of the display screen 1, the display screen 1 will have two dividing lines (see Figure 3d , first dividing line and second dividing line). Above the first dividing line is a display area with normal display. Below the first dividing line and above the second dividing line is a display area that gradually brightens in the order from third portion 163 to second portion 162. Below the second dividing line is a display area with relatively high overall display brightness. These two dividing lines can be used to determine the specific location of the crack. For other detailed analysis, please refer to the above example and will not be repeated here.

[0101] In one example, if a crack occurs in the left side of the first portion 161 of the crack detection region 16 (no crack occurs in the right side), the first crack detection signal sub-circuit 121 is broken. Figure 3e , the first crack detection signal sub-circuit 121 is unable to transmit the third clock signal to each of the first sub-switching transistors 141 connected to it. At this point, the entire display screen 1 appears to gradually brighten from the third portion 163 to the second portion 162. For further detailed analysis, please refer to the above example and will not be repeated here.

[0102] In one example, if a crack occurs in the right side of the first portion 161 of the crack detection region 16 (no crack occurs in the left side), the second crack detection signal sub-circuit 122 is broken. Figure 3f , the second crack detection signal sub-circuit 122 is unable to transmit the third clock signal to each of the second sub-switches 142 connected to it. At this point, the entire display screen 1 appears to gradually brighten from the second portion 162 to the third portion 163. For further detailed analysis, please refer to the above example and will not be repeated here.

[0103] In one example, if cracks occur in both the left and right sides of the first portion 161 of the crack detection region 16, the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122 are both broken. Figure 3g , at this time, the overall display brightness of the display screen 1 is relatively high. The rest of the specific analysis can refer to the above example, and will not be repeated here.

[0104] In an example, if there is no crack on the edge of the display screen 1, the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122 will not be broken. The third clock signal can replace the clock signal used by the first gate driver sub-circuit 151 and the second gate driver sub-circuit 152 when the display screen 1 is working normally. The first gate driver sub-circuit 151 and the second gate driver sub-circuit 152 corresponding to each row of pixels 13 can both generate the output signal Gout normally, and the display screen 1 displays normally.

[0105] It is understandable that the remaining crack conditions and display conditions of the display screen 1 will not be further described here.

[0106] In this embodiment of the present application, by replacing the original clock signal circuit with the first crack detection signal sub-circuit 121 and the second crack detection signal sub-circuit 122, the specific location of cracks on the edge of the display screen 1 can be located, improving the accuracy of crack detection compared to related technologies. The specific location of cracks on a foldable display screen can be detected. If most cracks occur in the foldable display screen's bend zone, this indicates that the material properties in this bend zone need to be further enhanced, thereby specifically improving the service life of the foldable display product.

[0107] In one possible implementation, see Figure 4 , the display screen 1 further includes a first clock signal circuit 17 and a second clock signal circuit 18;

[0108] For each pixel row 13, the first clock signal output terminal CLK1 of the signal source chip 11 is connected to the clock signal terminal of the first gate driving sub-circuit 151 corresponding to the pixel row 13 through the first clock signal line 17, and the second clock signal output terminal CLK2 of the signal source chip 11 is connected to the clock signal terminal of the second gate driving sub-circuit 152 corresponding to the pixel row 13 through the second clock signal line 18;

[0109] The signal source chip 11 is further configured to, when the display screen 1 is operating normally, output a first clock signal through its own first clock signal output terminal CLK1, transmit the first clock signal to the clock signal terminal of each first gate driving sub-circuit 151 through the first clock signal line 17, output a second clock signal through its own second clock signal output terminal CLK2, and transmit the second clock signal to the clock signal terminal of each second gate driving sub-circuit 152 through the second clock signal line 18;

[0110] The first clock signal and the second clock signal are the same clock signal.

[0111] The first clock signal and the second clock signal are clock signals used by the first gate driving sub-circuit 151 and the second gate driving sub-circuit 152 when the display screen 1 is working normally. The working state of the display screen 1 when working normally can be referred to the relevant technology.

[0112] In one possible implementation,

[0113] The signal source chip 11 is also used to output a second control signal to the control end of each first sub-switch tube 141 and the control end of each second sub-switch tube 142 through its own control signal output end when the display screen 1 is working normally, so as to cut off the connection between the first end and the second end of each first sub-switch tube 141 and the connection between the first end and the second end of each second sub-switch tube 142.

[0114] When the display screen 1 is operating normally, the first sub-switch tube 141 and the second sub-switch tube 142 are in the off state under the control of the signal source chip 11, and the crack detection signal output terminal PCD-Output is processed with high impedance. The clock signal used by the first gate drive sub-circuit 151 and the second gate drive sub-circuit 152 can be normally output by the clock signal output terminal (the first clock signal output terminal CLK1 and the second clock signal output terminal CLK2). That is to say, the working state of the display screen 1 at this time is the same as the working state of the display screen in the related technology.

[0115] It can be understood that the sub-switch tube used in this application can be a MOS tube (Metal-Oxide-Semiconductor Field-Effect Transistor), or a TFT tube (Thin Film Transistor) or other types of switch tubes. The specific selection can be made according to actual conditions, and the replacement scheme is still within the scope of protection of this application.

[0116] It is understood that for any sub-switch transistor in this application, the sub-switch transistor can be an N-type transistor or a P-type transistor, and the specific selection can be made according to actual circumstances; the control terminal of the transistor is the gate, the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal. It is understood that the transistor can be a P-type transistor or an N-type transistor, and the specific selection can be made according to actual circumstances.

[0117] When each sub-switch tube is a P-type transistor, the first control signal is a low-level signal and the second control signal is a high-level signal; when each sub-switch tube is an N-type transistor, the first control signal is a high-level signal and the second control signal is a low-level signal.

[0118] In a possible implementation manner, the third clock signal is the same clock signal as the first clock signal and the second clock signal.

[0119] In a possible implementation manner, the third clock signal is a positive phase clock signal GCK, the first clock signal is a positive phase clock signal GCK, and the second clock signal is a positive phase clock signal GCK;

[0120] or;

[0121] The third clock signal is an inverted clock signal GCB, the first clock signal is an inverted clock signal GCB, and the second clock signal is an inverted clock signal GCB.

[0122] The gate drive circuit can only generate the output signal Gout when it receives the positive phase clock signal GCK and the negative phase clock signal GCB at the same time. Therefore, when crack detection is performed on the edge of the display screen 1, crack detection can be performed only using the positive phase clock signal GCK / negative phase clock signal GCB. When crack detection is performed using the positive phase clock signal GCK, the negative phase clock signal GCB is output normally. When crack detection is performed using the negative phase clock signal GCB, the positive phase clock signal GCK is output normally.

[0123] In one possible implementation,

[0124] The signal source chip 11 is further used to perform high-impedance processing on the first clock signal output terminal CLK1 and the second clock signal output terminal CLK2 when crack detection is performed on the edge of the display screen 1 .

[0125] The specific analysis is the same as above and will not be repeated here.

[0126] In one possible implementation,

[0127] The signal source chip 11 is further configured to perform high-impedance processing on the crack detection signal output terminal PCD-Output when the display screen 1 is operating normally.

[0128] The specific analysis is the same as above and will not be repeated here.

[0129] In one possible implementation, see Figure 5 ,

[0130] The first end of the first crack detection signal sub-circuit 121 is connected to the first voltage terminal PCD1 of the signal source chip 11, and the second end of the first crack detection signal sub-circuit 121 is connected to the crack detection signal output terminal PCD-Output of the signal source chip 11;

[0131] A first end of the second crack detection signal sub-circuit 122 is connected to the second voltage terminal PCD2 of the signal source chip 11, and a second end of the second crack detection signal sub-circuit 122 is connected to the crack detection signal output terminal PCD-Output of the signal source chip 11;

[0132] A potential difference is formed between the crack detection signal output terminal PCD-Output and the first voltage terminal PCD1;

[0133] A potential difference is formed between the crack detection signal output terminal PCD-Output and the second voltage terminal PCD2.

[0134] The first voltage terminal PCD1 is used to form a loop of the first crack detection signal sub-circuit 121 , and the second voltage terminal PCD2 is used to form a loop of the second crack detection signal sub-circuit 122 .

[0135] The present application also provides a crack detection method for detecting cracks in the display screen 1 described in any of the above embodiments. Figure 6 , the method comprises the following steps:

[0136] Step S101 , obtaining the current display brightness of each pixel row 13 of the display screen 1 and the normal display brightness of the display screen 1 .

[0137] Step S102: When there is a brightness difference between the display brightness of the Nth row of pixel row 13 and the N+1th row of pixel row 13, and the brightness difference is greater than a preset difference threshold, or when there is a brightness difference between pixel units in the same row of pixel row 13, or when the current display brightness of the display screen 1 is uniform but there is a brightness difference between the current display brightness of the display screen 1 and the normal display brightness of the display screen 1, it is determined that a crack has occurred at the edge of the display screen 1; wherein N is an integer not less than 1.

[0138] The preset difference threshold needs to be set according to the original brightness difference between pixel rows due to their own reasons or other factors.

[0139] For an example, see Figure 3b If a dividing line exists on the display screen 1, the display area below the dividing line gradually brightens in the order from the third portion 163 to the second portion 162, and the display area above the dividing line displays normally. It is determined that a crack has occurred in the second portion 162 of the crack detection area 16, while no crack has occurred in the first portion 161 or the third portion 163 of the crack detection area 16. The remaining analysis is the same as above and will not be repeated here.

[0140] For an example, see Figure 3c If a dividing line exists on the display screen 1, the display area below the dividing line gradually brightens in the order from the second portion 162 to the third portion 163, while the display area above the dividing line displays normally. It is determined that a crack has occurred in the third portion 163 of the crack detection area 16, while no crack has occurred in the first portion 161 or the second portion 162 of the crack detection area 16. The remaining analysis is the same as above and will not be repeated here.

[0141] For an example, see Figure 3d If the display screen 1 has two dividing lines, the area above the first dividing line is a normal display area, the area below the first dividing line and above the second dividing line is a display area that gradually brightens in the order from the third portion 163 to the second portion 162, and the area below the second dividing line is a display area with a relatively high overall display brightness. It is determined that cracks have occurred in both the second portion 162 and the third portion 163 of the crack detection area 16, while no cracks have occurred in the first portion 161 of the crack detection area 16. The remaining analysis is the same as above and will not be repeated here.

[0142] For an example, see Figure 3e If the entire display screen 1 gradually brightens in the order from the third portion 163 to the second portion 162, it is determined that a crack has occurred in the left side of the first portion 161 of the crack detection area 16 (no crack has occurred in the right side). The remaining analysis is the same as above and will not be repeated here.

[0143] For an example, see Figure 3f If the entire display screen 1 gradually brightens in the order from the second portion 162 to the third portion 163, it is determined that a crack has occurred in the right side of the first portion 161 of the crack detection area 16 (no crack has occurred in the left side). The remaining analysis is the same as above and will not be repeated here.

[0144] For an example, see Figure 3g If the overall display brightness of the display screen 1 is too high, it is determined that cracks occur in both the left and right sides of the first portion 161 of the crack detection area 16. The remaining analysis is the same as above and will not be repeated here.

[0145] It is understandable that the remaining crack conditions and display conditions of the display screen 1 will not be further described here.

[0146] In the embodiment of the present application, when a crack occurs on the edge of the display screen 1, the display screen 1 will show an obvious abnormal display phenomenon, so that the position where the crack occurs can be located based on the abnormal display.

[0147] The present application also provides a display 2, see Figure 7 , the display 2 includes the display screen 1 described in any one of the above embodiments.

[0148] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0149] Each embodiment in this specification is described in a related manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences between the other embodiments. In particular, the system embodiment is generally similar to the method embodiment, so the description is relatively simple. For related parts, refer to the description of the method embodiment.

[0150] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application are included in the scope of protection of the present application.

Claims

1. A display screen, characterized in that: The display screen includes: A signal source chip, a crack detection signal circuit partially arranged at the edge of the display screen, a plurality of pixel rows, a switch tube corresponding to each pixel row, and a gate drive circuit corresponding to each pixel row; The crack detection signal circuit includes a first crack detection signal sub-circuit and a second crack detection signal sub-circuit; The first crack detection signal sub-circuit and the second crack detection signal sub-circuit are arranged in a crack detection area of ​​the display screen; the crack detection area is located at an edge and a middle portion of the display screen, the fourth portion of the crack detection area is located on a side where the signal source chip is located, the first portion of the crack detection area is located on a side away from the signal source chip, the second portion, the third portion, and the fifth portion of the crack detection area are perpendicular to the first portion and the fourth portion, the second portion and the third portion are located on both sides of the display screen, and the fifth portion is located in the middle portion of the display screen; The switch tube includes a first sub-switch tube and a second sub-switch tube, and the gate drive circuit includes a first gate drive sub-circuit and a second gate drive sub-circuit; In the row direction of the display screen, for each pixel row, a first gate driving sub-circuit and a first sub-switch tube corresponding to the pixel row are provided on one side of the pixel row, and a second gate driving sub-circuit and a second sub-switch tube corresponding to the pixel row are provided on the other side of the pixel row; For each pixel row, the crack detection signal output end of the signal source chip is connected to the first end of the first sub-switch tube corresponding to the pixel row through the first crack detection signal sub-circuit, and the second end of the first sub-switch tube corresponding to the pixel row is connected to the clock signal end of the first gate drive sub-circuit corresponding to the pixel row. The crack detection signal output end of the signal source chip is connected to the first end of the second sub-switch tube corresponding to the pixel row through the second crack detection signal sub-circuit, and the second end of the second sub-switch tube corresponding to the pixel row is connected to the clock signal end of the second gate drive sub-circuit corresponding to the pixel row. For each pixel row, one side of the pixel row is connected to the output end of the first gate driving sub-circuit corresponding to the pixel row, and the other side of the pixel row is connected to the output end of the second gate driving sub-circuit corresponding to the pixel row; The signal source chip is specifically configured to output a third clock signal through its own crack detection signal output terminal when crack detection is performed on the edge of the display screen, transmit the third clock signal to the first terminal of each of the first sub-switching transistors through the first crack detection signal sub-circuit, and transmit the third clock signal to the first terminal of each of the second sub-switching transistors through the second crack detection signal sub-circuit; The signal source chip is further specifically configured to output a first control signal to the control end of each of the first sub-switching tubes and the control end of each of the second sub-switching tubes through its own control signal output end when crack detection is performed on the edge of the display screen; The first sub-switch tube is configured to output the third clock signal to the clock signal terminal of the first gate drive sub-circuit connected to the first sub-switch tube by conducting between the first terminal and the second terminal when the control terminal thereof receives the first control signal; The second sub-switch tube is used to output the third clock signal to the clock signal end of the second gate drive sub-circuit connected to itself by conducting between its first end and second end when its control end receives the first control signal.

2. The display screen according to claim 1, wherein: The display screen further includes a first clock signal circuit and a second clock signal circuit; For each pixel row, the first clock signal output terminal of the signal source chip is connected to the clock signal terminal of the first gate driving sub-circuit corresponding to the pixel row through the first clock signal circuit, and the second clock signal output terminal of the signal source chip is connected to the clock signal terminal of the second gate driving sub-circuit corresponding to the pixel row through the second clock signal circuit; The signal source chip is further configured to, when the display screen is operating normally, output a first clock signal through its own first clock signal output terminal, and transmit the first clock signal to the clock signal terminal of each of the first gate drive sub-circuits through the first clock signal circuit; output a second clock signal through its own second clock signal output terminal, and transmit the second clock signal to the clock signal terminal of each of the second gate drive sub-circuits through the second clock signal circuit; The first clock signal and the second clock signal are the same clock signal.

3. The display screen according to claim 2, wherein: The signal source chip is further configured to output a second control signal to the control end of each of the first sub-switching tubes and the control end of each of the second sub-switching tubes through its own control signal output end when the display screen is operating normally, so as to disconnect the first end and the second end of each of the first sub-switching tubes and disconnect the first end and the second end of each of the second sub-switching tubes.

4. The display screen according to claim 2, wherein: The third clock signal is the same clock signal as the first clock signal and the second clock signal.

5. The display screen according to claim 4, characterized in that The third clock signal is a positive phase clock signal GCK, the first clock signal is a positive phase clock signal GCK, and the second clock signal is a positive phase clock signal GCK; or; The third clock signal is an inverted clock signal GCB, the first clock signal is an inverted clock signal GCB, and the second clock signal is an inverted clock signal GCB.

6. The display screen according to claim 3, characterized in that The signal source chip is further used to perform high-impedance processing on the first clock signal output end and the second clock signal output end when crack detection is performed on the edge of the display screen.

7. The display screen according to claim 6, characterized in that The signal source chip is further used to perform high-impedance processing on the crack detection signal output end when the display screen is working normally.

8. The display screen according to claim 1, wherein: The first end of the first crack detection signal sub-circuit is connected to the first voltage terminal of the signal source chip, and the second end of the first crack detection signal sub-circuit is connected to the crack detection signal output terminal of the signal source chip; The first end of the second crack detection signal sub-circuit is connected to the second voltage terminal of the signal source chip, and the second end of the second crack detection signal sub-circuit is connected to the crack detection signal output terminal of the signal source chip; A potential difference is formed between the crack detection signal output terminal and the first voltage terminal; A potential difference is formed between the crack detection signal output terminal and the second voltage terminal.

9. A crack detection method, characterized in that: For detecting the display screen according to any one of claims 1 to 8, the method comprises: Obtaining the current display brightness of each pixel row of the display screen and the normal display brightness of the display screen; When there is a brightness difference between the display brightness of the Nth row of pixels and the N+1th row of pixels, and the brightness difference is greater than a preset difference threshold, or when there is a brightness difference between pixel units in the same row of pixels, or when the current display brightness of the display screen is uniform but there is a brightness difference between the current display brightness of the display screen and the normal display brightness of the display screen, it is determined that a crack has occurred at the edge of the display screen; wherein N is an integer not less than 1.

10. A display, characterized in that: The display comprises the display screen described in any one of claims 1 to 8.

Images