Power semiconductor device and method for manufacturing the same

Abstract

A power semiconductor device and a manufacturing method thereof. The power semiconductor device includes a semiconductor layer, a gate lead-out terminal, and a gate mesh. Among them, the gate lead-out terminal and the gate mesh are disposed on the cathode surface of the semiconductor layer, and the contact resistance between the gate mesh and the semiconductor layer is distributed in a gradient manner according to the distance between the gate mesh and the gate lead-out terminal. The closer the gate mesh is to the gate lead-out terminal, the greater the contact resistance between the gate mesh and the semiconductor layer. By adjusting the contact resistance between the gate mesh and the semiconductor layer, the present invention controls the current flowing through the Au-Semiconductor contact to flow more along the metal interconnection structure to the region with a small contact resistance, realizes precise control of the current in the transverse and longitudinal directions, improves the uneven current distribution, and avoids burning out the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and particularly relates to a power semiconductor device and a method for manufacturing the same. Background Art

[0002] Power semiconductor devices, also known as power electronic devices or power electronics devices, are one of the most core devices in the electronic industry chain. Power semiconductor devices can achieve electric energy conversion and circuit control, and mainly play roles such as power conversion, power amplification, power switching, circuit protection, inversion (DC to AC), and rectification (AC to DC) in a circuit.

[0003] Gate Commutated Thyristors (GCT) are semiconductor devices with ultra-large power capacity in the field of power electronics. A GCT chip integrates multiple gate commutated thyristor cell units. Usually, an intermediate annular gate is adopted, and the gate impedance in the region close to and far from the gate lead-out terminal is slightly different, resulting in a tiny time difference between thyristor cell units during turn-off, thereby causing a current crowding phenomenon in the region far from the gate contact area.

[0004] Taking a fully controlled thyristor as an example, when the device is turned on, a large current is formed at the Schottky contact interface close to the gate lead-out terminal region, while the current in the far region is small, resulting in an uneven current distribution and eventually burning out the device; when the device is turned off, during the extraction of carriers in the base region under the gate, the gate base region close to the gate lead-out terminal region is quickly extracted to form a high electric field region or depletion region, causing carriers to flow to the gate base region far from the gate lead-out terminal region and a large amount of them to converge through the low-contact-resistance alloy interface in this region, forming a large current that exceeds the current-carrying capacity of the metal electrode and generating a large amount of heat accumulation to burn out the device.

[0005] In view of the above technical problems, in existing technologies such as Chinese Patent Application Publications CN2022800187754 and CN2023112244275, a lateral variable doping method is usually adopted to improve the turn-off ability of the device by changing the doping concentration at different positions in the gate region. However, the manufacturing process of this method is complex, and different templates are required to control the doping concentration at different positions in the gate region, resulting in a long process flow and high manufacturing cost.

[0006] Therefore, there is an urgent need in this field to develop a power semiconductor device and a manufacturing method with different implementation methods to reduce the process cost while improving the turn-off ability of the device. Summary of the Invention

[0007] In view of this, the main objective of the present invention is to provide a power semiconductor device and a method for manufacturing the same, in order to at least partially solve the above technical problems.

[0008] To achieve the above object, as one aspect of the present invention, there is provided a power semiconductor device, comprising a semiconductor layer, a gate lead-out terminal and a gate grid. Among them, the gate lead-out terminal and the gate grid are disposed on the cathode surface of the semiconductor layer, and the contact resistance between the gate grid and the semiconductor layer is distributed in a gradient manner according to the distance from the gate grid to the gate lead-out terminal. The closer the distance to the gate lead-out terminal, the greater the contact resistance between the gate grid and the semiconductor layer.

[0009] As another aspect of the present invention, there is provided a method for manufacturing a power semiconductor device, comprising the following steps:

[0010] Prepare a first metal layer on the cathode surface of the semiconductor layer;

[0011] Perform patterning on the first metal layer to divide the gate lead-out terminal region and the gate grid region;

[0012] Perform patterned annealing on the first metal layer in the gate grid region, so that the contact resistance between the first metal layer in the gate grid region and the semiconductor layer is distributed in a gradient manner according to the distance from the gate grid region to the gate lead-out terminal region. The closer the distance to the gate lead-out terminal region, the greater the contact resistance between the first metal layer in the gate grid region and the semiconductor layer.

[0013] It can be seen that the power semiconductor device and its manufacturing method of the present invention have at least one of the following beneficial effects compared with the prior art:

[0014] By reasonably controlling the contact resistance between the gate grid and the semiconductor layer, the present invention improves the current distribution, realizes precise control of the current path, and at the same time can effectively reduce the parasitic parameters of the device, improve the gate switching performance, improve the turn-off ability, and avoid local formation of large currents to burn out the device.

[0015] In addition, the technical solution of the present invention can be applied to power semiconductor devices with various different electrode patterns, and can be used for precisely regulating the patterned distribution of different alloy resistances. Moreover, the process flow is relatively simple, the process cost is low, and it is suitable for industrial application and promotion. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic cross-sectional structure diagram of a power semiconductor device according to an embodiment of the present invention;

[0017] Figure 2 is a schematic top view structure diagram of a power semiconductor device according to an embodiment of the present invention;

[0018] Figure 3 is a schematic cross-sectional structure diagram of a power semiconductor device according to a preferred embodiment of the present invention;

[0019] Figure 4 It is a top - view structural schematic diagram of a power semiconductor device according to a preferred embodiment of the present invention. Specific embodiments

[0020] To make the objectives, technical solutions, and advantages of the present invention clearer and more understandable, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings.

[0021] The present invention proposes a power semiconductor device and a manufacturing method implemented in different ways, which can improve the turn - off ability of the device while reducing the process cost.

[0022] Specifically, in a specific embodiment, the present invention provides a power semiconductor device 100, as Figure 1 and Figure 2 shown, for example, including a semiconductor layer 101, a gate lead 102, a gate mesh 103, and a cathode layer 104. Among them, the gate lead 102, the gate mesh 103, and the cathode layer 104 are all disposed on the cathode surface of the semiconductor layer 101. The contact resistance between the gate mesh 103 and the semiconductor layer 101 is distributed in a gradient according to the distance from the gate mesh 103 to the gate lead 102. The closer the gate mesh 103 is to the gate lead 102, the greater the contact resistance between the gate mesh 103 and the semiconductor layer 101.

[0023] Preferably, the power semiconductor device 100 further includes a dielectric layer 105. The dielectric layer 105 is disposed on the cathode surface of the semiconductor layer 101, covering the gate mesh 103 and the exposed semiconductor layer, mainly for insulation between electrodes and protection of the device.

[0024] In this specific embodiment, the contact resistance between the gate mesh and the semiconductor layer is regulated according to the distance between the gate mesh and the gate lead, so that the Au - semiconductor contact resistance in the region closer to the gate lead is larger, and the Au - semiconductor contact resistance in the region farther from the gate lead is smaller. Thus, during the switching process, the currents converging and diverging from the gate lead flow to the regions away from the gate lead due to different contact resistances, thereby achieving a better current sharing effect, and the current non - uniformity of the device ≤ 20%.

[0025] As a specific embodiment, as Figure 2 shown, the contact resistance (Au - semiconductor contact resistance) between the gate mesh 103 and the semiconductor layer 101 is different at different distances from the gate lead 102. For example, the Au - semiconductor contact resistance at a distance d 1 from the gate lead 102 is R 1 , the Au - semiconductor contact resistance at a distance d 2 from the gate lead 102 is R 2 , and the Au - semiconductor contact resistance at a distance d 3 from the gate lead 102 is R 3, d 1 <d 2 <d 3 , then R 1 > R 2 > R 3 .

[0026] Preferably, the gate grid 103 includes a first metal layer and a second metal layer, and the first metal layer is disposed between the semiconductor layer 101 and the second metal layer. The setting of the double-layer metal layer is beneficial to better control the contact resistance between the gate grid and the semiconductor layer, so that it more precisely meets the gradient distribution of the contact resistance.

[0027] Preferably, the semiconductor layer 101 can be any one of silicon, silicon carbide, gallium nitride, gallium arsenide, diamond, and other III-IV compounds; the first metal layer is made of a metal or alloy material with a conductivity greater than or equal to 0.025 Ω·mm 2 / m and a thermal conductivity greater than or equal to 220 W / mK. For example, it can be any one of gold, silver, copper, nickel, titanium, aluminum, nickel-titanium-silver, and aluminum-silicon-copper. Preferably, it is aluminum, and the thickness is preferably 5 nm - 1 μm, and the thickness uniformity ≤ 5%; the first metal layer shows different degrees of alloying, and the alloying depth is 2 - 50 nm; when the material of the first metal layer is aluminum, the composition after alloying of the first metal layer is Al x Si y , where 7 ≤ x / y ≤ 60. Due to the different degrees of alloying of the first metal layer, the alloying depth and the alloy composition ratio are different, and the two together determine the different contact resistances between the first metal layer and the semiconductor layer (i.e., the metal-semiconductor contact resistance). By precisely controlling the degree of alloying of the first metal layer, the gradient distribution of the metal-semiconductor contact resistance can be precisely regulated so that the metal-semiconductor contact resistance is smaller in the area farther from the gate lead-out end and larger in the area closer to the gate lead-out end.

[0028] Preferably, the gate grid 103 includes an alloy layer and a third metal layer, where the alloy layer is disposed between the semiconductor layer and the third metal layer, and the contact resistance between the alloy layer and the semiconductor layer shows a gradient distribution, and the closer to the gate lead-out end, the greater the contact resistance between the alloy layer and the semiconductor layer. Further preferably, the composition of the alloy layer is Al x Si y , where 7 ≤ x / y ≤ 60; the thickness of the alloy layer is 2 - 50 nm.

[0029] Another embodiment of the present invention provides a method for manufacturing a power semiconductor device for manufacturing the power semiconductor device described in the present invention. The manufacturing method includes the following steps:

[0030] S101, preparing a first metal layer on the cathode surface of the semiconductor layer;

[0031] S102. Pattern the first metal layer to divide the gate lead-out terminal area and the gate mesh area;

[0032] S103. Perform a patterned annealing process on the first metal layer in the gate mesh area, so that the contact resistance between the first metal layer in the gate mesh area and the semiconductor layer shows a gradient distribution according to the distance between the gate mesh area and the gate lead-out terminal area. The closer the distance to the gate lead-out terminal area, the greater the contact resistance between the first metal layer in the gate mesh area and the semiconductor layer.

[0033] Among them, the gradient distribution of the contact resistance and the process conditions of the patterned annealing process can both be obtained through pre-modeling. Specifically, the gradient distribution of the contact resistance is related to the structure of the gate electrode layer. By modeling the structural parameters of the gate electrode layer in combination with Kirchhoff's current law and solving using the numerical iteration method, the gradient distribution design of the contact resistance between the gate mesh and the semiconductor layer can be obtained; on this basis, combined with the doping elements and doping concentrations of the semiconductor layer, according to the barrier matching, the first metal layer material can be determined through theoretical calculations and simulation, and the alloying-related parameters can be deduced, including alloy composition and ratio, alloying depth, etc.; and according to the phase diagram theory of the metal-semiconductor contact resistance, combined with the laws of thermodynamics, material physics, and the alloying theory analysis of the contact resistance, the patterned annealing process conditions can be obtained.

[0034] Preferably, in step S101, the preparation method of the first metal layer can be any one of processes such as electroplating, nano-spray coating, gel titanium metal printing or coating, sputtering, etc., and can be arbitrarily selected according to actual needs.

[0035] Preferably, before step S101, the semiconductor layer is pretreated to make its surface quality meet the requirements of the alloy process. Among them, the pretreatment includes one or more of RCA cleaning, nitrogen gun purging, and deionized water cleaning.

[0036] Preferably, in step S103, the patterned annealing treatment includes: dividing the gate mesh region into different annealing regions according to the gradient distribution of the contact resistance, and annealing the same annealing region at the same annealing temperature and annealing time. Preferably, the annealing temperature of the patterned annealing treatment is 400-550 °C, and the annealing time is 10 μs-30 min; each of the annealing regions includes a plurality of heated regions, and the cross-section of the heated region is preferably circular, with a radius of 10 μm-5 mm, and the distance between adjacent heated regions is 5-30 μm. The patterned annealing treatment can be any one of laser annealing, thermal probe point annealing, local heating annealing with a resistance wire, and condensing heating annealing. Preferably, laser annealing or thermal probe point annealing is used, which can precisely control the annealing region. The patterned annealing treatment causes the first metal layer to form alloying with different depths, and the alloy composition ratios are also different. The alloying depth and the alloy composition ratio jointly determine that the metal-semiconductor contact resistance exhibits a gradient distribution according to the design requirements.

[0037] Preferably, the patterned annealing adopts a zoning and sectional annealing method. According to the gradient distribution of the contact resistance, annealing is sequentially started in zones from the gate mesh region farthest from the gate lead-out end region. The same annealing region is annealed at the same annealing temperature and annealing time, and the annealing time interval between adjacent annealing regions is 10 μs. By means of zoning and sectional annealing, precise control of the metal-semiconductor contact resistance can be achieved, so that the metal-semiconductor contact resistance realizes the required gradient distribution.

[0038] Preferably, after step S103, the method for manufacturing the power semiconductor device further includes: preparing a second metal layer on the first metal layer after the patterned annealing treatment, and forming a gate lead-out end and a gate mesh through patterning. Preparing the second metal layer on the first metal layer of the gate mesh can effectively improve the conductivity of the gate mesh on the basis of precisely controlling the gradient distribution of the metal-semiconductor contact resistance.

[0039] Among them, the material of the second metal layer can be the same as or different from the material of the first metal layer; the preparation method of the second metal layer can be any one of processes such as electroplating, nano-spray plating, gel titanium metal printing or coating, sputtering, evaporation, etc. Preferably, the evaporation process is used.

[0040] Preferably, after step S103, the method for manufacturing the power semiconductor device further includes: performing surface treatment on the first metal layer after the patterned annealing treatment to form a patterned alloy layer, and the contact resistance between the alloy layer and the semiconductor layer exhibits a gradient distribution according to the distance from the gate lead-out end region.

[0041] Specifically, the surface treatment may include processes such as metal corrosion cleaning, deionized water washing, purging, spin drying, drying, etc., to remove residual metal media, metal particles, alloy impurities, other attachments, etc., and improve the process quality of the alloy interface.

[0042] Further preferably, the preparation method further includes: preparing a patterned third metal layer on the alloy layer. Among them, the material of the third metal layer may be the same as or different from that of the first metal layer; the preparation method of the third metal layer may be any one of processes such as electroplating, nano-spray plating, gel titanium metal printing or coating, sputtering, evaporation, etc., and the evaporation process is preferred.

[0043] As a further preferred specific embodiment, the power semiconductor device of the present invention may be a gate commutated thyristor. As Figure 3 and Figure 4 shown, the gate commutated thyristor 200 includes a semiconductor layer 201, a gate lead 202, a gate grid 203, and a cathode comb 204. Among them, the gate lead 202, the gate grid 203, and the cathode comb 204 are all disposed on the cathode surface of the semiconductor layer 201. The gate lead 202 is annular and concentric with the power semiconductor device 200; a plurality of cathode rings concentric with the gate lead 202 are also disposed on the cathode surface of the power semiconductor device 200. Each cathode ring includes a plurality of cathode combs 204 arranged radially. The gate grid 203 and the cathode comb 204 are arranged at intervals. The contact resistance between the gate grid 203 and the semiconductor layer 201 decreases logarithmically as the radial distance between the gate grid 203 and the gate lead 202 becomes farther. Among them, the gate grid 203 includes a first metal layer and a second metal layer, and the first metal layer is disposed between the semiconductor layer 201 and the second metal layer.

[0044] Preferably, the gate commutated thyristor 200 further includes a dielectric layer 205. The dielectric layer 205 is disposed on the cathode surface of the semiconductor layer 201, covering the gate grid 203 and the exposed semiconductor layer, and is mainly used for insulation between electrodes and protection of the device.

[0045] Preferably, as Figure 3 shown, the contact resistance between the gate grid 203 and the semiconductor layer is different at different distances from the gate lead 202. For example, the Au-Semiconductor contact resistance at the radial distance r 1 from the gate lead 202 is R 1 ’ , the Au-Semiconductor contact resistance at the radial distance r 2 from the gate lead 202 is R 2 ’ , the Au-Semiconductor contact resistance at the radial distance r 3 from the gate lead 202 is R 3 ’ , r1 <r 2 <r 3 If so, then R 1 ’ >R 2 ’ >R 3 ’ and R 1 ’ 、R 2 ’ 、R 3 ’ decrease according to a logarithmic change.

[0046] Preferably, the semiconductor layer 201 is single-crystalline silicon, and boron and aluminum are doped on the side of the semiconductor layer 201 close to the first metal layer, with a doping concentration of 1E15 - 2E18 / cm 3 ; the first metal layer is aluminum, with a thickness of 30 nm - 1 μm and a thickness uniformity of ≤5%; the first metal layer exhibits alloying at different depths, and the alloy composition is Al x Si y , where 7 ≤ x / y ≤ 60 and the alloying depth is 2 - 50 nm; the second metal layer is aluminum, with a thickness of 5 - 50 μm and a thickness uniformity of ≤10%.

[0047] As a preferred embodiment, the present invention also provides a method for manufacturing the gate-commutated thyristor 200, including the following steps:

[0048] S201, preparing the first metal layer on the cathode surface of the semiconductor layer 201 by sputtering;

[0049] S202, patterning the first metal layer by photolithography and etching to divide the gate lead-out terminal area and the gate mesh area; among them, the gate lead-out terminal area is an annular area concentric with the gate-commutated thyristor 200; the gate mesh area is arranged outside the gate lead-out terminal area on the gate-commutated thyristor 200 to form a plurality of annular areas concentric with the gate lead-out terminal area;

[0050] S203, performing patterned annealing on the first metal layer in the gate mesh area by laser annealing, so that the contact resistance between the first metal layer in the gate mesh area and the semiconductor layer decreases according to a logarithmic change as the radial distance between the gate mesh area and the gate lead-out terminal area becomes farther;

[0051] S204, preparing the second metal layer on the patterned-annealed first metal layer and forming the gate lead-out terminal 202 and the gate mesh 203 through patterning.

[0052] Among them, the gradient distribution of the contact resistance and the process conditions of the patterned annealing treatment can both be obtained through pre-modeling. The specific method is as described above and will not be elaborated here.

[0053] Preferably, in step S203, the patterned annealing treatment includes: dividing the gate mesh region into concentric rings with different radii according to the gradient distribution of the contact resistance to form different annealing regions; the annealing temperature of the patterned annealing treatment is 400 - 550 °C, and the annealing time is 10 μs - 100 ms; each annealing region includes uniformly distributed circular heating regions with a radius of 30 - 150 μm, and the distance between adjacent two circular heating regions is 5 - 30 μm; the same annealing temperature and annealing time are used for annealing in the same annealing region, and the annealing time interval between adjacent annealing regions is 10 μs.

[0054] Preferably, after step S203, it further includes: performing processes such as metal corrosion cleaning, deionized water washing, purging, spin-drying, and drying on the surface of the wafer after the patterned annealing treatment to remove residual metal media, metal particles, alloy impurities, other attachments, etc., and improving the process quality of the alloy interface.

[0055] Through simulation, the present invention can control the contact resistance between the gate mesh and the semiconductor layer to improve the current distribution, achieve precise control of the current path, effectively reduce the parasitic parameters of the device, improve the gate switching performance, enhance the turn-off ability, and avoid local large current burning out the device.

[0056] The specific embodiments described above further elaborate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are only specific embodiments of the present invention and are not used to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0057] The "first", "second",... of the present invention are only used to distinguish different devices / components / members, and are not used to mark the setting order of the devices / components / members, nor are they used to limit the quantity of the devices / components / members.

Claims

1. A power semiconductor device, comprising a semiconductor layer, a gate lead terminal and a gate network, wherein: The gate lead-out terminal and the gate grid are arranged on the cathode surface of the semiconductor layer, characterized in that the contact resistance between the gate grid and the semiconductor layer is distributed in a gradient according to the distance between the gate grid and the gate lead-out terminal, and the closer the distance to the gate lead-out terminal, the greater the contact resistance between the gate grid and the semiconductor layer; The gate grid includes a first metal layer and a second metal layer, the first metal layer is arranged between the semiconductor layer and the second metal layer, and the contact resistance between the first metal layer and the semiconductor layer is distributed in a gradient manner; the thickness of the first metal layer is 5 nm-1 μm; The first metal layer is alloyed at different depths; the alloying depth of the first metal layer is 2-50 nm; the gradient distribution of the contact resistance is precisely controlled by precisely controlling the alloying degree of the first metal layer; or The gate grid includes an alloy layer and a third metal layer, the alloy layer is arranged between the semiconductor layer and the third metal layer, and the contact resistance between the alloy layer and the semiconductor layer is in the gradient distribution; the composition of the alloy layer is Al x Si y , wherein 7≤x / y≤60; the thickness of the alloy layer is 2-50 nm; and the gradient distribution of the contact resistance is precisely regulated by precisely controlling the alloying degree of the alloy layer.

2. The power semiconductor device according to claim 1, characterized in that: The first metal layer is made of metal or alloy material with an electrical conductivity greater than or equal to 0.025Ω·mm² / m; the first metal layer is made of any one of gold, silver, copper, nickel, titanium, aluminum, nickel-titanium-silver, and aluminum-silicon-copper.

3. The power semiconductor device according to claim 1, characterized in that: When the material of the first metal layer is aluminum, the composition of the first metal layer after alloying is Al x Si y , where 7≤x / y≤60.

4. The power semiconductor device according to any one of claims 1 to 3, characterized in that: The gate lead-out terminal is annular and is arranged concentrically with the power semiconductor device. A plurality of cathode rings concentric with the gate lead-out terminal are also arranged on the cathode surface of the semiconductor layer. Each of the cathode rings includes a plurality of cathode comb bars arranged radially. The gate grid and the cathode comb bars are arranged at intervals. The contact resistance between the gate grid and the semiconductor layer decreases logarithmically as the radial distance between the gate grid and the gate lead-out terminal becomes greater.

5. The power semiconductor device according to claim 1, characterized in that: The power semiconductor device is any one of GCT, IGCT and GTO.

6. A method for preparing a power semiconductor device, characterized in that: The following steps are involved: Preparing a first metal layer on the cathode surface of the semiconductor layer; Performing a patterning process on the first metal layer to divide the gate lead-out terminal region and the gate grid region; Performing a patterned annealing process on the first metal layer in the gate grid region so that the contact resistance between the first metal layer in the gate grid region and the semiconductor layer is distributed in a gradient according to the distance between the gate grid region and the gate lead-out region, wherein the closer the distance to the gate lead-out region is, the greater the contact resistance between the first metal layer in the gate grid region and the semiconductor layer is; Performing surface treatment on the first metal layer after the patterned annealing treatment to form a patterned distributed alloy layer, wherein the contact resistance between the alloy layer and the semiconductor layer is distributed in a gradient according to the distance between the alloy layer and the gate lead-out terminal region; By precisely controlling the alloying degree of the alloy layer, the gradient distribution of the contact resistance can be precisely regulated.

7. The preparation method according to claim 6, characterized in that: The preparation method further comprises: preparing a patterned second metal layer on the first metal layer after the patterned annealing treatment.

8. The preparation method according to claim 6, characterized in that: The gradient distribution of the contact resistance and the process conditions of the graphic annealing treatment are obtained by pre-modeling; the structural parameters of the gate grid are modeled in combination with the node current law, and the gradient distribution design of the contact resistance between the gate grid and the semiconductor layer is obtained by adopting the numerical iteration method; according to the gradient distribution design of the contact resistance between the gate grid and the semiconductor layer, combined with the doping elements, doping concentration, and barrier matching of the semiconductor layer, the material properties of the first metal layer are simulated and determined, and the alloying parameters of the first metal layer are calculated; according to the alloying parameters of the first metal layer, combined with the phase diagram theory of gold-semiconductor contact resistance and the alloying theory of contact resistance, the process conditions of the graphic annealing treatment are simulated.

9. The preparation method according to claim 6, characterized in that: The patterned annealing process includes: dividing the gate grid area into different annealing areas according to the gradient distribution of the contact resistance, and annealing the same annealing area using the same annealing temperature and annealing time; the annealing area is a plurality of annular areas concentric with the gate lead-out terminal area.

10. The preparation method according to claim 9, characterized in that: Each of the annealing regions includes a plurality of heating zones, and the distance between adjacent heating zones is 5-30 μm.

11. The preparation method according to claim 6, characterized in that: The annealing temperature of the patterned annealing treatment is 400-550° C., and the annealing time is 10 μs-30 min. The patterned annealing treatment adopts any one of laser annealing, thermal probe point annealing, resistance wire local heating annealing, and concentrated heating annealing.

12. The preparation method according to claim 6, characterized in that: The power semiconductor device is any one of GCT, IGCT and GTO.

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