Solar cell preparation method, passivation contact structure preparation method and solar cell

Abstract

The present application relates to a method for preparing a solar cell, a method for preparing a passivation contact structure, and a solar cell. The method for preparing the passivation contact structure includes the following steps: preparing a tunneling silicon oxide layer on a silicon substrate; depositing an intrinsic amorphous silicon layer on the tunneling silicon oxide layer; pre-annealing the silicon substrate on which the tunneling silicon oxide layer and the intrinsic amorphous silicon layer are stacked; depositing a doped amorphous silicon layer on the pre-annealed intrinsic amorphous silicon layer; and annealing the silicon substrate on which the tunneling silicon oxide layer, the intrinsic amorphous silicon layer, and the doped amorphous silicon layer are deposited to form a doped polycrystalline silicon layer stacked on the tunneling oxide layer. Thus, after depositing the intrinsic amorphous silicon layer, a pre-annealing operation is introduced to open some pores in the tunneling silicon oxide layer, thereby assisting carrier transport and improving the passivation performance of the passivation contact structure.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a method for preparing a solar cell, a method for preparing a passivation contact structure, and a solar cell. Background Art

[0002] Solar cells have consistently dominated the photovoltaic industry, holding over 90% of the market share. Given such a large volume and broad market prospects, reducing solar cell costs is a key consideration. Cost reduction can be achieved through various means, including increasing solar cell efficiency, increasing silicon wafer size, reducing silicon wafer thickness, and reducing silver consumption. However, solar cell efficiency is the key lever for reducing photovoltaic costs.

[0003] Currently, there are still many challenges in improving the efficiency of industrial batteries. Among them, the contact recombination in the contact area between metal and silicon and the Auger recombination and deep energy level recombination caused by diffusion in the silicon matrix are the main factors restricting the improvement of battery efficiency.

[0004] To reduce recombination rates, extend minority carrier lifetimes, and improve solar cell photoelectric conversion efficiency, the silicon substrate is typically passivated. This creates a passivating contact structure on the silicon substrate surface to reduce surface carrier recombination and mitigate the effects of internal silicon substrate defects. Therefore, the passivating contact structure is a key component of these high-efficiency cells, and optimizing its passivation performance is urgently needed. Summary of the Invention

[0005] Based on this, the present application provides a method for preparing a solar cell, a method for preparing a passivation contact structure, and a solar cell, so as to improve the passivation performance of the passivation contact structure.

[0006] An embodiment of the first aspect of the present application provides a method for preparing a passivation contact structure for a solar cell, comprising the following steps:

[0007] preparing a tunneling silicon oxide layer on a silicon substrate;

[0008] depositing an intrinsic amorphous silicon layer on the tunneling silicon oxide layer;

[0009] Pre-annealing the silicon substrate on which the tunneling silicon oxide layer and the intrinsic amorphous silicon layer are stacked;

[0010] depositing a doped amorphous silicon layer on the pre-annealed intrinsic amorphous silicon layer;

[0011] The silicon substrate on which the tunneling silicon oxide layer, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are deposited is annealed to form a doped polysilicon layer stacked on the tunneling oxide layer.

[0012] In some embodiments, the pre-annealing temperature is higher than the annealing temperature.

[0013] In one embodiment, the step of pre-annealing the silicon substrate stacked with the tunneling silicon oxide layer and the intrinsic amorphous silicon layer is specifically:

[0014] The temperature of the space where the silicon substrate is located is increased from the initial temperature to a first preset temperature and maintained for a first preset time, and finally the temperature of the space where the silicon substrate is located is reduced to the initial temperature.

[0015] In one embodiment, the first preset temperature ranges from 1000° C. to 1200° C., and the first preset time ranges from 0.8 min to 1.3 min.

[0016] In one embodiment, the step of annealing the silicon substrate on which the tunneling silicon oxide layer, the intrinsic amorphous silicon layer, and the doped amorphous silicon layer are deposited is specifically:

[0017] Raising the temperature of the space where the silicon substrate is located from the initial temperature to a second preset temperature and maintaining it for a second preset time, and finally lowering the temperature of the space where the silicon substrate is located to the initial temperature;

[0018] The first preset temperature is greater than the second preset temperature, and the first preset time is less than the second preset time.

[0019] In one embodiment, the second preset temperature ranges from 850° C. to 900° C., and the second preset time ranges from 25 min to 35 min.

[0020] In one embodiment, the processes of preparing the tunneling silicon oxide layer and the intrinsic amorphous silicon layer are both performed in a PECVD device.

[0021] In one embodiment, the step of preparing a tunneling silicon oxide layer on a silicon substrate is specifically as follows:

[0022] Placing a silicon substrate in a diffusion chamber, introducing oxygen and nitrogen into the diffusion chamber, and preparing a tunneling silicon oxide layer by thermal oxidation; wherein the thickness of the tunneling silicon oxide layer is 1 nm to 1.5 nm;

[0023] In one embodiment, during the thermal oxidation process of preparing the tunneling silicon oxide layer, the temperature of the diffusion chamber is maintained at a first preset temperature within a third preset time, the third preset time ranges from 2 min to 5 min, and the first preset temperature ranges from 620°C to 710°C.

[0024] In one embodiment, the tunneling silicon oxide layer, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are sequentially stacked on both the front and back surfaces of the silicon substrate;

[0025] Wherein, one of the doped amorphous silicon layers on the front and back sides of the silicon substrate is a boron-doped amorphous silicon layer, and the thickness of the boron-doped amorphous silicon layer is 90 nm-110 nm.

[0026] In one embodiment, the process of depositing the intrinsic amorphous silicon layer on the tunneling silicon oxide layer is performed in an LPCVD device, and the process of depositing the doped amorphous silicon layer on the pre-annealed intrinsic amorphous silicon layer is performed in a PECVD device.

[0027] An embodiment of the second aspect of the present application provides a method for preparing a solar cell, characterized in that it includes a method for preparing the above-mentioned solar cell passivation contact structure.

[0028] An embodiment of the third aspect of the present application provides a solar cell, characterized in that it is manufactured by the above-mentioned solar cell manufacturing method.

[0029] In the aforementioned method for fabricating a solar cell passivation contact structure, a pre-annealing step is introduced after depositing the intrinsic amorphous silicon layer to open pores in the tunneling silicon oxide layer, aiding carrier transport and improving the passivation performance of the passivation contact structure. Furthermore, by selecting appropriate pre-annealing conditions, the pores in the tunneling silicon oxide layer are controlled to an appropriate size, minimizing the risk of subsequent doping elements from penetrating the tunneling silicon oxide layer and causing interfacial recombination on the silicon substrate surface, further ensuring the passivation effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. The same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0031] Figure 1 This is a flow chart of a method for preparing a solar cell passivation contact structure in some embodiments of the present application.

[0032] Figure 2 Schematic diagram of the structure of the passivation contact structure of the solar cell before annealing in some embodiments of the present application;

[0033] Figure 3 This is a schematic diagram of the structure of the solar cell passivation contact structure after annealing in some embodiments of the present application;

[0034] Figure 4Schematic diagram of the structure of solar cells in other embodiments of the present application;

[0035] Figure 5 This is the secondary ion mass spectrum of the passivated contact structure in Example 3 of the present application;

[0036] Figure 6 Schematic diagram of the relationship between the open circuit voltage and the thickness of the tunnel oxide layer of the passivation contact structure in Example 4 of the present application;

[0037] Figure 7 Schematic diagram of the relationship between the thickness of the tunneling silicon oxide layer and the oxidation time in Example 4 of the present application;

[0038] Figure 8 Schematic diagram of the relationship between the thickness of the tunneling silicon oxide layer and the oxygen flow rate in Example 4 of the present application;

[0039] Figure 9 Schematic diagram of the relationship between the thickness of the tunneling silicon oxide layer and the oxidation temperature in Example 4 of the present application;

[0040] Figure 10 Schematic diagram of the relationship between the thickness of the boron-doped amorphous silicon layer and the open-circuit voltage of the passivation contact structure in Example 5 of the present application;

[0041] Figure 11 Schematic diagram of the structure of the passivated contact structure surface in the comparative example of Example 6 of the present application;

[0042] Figure 12 This is a schematic structural diagram of the passivated contact structure surface in Example 6 of the present application.

[0043] Explanation of reference numerals: 100, solar cell passivation contact structure; 10, silicon substrate; 30, tunneling silicon oxide layer; 40, intrinsic amorphous silicon layer; 50, doped amorphous silicon layer; 70, doped polysilicon layer. DETAILED DESCRIPTION

[0044] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0045] In the description of this application, it should be understood that if the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. appear, the orientation or position relationship indicated by these terms is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0046] In addition, if the terms "first" or "second" appear, these terms are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature specified as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, if the term "plurality" appears, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0047] In this application, unless otherwise specified or limited, the terms "mounted," "connected," "connected," "fixed," etc., should be interpreted broadly. For example, these terms may refer to fixed connections, removable connections, or integration; mechanical connections or electrical connections; direct connections or indirect connections through an intermediary; and internal communication between two components or interaction between two components, unless otherwise specified. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0048] In this application, unless otherwise expressly specified or limited, if a first feature is described as being "above" or "below" a second feature, or similar descriptions, this may mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is described as being "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is described as being "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0049] It should be noted that if an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. If an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. If any, the terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in this application are for illustrative purposes only and do not represent the only embodiment.

[0050] See Figure 1-Figure 2 In one embodiment of the present application, a method for preparing a solar cell passivation contact structure 100 is provided, which specifically includes the following steps:

[0051] Step S100: Forming a tunneling silicon oxide layer 30 on the silicon substrate 10. In some embodiments, the tunneling silicon oxide layer 30 is formed on at least one of the front and back surfaces of the silicon substrate 10. It is understood that the tunneling silicon oxide layer 30 can be formed by processes such as ALD (Atomic Layer Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PEALD (Plasma Enhanced Atomic Layer Deposition), and LPCVD (Low Pressure Chemical Vapor Deposition).

[0052] Optionally, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used to form the tunneling silicon oxide layer 30. Optionally, the PECVD RF (Radio Frequency) power is 1.5 W, the gas introduced during vapor deposition is 50 sccm N2O, the working pressure is 0.08 mbar, the deposition time is approximately 9 minutes, the thickness is approximately 1.3 nm, and the deposition temperature is 200°C.

[0053] Step S300: Depositing an intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30. In some embodiments, the tunneling silicon oxide layer 30 is formed on at least one of the front and back surfaces of the silicon substrate 10, and the intrinsic amorphous silicon layer 40 is correspondingly deposited on the tunneling silicon oxide layer 30 on one or both surfaces of the silicon substrate 10. It is understood that the intrinsic amorphous silicon layer 40 can be prepared using processes such as PECVD (Plasma Enhanced Chemical Vapor Deposition) and LPCVD (Low Pressure Chemical Vapor Deposition).

[0054] According to some embodiments of the present application, a PECVD (Plasma Enhanced Chemical Vapor Deposition) process is used to form the intrinsic amorphous silicon layer 40. Optionally, the PECVD RF (Radio Frequency) power is 5W, the gases introduced during deposition are 8sccm SiH4, 2sccm CO2, and 100sccm H2, the working pressure is 2mbar, the deposition temperature is 200°C, the deposition time is 1 min-1.5 min, for example, the deposition time is 1 min 0.8 s, and the thickness is 9-12 nm, for example, 10 nm.

[0055] In step S500, the silicon substrate 10, which is laminated with the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40, is pre-annealed. This pre-annealing step is performed after the deposition of the intrinsic amorphous silicon to open pores in the tunneling silicon oxide layer 30, aiding carrier transport and improving the passivation performance of the passivation contact structure. Furthermore, by selecting appropriate pre-annealing conditions, the pores in the tunneling silicon oxide layer 30 are controlled to an appropriate size, minimizing the risk of subsequent doping elements from passing through the tunneling silicon oxide layer 30 and causing interfacial recombination on the surface of the silicon substrate 10, further ensuring the passivation effect.

[0056] In some embodiments, the temperature of the space surrounding the silicon substrate 10 is raised from an initial temperature to a first predetermined temperature and maintained for a first predetermined time. Finally, the temperature of the space surrounding the silicon substrate 10 is lowered back to the initial temperature. Thus, the temperature of the space surrounding the silicon substrate 10 is raised to the first predetermined temperature and maintained for a first predetermined time to perform a pre-annealing operation. Finally, the temperature of the space surrounding the silicon substrate 10 is lowered back to the initial temperature. This cooling process is also important because it allows the pre-annealed film layers to return to a stable state, preparing for subsequent processes.

[0057] Furthermore, the first preset temperature ranges from 1000°C to 1200°C, for example, the first preset temperature is 1025°C, and the first preset duration ranges from 0.8 min to 1.3 min, for example, the first preset duration is 1 min. This provides a short ultra-high temperature pre-annealing process, which can open some holes in the tunnel oxide layer at a higher temperature without damaging the film layer due to excessively long high temperature time. At the same time, by providing an appropriate temperature and duration, the size of the holes in the tunnel oxide layer is controlled, preventing the subsequently doped dopant elements from passing through the tunnel oxide layer and causing interfacial recombination on the surface of the silicon substrate 10, further ensuring the passivation effect.

[0058] Optionally, nitrogen is filled into the space where the silicon substrate 10 is located to protect the film layer formed on the silicon substrate 10 and prevent the film layer from chemical reaction.

[0059] In step S700, a doped amorphous silicon layer 50 is deposited on the pre-annealed intrinsic amorphous silicon layer 40. It is understood that the doped amorphous silicon layer 50 may be a boron-doped amorphous silicon layer 50 or a phosphorus-doped amorphous silicon layer 50.

[0060] In some embodiments, the doped amorphous silicon layer 50 may be prepared by processes such as PECVD (Plasma Enhanced Chemical Vapor Deposition), spin coating, or printing.

[0061] Specifically in one embodiment, the doped amorphous silicon layer 50 is deposited by PECVD, the PECVD RF (Radio Frequency) power is 5W, the gases introduced during deposition are 8sccm SiH4, 2sccm C02, 100sccm H2, 5sccm B2H6, the working pressure is Wie2 mbar, the deposition temperature is 200°C, the deposition time is 2min-2.5min, for example, the deposition time is 2min16s, and the thickness is 19nm-21nm, for example, the thickness is 20nm.

[0062] See Figure 3 In step S900, the silicon substrate 10 on which the tunneling silicon oxide layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer 50 are deposited is annealed to form a doped polysilicon layer 70 stacked on the tunneling silicon oxide layer 30. It is understood that by annealing the silicon substrate 10 on which the tunneling silicon oxide layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer 50 are deposited, the doped amorphous silicon layer 50 and the intrinsic amorphous silicon layer 40 are annealed to relieve stress and then fuse into a doped polysilicon layer 70 with a stable internal structure, thereby forming a passivation contact structure formed by the doped polysilicon layer 70 and the tunneling oxide layer to reduce carrier recombination.

[0063] Optionally, the pre-annealing temperature is higher than the annealing temperature. Thus, performing an ultra-high temperature pre-annealing operation on the tunnel oxide layer before annealing can open some holes in the tunnel oxide layer 30, thereby assisting carrier transport. Furthermore, the high temperature of the pre-annealing process can effectively open some holes in the tunnel oxide layer.

[0064] In some embodiments, the temperature of the space where the silicon substrate 10 is located is increased from the initial temperature to a second preset temperature and maintained for a second preset time, and finally the temperature of the space where the silicon substrate 10 is located is reduced to the initial temperature; wherein the first preset temperature is greater than the second preset temperature, and the first preset time is less than the second preset time.

[0065] It can be understood that an annealing process with a lower temperature and longer duration than the pre-annealing process is provided, and the temperature of the space where the silicon substrate 10 is located is raised to a second preset temperature and maintained for a second preset time, so that the doping elements in the doped amorphous silicon layer 50 on the silicon substrate 10 are heated and diffused to the intrinsic amorphous silicon layer 40, and the two are melted into one layer, while the amorphous silicon is converted into polycrystalline silicon. Finally, the temperature of the space where the silicon substrate 10 is located is lowered to the initial temperature to complete the annealing process.

[0066] Furthermore, the second preset temperature range is 850°C-900°C, for example, the second preset temperature is 875°C, and the second preset time range is 25min-35min, for example, the second preset time is 30min. This corresponds to the pre-annealing process and matches the appropriate post-annealing conditions to ensure the overall annealing effect.

[0067] In some embodiments, the processes of preparing the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40 are both carried out in a PECVD device, that is, after the tunneling silicon oxide layer 30 is vapor-deposited by the PECVD device, the intrinsic amorphous silicon layer 40 is continued to be deposited in situ without destroying the vacuum. The steps of preparing the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40 are both carried out in the same PECVD device, and there is no need to replace the equipment. The preparation process is simple and efficient.

[0068] Specifically, when PECVD was used to deposit the tunneling silicon oxide layer 30, the PECVD RF (Radio Frequency) power was 1.5W, the gas introduced during vapor deposition was 50sccm N2O, the operating pressure was 0.08mbar, the deposition time was approximately 9 minutes, and the thickness was approximately 1.3nm. When PECVD was used to deposit the intrinsic amorphous silicon layer 40, the PECVD RF (Radio Frequency) power was 5W, the gas introduced during vapor deposition was 8sccm SiH4, 2sccm CO2, 100sccm H2, the operating pressure was 2mbar, the deposition time was approximately 1 minute 08 seconds, and the thickness was approximately 10nm.

[0069] In some embodiments, nitrogen is introduced into the space where the silicon substrate 10 is located during the pre-annealing and / or annealing process to protect the film layer on the silicon substrate 10 during the pre-annealing and annealing process, prevent the film layer on the silicon substrate 10 from undergoing chemical reactions, protect the film layer on the silicon substrate 10, and ensure the pre-annealing and annealing effects.

[0070] Optionally, the pre-annealing and / or annealing process is performed in a tubular annealing furnace, and nitrogen gas may be introduced into the tubular annealing furnace to perform the pre-annealing or annealing process.

[0071] In the above-described method for fabricating the solar cell passivation contact structure 100, a pre-annealing step is introduced after depositing the intrinsic amorphous silicon layer 40 to open pores in the tunneling silicon oxide layer 30, aiding carrier transport and improving the passivation performance of the passivation contact structure. Furthermore, by selecting appropriate pre-annealing conditions, the pores in the tunneling silicon oxide layer 30 are controlled to an appropriate size, minimizing the risk of subsequent doping elements from passing through the tunneling silicon oxide layer 30 and causing interfacial recombination on the surface of the silicon substrate 10, further ensuring the passivation effect.

[0072] In order to objectively evaluate the technical effects of the above embodiments of the present application, the present application will be described in detail and exemplarily through the following embodiments.

[0073] Example 1

[0074] The preparation method of the solar cell passivation contact structure 100 provided in Example 1 is as follows:

[0075] Step S1, cleaning and texturing the surface of the silicon substrate 10; pre-cleaning the N-type silicon substrate 10, followed by double-sided texturing to form a uniformly textured surface on both sides of the silicon substrate 10, followed by RCA-1 and RCA-2 to clean organic matter and metal ions from the textured surface, then smoothing the surface pyramids, and finally removing the surface oxide layer with hydrofluoric acid;

[0076] Step S2: Forming a tunneling silicon oxide layer 30 on the silicon substrate 10 using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. Optionally, the PECVD RF (Radio Frequency) power is 1.5 W, the gas introduced during vapor deposition is 50 sccm N2O, the operating pressure is 0.08 mbar, the deposition time is approximately 9 minutes, the thickness is approximately 1.3 nm, and the deposition temperature is 200°C.

[0077] In step S3, an intrinsic amorphous silicon layer 40 is deposited on the tunneling silicon oxide layer 30. The intrinsic amorphous silicon layer 40 is prepared using a PECVD (Plasma Enhanced Chemical Vapor Deposition) process. Optionally, the PECVD RF (Radio Frequency) power is 5W, the gases introduced during deposition are 8sccm SiH4, 2sccm CO2, and 100sccm H2, the working pressure is 2mbar, the deposition temperature is 200°C, the deposition time is 1min-1.5min, for example, the deposition time is 1min08s, and the thickness is 9-12nm, for example, the thickness is 10nm.

[0078] In step S4, the silicon substrate 10 stacked with the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40 is pre-annealed. The temperature of the space surrounding the silicon substrate 10 is raised from the initial temperature to a first preset temperature and maintained for a first preset time. Finally, the temperature of the space surrounding the silicon substrate 10 is lowered back to the initial temperature. The first preset temperature ranges from 1000°C to 1200°C, for example, 1025°C, and the first preset time ranges from 0.8 minutes to 1.3 minutes, for example, 1 minute.

[0079] In step S5, a doped amorphous silicon layer 50 is deposited on the pre-annealed intrinsic amorphous silicon layer 40. The doped amorphous silicon layer 50 is a boron-doped amorphous silicon layer 50. The doped amorphous silicon layer 50 is deposited by PECVD. The PECVD RF (Radio Frequency) power is 5 W. The gases introduced during deposition are 8 sccm SiH4, 2 sccm CO2, 100 sccm H2, and 5 sccm B2H6. The working pressure is 2 mbar. The deposition temperature is 200°C. The deposition time is 2 min-2.5 min, for example, 2 min 16 s. The thickness is 19 nm-21 nm, for example, 20 nm.

[0080] In step S6, the silicon substrate 10 on which the tunneling silicon oxide layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer 50 are deposited is annealed to form a doped polysilicon layer 70 stacked on the tunneling oxide layer. The temperature of the space in which the silicon substrate 10 is located is increased from the initial temperature to a second preset temperature and maintained for a second preset time. Finally, the temperature of the space in which the silicon substrate 10 is located is reduced to the initial temperature; wherein the first preset temperature is greater than the second preset temperature, and the first preset time is less than the second preset time. The second preset temperature ranges from 850°C to 900°C, for example, the second preset temperature is 875°C, and the second preset time ranges from 25min to 35min, for example, the second preset time is 30min.

[0081] After testing, as shown in Table 1 below, for the boron-doped passivation contact structure in Example 1, the introduction of the pre-annealing operation increases the iVoc (implied Voc implied open circuit voltage) by 10.4 mV compared to not introducing the pre-annealing operation, and the passivation performance is improved.

[0082] No pre-annealing Pre-annealing iVoc=678.7mV iVoc=689.1mV

[0083] Table 1

[0084] Example 2

[0085] The method for preparing the solar cell passivation contact structure 100 in Example 2 is substantially the same as the method for preparing the solar cell in Example 1, except that:

[0086] In step S5 , a doped amorphous silicon layer 50 is deposited on the pre-annealed intrinsic amorphous silicon layer 40 . The doped amorphous silicon layer 50 is a phosphorus-doped amorphous silicon layer 50 .

[0087] After testing, as shown in Table 2 below, for the phosphorus-doped passivation contact structure in Example 2, the introduction of the pre-annealing operation increases the iVoc (implied Voc) by 43.9 mV compared to not introducing the pre-annealing operation, and the passivation performance is improved.

[0088] No pre-annealing Pre-annealing iVoc=683.5mV iVoc=727.4mV

[0089] Table 2

[0090] In other embodiments of the present application, a method for preparing a solar cell is provided, including the method for preparing the solar cell passivation contact structure 100 described in any of the above embodiments.

[0091] The beneficial technical effects of the solar cell manufacturing method provided in the embodiment of the present application are the same as the beneficial technical effects of the solar cell passivation contact structure 100 provided in the embodiment of the present application, and are not repeated here.

[0092] According to other embodiments of the present application, step S10 of preparing a tunneling silicon oxide layer 30 on a silicon substrate 10 is specifically as follows: placing the silicon substrate 10 in a diffusion chamber, introducing oxygen and nitrogen into the diffusion chamber, and preparing the tunneling silicon oxide layer 30 by a thermal oxidation method. For example, the tunneling silicon oxide layer 30 can be prepared by LPCVD (Low Pressure Chemical Vapor Deposition). In this way, the tunneling silicon oxide layer 30 is prepared by thermal oxidation, and the Si in the formed tunneling silicon oxide layer 30 is 4+The content is relatively high, the quality of the tunneling silicon oxide layer 30 is good, and the formed film is relatively dense, which can prevent the subsequent doping elements from diffusing into the silicon substrate 10 to the greatest extent. The tunneling oxide as a passivation contact structure is more qualified, and the passivation performance of the passivation contact structure is effectively improved.

[0093] The thickness of the tunneling silicon oxide layer 30 is 1 nm to 1.5 nm. By selecting an appropriate thickness of the tunneling silicon oxide layer 30, the open circuit voltage of the passivation contact structure can be increased, thereby improving the passivation performance of the passivation contact structure. For example, the thickness of the tunneling silicon oxide layer 30 is 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, or 1.5 nm. Optionally, the thickness of the tunneling silicon oxide layer 30 is 1.2 nm. This configuration can provide the passivation contact structure with better passivation performance.

[0094] Furthermore, in the process of preparing the tunneling silicon oxide layer 30 by the thermal oxidation method, the temperature of the diffusion chamber is maintained at the first preset temperature within the third preset time, and the range of the third preset time is 2min-5min, for example, the third preset time is 2min, 3min, 4min, 5min, and the range of the first preset temperature is 620℃-710℃, for example, the first preset temperature is 620℃, 650℃, 675℃, 700℃, 710℃. In this way, the parameters for preparing the tunneling silicon oxide layer 30 by the thermal oxidation method are reasonably set to prepare a tunneling silicon oxide layer 30 with a thickness of 1nm-1.5nm.

[0095] Optionally, the third preset time is 3 minutes; further optionally, the first preset temperature is 675° C. Specifically, during the process of forming the tunneling silicon oxide layer 30 , 6.0 SLM of nitrogen and 0.6 SLM of oxygen are introduced into the diffusion chamber. At 675° C. for 3 minutes, a tunneling oxide film with a thickness of approximately 1.3 nm can be formed.

[0096] According to some embodiments of the present application, step S300 of depositing an intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30 specifically comprises placing the silicon substrate 10 having the tunneling silicon oxide layer 30 formed thereon into a first process chamber, filling the first process chamber with a first reaction gas, and depositing the intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30. The first reaction gas comprises silane and hydrogen. Thus, when the silane and hydrogen are filled into the first process chamber, the silane and hydrogen react in the first process chamber, and the intrinsic amorphous silicon layer 40 is deposited on the tunneling silicon oxide layer 30.

[0097] Furthermore, step S700 of depositing the doped amorphous silicon layer 50 on the pre-annealed intrinsic amorphous silicon layer 40 specifically comprises placing the silicon substrate 10 formed with the intrinsic amorphous silicon layer 40 and the tunneling silicon oxide layer 30 into a second process chamber, filling the second process chamber with a second reaction gas, and depositing the doped amorphous silicon layer 50 on the intrinsic amorphous silicon layer 40. The second reaction gas comprises a dopant source gas, silane, and hydrogen. Thus, the dopant source gas, silane, and hydrogen are filled into the second process chamber, and the dopant source gas, silane, and hydrogen chemically react within the second process chamber to form the doped amorphous silicon layer 50 deposited on the intrinsic amorphous silicon layer 40.

[0098] It can be understood that the doping source gas may be a boron doping gas or a phosphorus doping gas to form a boron doped amorphous silicon layer 50 or a phosphorus doped amorphous silicon layer 50 .

[0099] Specifically, the process of depositing the intrinsic amorphous silicon layer 40 is performed in an LPCVD apparatus equipped with a first process chamber, while the process of depositing the doped amorphous silicon layer 50 is performed in a PECVD apparatus equipped with a second process chamber. During the fabrication process, silane and hydrogen are first introduced into the first process chamber of the LPCVD apparatus. The silane and hydrogen react chemically within the first process chamber, depositing the intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30. The silicon substrate 10, with the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40 deposited thereon, is then transferred to the second process chamber of the PECVD apparatus. A dopant source gas, silane, and hydrogen are introduced into the second process chamber. The silane and hydrogen react chemically within the second process chamber, depositing the doped amorphous silicon layer 50 on the intrinsic amorphous silicon layer 40.

[0100] Compared to PECVD deposition of the intrinsic amorphous silicon layer 40, LPCVD deposition of the intrinsic amorphous silicon layer 40 achieves a slower deposition rate, resulting in a denser film with lower hydrogen content. Furthermore, the post-LPCVD deposition process involves a heat-retention stress release process, further improving the film's density and reducing hydrogen content. In other words, by reducing the hydrogen content in the intrinsic amorphous silicon layer 40 in these two ways, less hydrogen escapes during the subsequent annealing process, preventing film bursting in the solar cell's passivation contact structure.

[0101] According to some embodiments of the present application, a tunneling silicon oxide layer 30, an intrinsic amorphous silicon layer 40, and a doped amorphous silicon layer 50 are sequentially stacked on both the front and back surfaces of the silicon substrate 10, and one of the doped amorphous silicon layers 50 on both the front and back surfaces of the silicon substrate 10 is a boron-doped amorphous silicon layer 50. It can be understood that by stacking the tunneling silicon oxide layer 30, the intrinsic amorphous silicon layer 40, and the doped amorphous silicon layer on both the front and back surfaces of the silicon substrate 10, a passivated contact structure is prepared on both the front and back surfaces of the silicon substrate 10 to prevent carrier interfacial recombination on the front and back surfaces of the silicon substrate 10 and to facilitate carrier transport.

[0102] Optionally, the boron-doped amorphous silicon layer 50 has a thickness of 90 nm to 110 nm, for example, 90 nm, 95 nm, 100 nm, 115 nm, or 110 nm. Selecting an appropriate thickness for the boron-doped amorphous silicon layer 50 increases the open-circuit voltage of the passivation contact structure and enhances passivation performance. Preferably, the boron-doped amorphous silicon layer 50 has a thickness of 100 nm, which provides the passivation contact structure with an optimal open-circuit voltage.

[0103] It is understandable that in some other embodiments, the tunneling silicon oxide layer 30 , the intrinsic amorphous silicon layer 40 and the doped amorphous silicon layer 50 are stacked only on one side of the silicon substrate 10 , and a passivation contact structure is prepared on one side of the silicon substrate 10 .

[0104] In the above-mentioned method for preparing the solar cell passivation contact structure 100, the tunneling silicon oxide layer 30 is prepared by thermal oxidation. 4+ The high content of silicon oxide (SiO2) provides high-quality tunneling silicon oxide layer 30, and the resulting film is dense, minimizing the diffusion of subsequently doped elements into silicon substrate 10. This makes the tunneling oxide layer 30 a qualified passivation contact structure, effectively improving the passivation performance of the passivation contact structure. Furthermore, the thickness of tunneling silicon oxide layer 30 is between 1 nm and 1.5 nm. By selecting an appropriate thickness for tunneling silicon oxide layer 30, the open-circuit voltage of the passivation contact structure can be further increased, thereby enhancing the passivation performance of the passivation contact structure.

[0105] In order to objectively evaluate the technical effects of the above embodiments of the present application, the present application will be described in detail and exemplarily through the following embodiments.

[0106] Example 3

[0107] The preparation method of the solar cell passivation contact structure 100 provided in Example 3 is as follows:

[0108] Step S1, cleaning and texturing the surface of the silicon substrate 10; pre-cleaning the silicon substrate 10, and then texturing the light incident surface of the silicon substrate 10, that is, the front side of the silicon substrate 10, to form a textured surface of uniform size on the front side, and then through RCA-1 and RCA-2, clean the organic matter and metal ions on the textured surface of the light incident surface of the battery, and then smooth the surface pyramid, and finally use hydrofluoric acid to remove the surface oxide layer.

[0109] In step S2, the silicon substrate 10 is placed in a diffusion chamber, oxygen and nitrogen are introduced into the diffusion chamber, and a tunneling silicon oxide layer 30 is formed on both sides of the silicon substrate 10 by thermal oxidation. It is understood that the tunneling silicon oxide layer 30 is formed by LPCVD (Low Pressure Chemical Vapor Deposition).

[0110] In step S3 , an intrinsic amorphous silicon layer 40 and a doped amorphous silicon layer 50 are deposited on the tunneling silicon oxide layer 30 . The doped amorphous silicon layer 50 incorporates doping elements, and the intrinsic amorphous silicon layer 40 blocks the doping elements in the doped amorphous silicon layer 50 from penetrating into the silicon substrate 10 .

[0111] It can be understood that after the intrinsic amorphous silicon layer 40 is deposited on the tunneling silicon oxide layer 30, the silicon substrate 10 on which the tunneling silicon oxide layer 30 and the intrinsic amorphous silicon layer 40 are deposited is pre-annealed, and then the doped amorphous silicon layer is deposited on the intrinsic amorphous silicon layer. That is to say, after the intrinsic amorphous silicon is deposited, a pre-annealing operation is introduced to open some holes in the tunneling silicon oxide layer 30 to assist the transport of carriers and improve the passivation performance of the passivation contact structure. At the same time, by selecting appropriate pre-annealing conditions, the holes in the tunneling silicon oxide layer 30 are controlled to a suitable size, and the subsequent doping elements are prevented from passing through the tunneling silicon oxide layer 30 and undergoing interfacial recombination on the surface of the silicon substrate 10, thereby further ensuring the passivation effect. In this way, the passivation performance of the passivation contact structure is further improved through the pre-annealing process.

[0112] Step S5, annealing at a temperature of 900°C-950°C for 30 minutes in a tubular annealing furnace to form a phosphorus-doped polysilicon layer 70 on the front side of the silicon substrate 10, and a boron-doped polysilicon layer 70 on the back side of the silicon substrate 10. In this way, the corresponding tunneling silicon oxide layer 30 on the front side of the silicon substrate 10 cooperates with the phosphorus-doped polysilicon layer 70 to form a passivation contact structure, and the corresponding tunneling silicon oxide layer 30 on the back side of the silicon substrate 10 cooperates with the boron-doped polysilicon layer 70 to form another passivation contact structure. In this way, passivation contact structures are prepared on both the front and back sides of the silicon substrate 10.

[0113] In Example 3, to verify the quality of the tunneling silicon oxide layer 30 prepared by the thermal oxidation method, three methods for preparing the tunneling silicon oxide layer 30 were compared. The first method used a wet chemical method to prepare a silicon oxide film, referred to as the NAOS (Nitric Acid Oxidation of Silicon) method. The specific operation was as follows: at room temperature, the silicon substrate 10 that had completed the cleaning step was immersed in a 69.5% nitric acid solution for 60 minutes, forming a tunneling silicon oxide layer 30 with a thickness of approximately 1.3-1.5 nm. The second method used a PECVD device to deposit a silicon oxide film by introducing N2O gas, referred to as the PANO (Plasma Assisted N2O Oxidation) method. The specific operation was as follows: the PECVD RF power was 1.5 W, the deposition pressure was 0.08 mbar, the N2O gas flow rate was 50 sccm, and the PECVD deposition time was approximately 9 minutes. The third method is the method described in Example 3, which uses LPCVD equipment to prepare a silicon oxide film, referred to as t-SiOx (thermal silicon oxide). The specific operation is to introduce nitrogen and oxygen and deposit them at high temperature for a period of time to form a tunneling oxide film.

[0114] First, as shown in Table 3 below, it is found through XPS (X-ray photoelectron spectroscopy) characterization that the Si in the tunneling silicon oxide layer 30 prepared by the thermal oxidation method is 4+ The content is the highest, reflecting that its quality is the best, the film formed is the densest, and it is the most qualified as a tunneling oxide for passivation contact structure.

[0115]

[0116] Table 3

[0117] Secondly, if Figure 5 As shown, SIMS (Secondary Ion Mass Spectrometry) characterization of boron-doped passivation structures composed of tunneling silicon oxide layers 30 prepared by three different methods reveals that tunneling silicon oxide layer 30 prepared by thermal oxidation (abbreviated as t-SiOx) can best prevent boron diffusion into bulk silicon and has the best quality. In summary, silicon oxide prepared by thermal oxidation is the most suitable as the tunneling oxide for boron-doped passivation contact structures.

[0118] Example 4

[0119] The method for preparing the solar cell passivation contact structure 100 in Example 4 is substantially the same as the method for preparing the solar cell in Example 3, except that:

[0120] In step S2, the silicon substrate 10 is placed in a diffusion chamber, oxygen and nitrogen are introduced into the diffusion chamber, and a tunneling silicon oxide layer 30 is formed on both sides of the silicon substrate 10 by thermal oxidation. The thickness of the tunneling silicon oxide layer 30 is 1.2 nm. In this way, by selecting an appropriate thickness of the tunneling silicon oxide layer 30, the open circuit voltage of the passivation contact structure can be improved, and the passivation performance of the passivation contact structure can be improved. The specific operation is to introduce 6.0 SLM of nitrogen and 0.6 SLM of oxygen, and deposit at 675°C for 3 minutes to form a 1.2 nm thick tunneling oxide film.

[0121] For Example 4, Figure 6-Figure 9 As shown, the oxidation time, oxygen flow rate, and oxidation temperature during the thermal oxidation process of preparing the tunneling silicon oxide layer 30 will affect the thickness of the tunneling silicon oxide layer 30, and the thickness of the tunneling silicon oxide layer 30 will also affect the open circuit voltage of the passivation contact structure.

[0122] Depend on Figure 6 It can be seen that, whether after PDA (Post Deposition Annealing) or after Hydrogenation, the 1.3nm thick tunneling silicon oxide layer 30 can bring the best chemical passivation effect for the boron-doped passivation contact structure. Figure 7-Figure 9 It can be seen that the most suitable temperature and time for preparing the tunneling silicon oxide layer 30 with a thickness of 1.3 nm are 675° C. and 3 minutes of oxidation.

[0123] Example 5

[0124] The method for preparing the solar cell passivation contact structure 100 in Example 5 is substantially the same as the method for preparing the solar cell in Example 3, except that:

[0125] In step S4, the silicon substrate 10 having the intrinsic amorphous silicon layer 40 and the tunneling silicon oxide layer 30 is placed in the second process chamber of the PECVD equipment, and a phosphorus-doped amorphous silicon layer 50 is deposited on the front surface of the silicon substrate 10, and a boron-doped amorphous silicon layer 50 with a thickness of 100 nm is deposited on the back surface of the silicon substrate 10.

[0126] like Figure 10 As shown, the open circuit voltage (iVOC) of the passivation contact structure varies with the thickness of the boron-doped polysilicon layer 70 (poly-SiOX:H(p)), and the most suitable poly-SiOX:H(p) thickness is 100nm, at which the open circuit voltage is the largest and the best passivation effect can be produced.

[0127] Example 6

[0128] The method for preparing the solar cell passivation contact structure 100 in Example 6 is substantially the same as the method for preparing the solar cell in Example 3, except that:

[0129] Step S3 specifically includes the following steps:

[0130] In step S31, a silicon substrate 10 having a tunneling silicon oxide layer 30 formed thereon is placed into a first process chamber of an LPCVD device. A first reaction gas is introduced into the first process chamber to deposit an intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30 on both sides of the silicon substrate 10. The first reaction gas comprises silane and hydrogen. As the silane and hydrogen are introduced into the first process chamber, a chemical reaction occurs within the first process chamber, depositing the intrinsic amorphous silicon layer 40 on the tunneling silicon oxide layer 30.

[0131] In step S33, the silicon substrate 10 having the intrinsic amorphous silicon layer 40 and the tunneling silicon oxide layer 30 is placed in the second process chamber of the PECVD equipment, and a phosphorus-doped amorphous silicon layer 50 is deposited on the front surface of the silicon substrate 10, and a boron-doped amorphous silicon layer 50 is deposited on the back surface of the silicon substrate 10.

[0132] like Figure 11 As shown, in the comparative example of Example 6, when the boron-doped polysilicon layer 70 is prepared by the in-situ doping method using PECVD equipment, it is often found that the film will have the problem of film bursting, affecting the passivation performance of the film. This is due to the overflow of hydrogen and the stress problem of the film during the high-temperature annealing crystallization process.

[0133] In Example 6, LPCVD equipment was used to introduce oxygen and nitrogen into the thermal oxidation process to prepare tunneling silicon oxide, and then silane and hydrogen were introduced to prepare the intrinsic amorphous silicon layer 40. Finally, PECVD equipment was used to introduce silane, hydrogen, carbon dioxide and borane to prepare a boron-doped hydrogenated amorphous silicon oxide film. Figure 12 As shown, the boron-doped polysilicon layer 70 formed by high-temperature annealing of the intrinsic amorphous silicon film layer and the boron-doped hydrogenated amorphous silicon oxide film layer in Example 6 does not exhibit film bursting.

[0134] It can be seen that depositing the intrinsic amorphous silicon layer 40 by LPCVD can reduce the hydrogen content in the intrinsic amorphous silicon layer 40, thereby preventing hydrogen overflow from the surface of the passivation contact structure after annealing and causing film explosion.

[0135] According to some embodiments of the present application, a method for preparing a solar cell is further provided, including the method for preparing the solar cell passivation contact structure 100 described in any of the above embodiments.

[0136] The beneficial technical effects of the solar cell manufacturing method provided in the embodiment of the present application are the same as the beneficial technical effects of the solar cell passivation contact structure 100 provided in the embodiment of the present application, and are not repeated here.

[0137] According to some embodiments of the present application, a solar cell is further provided, which is manufactured by the solar cell manufacturing method described in any of the above embodiments.

[0138] The beneficial technical effects of the solar cell provided by the embodiment of the present application and the beneficial technical effects of the method for preparing the solar cell passivation contact structure 100 provided by the embodiment of the present application are the same, and will not be repeated here.

[0139] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a passivation contact structure for a solar cell, characterized in that: The following steps are involved: preparing a tunneling silicon oxide layer on a silicon substrate; depositing an intrinsic amorphous silicon layer on the tunneling silicon oxide layer; Pre-annealing the silicon substrate on which the tunneling silicon oxide layer and the intrinsic amorphous silicon layer are stacked; depositing a doped amorphous silicon layer on the pre-annealed intrinsic amorphous silicon layer; Annealing the silicon substrate on which the tunneling silicon oxide layer, the intrinsic amorphous silicon layer, and the doped amorphous silicon layer are deposited to form a doped polysilicon layer stacked on the tunneling silicon oxide layer; The pre-annealing temperature is higher than the annealing temperature. The pre-annealing temperature ranges from 1000°C to 1200°C, and the annealing temperature ranges from 850°C to 900°C.

2. The method for preparing a solar cell passivation contact structure according to claim 1, wherein: The step of pre-annealing the silicon substrate stacked with the tunneling silicon oxide layer and the intrinsic amorphous silicon layer is specifically: The temperature of the space where the silicon substrate is located is increased from the initial temperature to the pre-annealing temperature and maintained for a first preset time, and finally the temperature of the space where the silicon substrate is located is reduced to the initial temperature.

3. The method for preparing a solar cell passivation contact structure according to claim 2, characterized in that: The first preset time length ranges from 0.8 min to 1.3 min.

4. The method for preparing a solar cell passivation contact structure according to claim 2, wherein: The step of annealing the silicon substrate on which the tunneling silicon oxide layer, the intrinsic amorphous silicon layer, and the doped amorphous silicon layer are deposited is specifically: Raising the temperature of the space where the silicon substrate is located from the initial temperature to the annealing temperature and maintaining it for a second preset time, and finally lowering the temperature of the space where the silicon substrate is located to the initial temperature; The first preset time length is shorter than the second preset time length.

5. The method for preparing a solar cell passivation contact structure according to claim 4, characterized in that: The second preset duration ranges from 25 minutes to 35 minutes.

6. The method for preparing a solar cell passivation contact structure according to any one of claims 1 to 5, characterized in that: The processes of preparing the tunneling silicon oxide layer and the intrinsic amorphous silicon layer are both carried out in PECVD equipment.

7. The method for preparing a solar cell passivation contact structure according to any one of claims 1 to 5, characterized in that: The steps of preparing a tunneling silicon oxide layer on a silicon substrate are specifically as follows: A silicon substrate is placed in a diffusion chamber, oxygen and nitrogen are introduced into the diffusion chamber, and a tunneling silicon oxide layer is prepared by a thermal oxidation method; wherein the thickness of the tunneling silicon oxide layer is 1nm-1.5nm.

8. The method for preparing a solar cell passivation contact structure according to claim 7, characterized in that: During the thermal oxidation process of preparing the tunneling silicon oxide layer, the temperature of the diffusion chamber is maintained at the first preset temperature within a third preset time, the third preset time ranges from 2 minutes to 5 minutes, and the first preset temperature ranges from 620°C to 710°C.

9. The method for preparing a solar cell passivation contact structure according to claim 7, characterized in that: The tunneling silicon oxide layer, the intrinsic amorphous silicon layer and the doped amorphous silicon layer are sequentially stacked on both the front and back surfaces of the silicon substrate; Wherein, one of the doped amorphous silicon layers on the front and back sides of the silicon substrate is a boron-doped amorphous silicon layer, and the thickness of the boron-doped amorphous silicon layer is 90 nm-110 nm.

10. The method for preparing a solar cell passivation contact structure according to any one of claims 1 to 5, characterized in that: The process of depositing the intrinsic amorphous silicon layer on the tunneling silicon oxide layer is carried out in an LPCVD device, and the process of depositing the doped amorphous silicon layer on the pre-annealed intrinsic amorphous silicon layer is carried out in a PECVD device.

11. A method for preparing a solar cell, characterized in that: A method for preparing a solar cell passivation contact structure comprising the steps of any one of claims 1 to 9.

12. A solar cell, characterized in that: The solar cell is manufactured by the method for manufacturing the solar cell according to claim 11.

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