Level converter chip and display panel

Abstract

The present application provides a level converter chip and a display panel. The level converter chip includes multiple switch modules, multiple detection modules and a control unit. The multiple switch modules boost the original signal to obtain a first control signal; the switch module includes multiple thin film transistors, multiple thin film transistors of the same switch module are connected in parallel, and the gate-drain parasitic capacitance of each thin film transistor is different; each detection module corresponds to a switch module setting, and the detection module includes multiple detection units for detecting the parameters of the thin film transistor to obtain the detection parameters; the control unit controls one of the multiple thin film transistors in each switch module as the current working switch, and when the control unit determines that the temperature represented by the detection parameter of one is greater than or equal to the preset threshold, the control unit enables another one of the multiple thin film transistors in the switch module where the one is located as the current working switch, wherein the gate-drain parasitic capacitance of the other one is less than the gate-drain parasitic capacitance of the one.

Description

Technical Field

[0001] The present application relates to the field of display panels, and in particular to a level converter chip and a display panel. Background Art

[0002] In the field of display panels, whether it is a liquid crystal display panel, an organic light emitting diode display panel, or a mini light emitting diode display panel, thin film transistors are used to control the on and off of signals in the panel. These display panels include a level converter chip, which is used to generate a control signal to control the driving thin film transistors of the driving array of the display panel. However, in the related art, the temperature of the level converter chip is relatively high, which has an adverse effect on the performance of the level converter chip. Summary of the invention

[0003] In a first aspect, an embodiment of the present application provides a level converter chip, wherein the level converter chip comprises:

[0004] A plurality of switch modules, for receiving an original signal and boosting the original signal to obtain a first control signal; the switch module comprises a plurality of thin film transistors, each thin film transistor comprises a drain, a source and a gate, the plurality of thin film transistors in the same switch module: the drains are electrically connected, the sources are electrically connected, and the gate-drain parasitic capacitance of each thin film transistor is different;

[0005] A plurality of detection modules, each detection module corresponds to a switch module, and different detection modules correspond to different switch modules, the detection module includes a plurality of detection units, the detection unit corresponds to a thin film transistor, and is used to detect a parameter of the thin film transistor to obtain a detection parameter; and

[0006] A control unit controls one of the plurality of thin film transistors in each switch module to be a currently working switch. When the control unit determines that the temperature represented by the detection parameter of the one is greater than or equal to a preset threshold, the control unit controls the one to no longer be the currently working switch, and enables another one of the plurality of thin film transistors in the switch module where the one is located to be the currently working switch, wherein the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one.

[0007] In a second aspect, an embodiment of the present application provides a display panel, the display panel comprising:

[0008] The level converter chip as described in the first aspect;

[0009] The array substrate comprises a plurality of driving thin film transistors, wherein the gates of the driving thin film transistors are used to receive the first control signal and control the corresponding driving thin film transistors to be turned on or off under the control of the first control signal.

[0010] In summary, each switch module in the level converter chip provided in the embodiment of the present application includes a plurality of thin film transistors, and the gate-drain parasitic capacitance of each thin film transistor in the same switch module is different. When the control unit determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold, the control unit controls the one to no longer be the current working switch, but enables another of the plurality of thin film transistors in the switch module where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other when working is smaller, and the heat generated when working is also smaller, so that the level converter chip has better performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the implementation will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 A schematic diagram of a display panel provided in one embodiment of the present application;

[0013] Figure 2 A schematic diagram of a level converter chip provided in one embodiment of the present application;

[0014] Figure 3 A schematic diagram of a detection unit provided in one embodiment of the present application;

[0015] Figure 4 A schematic diagram of a detection unit provided in another embodiment of the present application;

[0016] Figure 5 An equivalent schematic diagram of a thin film transistor in a level converter chip provided in one embodiment;

[0017] Figure 6 for Figure 5 The schematic diagram of various voltage and current curves of the thin film transistor during the conduction process shown;

[0018] Figure 7 A schematic diagram of a computing unit provided in one embodiment of the present application;

[0019] Figure 8An implementation method provided Figure 2 A schematic diagram of a specific circuit structure of a level converter chip shown in ;

[0020] Fig. 9 for Figure 8 Equivalent schematic diagram of thin film transistors working in each switch module;

[0021] Fig.10 for Fig. 9 The control timing diagram of multiple switch modules in the level converter chip shown in FIG.

[0022] Description of main component numbers:

[0023] Display panel 1, level converter chip 10, array substrate 30;

[0024] A switch module 110, a first switch module 111, a second switch module 112, a third switch module 113, a fourth switch module 114, a fifth switch module 115, a sixth switch module 116, a seventh switch module 117, and an eighth switch module 118;

[0025] Thin film transistor Q, Q 11 , Q 12 , Q 13 , Q 21 , Q 22 , Q 23 , Q 31 , Q 32 , Q 33 , Q 41 , Q 42 , Q 43 , Q 51 , Q 52 , Q 53 , Q 61 , Q 62 , Q 63 , Q 71 , Q 72 , Q 73 , Q 81 , Q 82 , Q 83 ;

[0026] Gate g, g0; Source d, d0; Drain s, s0;

[0027] Gate-drain parasitic capacitance Cgd, gate-source parasitic capacitance Cgs, drain-source parasitic capacitance Cgd;

[0028] Gate-source voltage Vg, power signal VDD, gate-on voltage VGH, gate-off voltage VGL;

[0029] Detection module 130, detection unit 131, temperature detection unit 131a, calculation unit 131b, first resistor R1, second resistor R2, output terminal 1311, crystal oscillator 1312, counter 1313;

[0030] The thin film transistor 310 is driven. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0033] Reference to "embodiment" or "implementation" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiment or implementation may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0034] An embodiment of the present application provides a level converter chip (LS IC) 10 and a display panel 1. Next, the level converter chip 10 and the display panel 1 provided in the embodiment of the present application are described in detail.

[0035] The display panel 1 may be, but is not limited to, a liquid crystal display panel (LCD), an organic light-emitting diode display panel (OLED), or a mini organic light-emitting diode display panel (mini OLED).

[0036] See also Figure 1 , Figure 1 A schematic diagram of a display panel provided in one embodiment of the present application. The display panel 1 includes a level converter chip 10 and an array substrate 30. The level converter chip 10 is used to receive an original signal and boost the original signal to obtain a first control signal. The array substrate 30 includes a plurality of driving thin film transistors 310. The plurality of driving thin film transistors 310 are electrically connected to the level converter chip 10 and are used to receive the first control signal. The gate of the driving thin film transistor 310 is used to receive the first control signal and control the corresponding driving thin film transistor 310 to be turned on or off under the control of the first control signal.

[0037] Specifically, in the schematic diagram of the present embodiment, the number of the driving thin film transistors 310 illustrated should not be understood as a limitation on the array substrate 30 in the display panel 1 provided in the embodiment of the present application. The driving thin film transistor 310 includes a gate g0, a source s0 and a drain d0. The gate g0 of the driving thin film transistor 310 receives the first control signal, and controls the source s0 and the drain d0 of the corresponding driving thin film transistor 310 to be turned on or off under the control of the first control signal. When the source s0 and the drain d0 of the driving thin film transistor 310 are turned on under the control of the first control signal, the driving thin film transistor 310 is turned on; when the source s0 and the drain d0 of the driving thin film transistor 310 are turned off under the control of the first control signal, the driving thin film transistor 310 is turned off.

[0038] Next, the level converter chip provided in the embodiments of the present application will be described in detail.

[0039] See also Figure 2 , Figure 2A schematic diagram of a level converter chip provided in one embodiment of the present application. The level converter chip 10 includes a plurality of switch modules 110, a plurality of detection modules 130 and a control unit 150. The plurality of switch modules 110 are used to receive original signals and boost the original signals to obtain a first control signal. The switch module 110 includes a plurality of thin film transistors Q. Each thin film transistor Q includes a drain, a source and a gate. The plurality of thin film transistors Q of the same switch module 110: the drain is electrically connected, and the source is electrically connected, and the gate-drain parasitic capacitance of each thin film transistor Q is different. Each detection module 130 in the plurality of detection modules 130 corresponds to a switch module 110, and different detection modules 130 correspond to different switch modules 110, and the detection module 130 includes a plurality of detection units 131. The detection unit 131 corresponds to a thin film transistor Q and is used to detect the parameters of the thin film transistor Q to obtain the detection parameters. The control unit 150 controls one of the multiple thin film transistors Q in each switch module 110 to be the current working switch. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to a preset threshold, the control unit 150 controls the one to no longer be the current working switch, and enables another one of the multiple thin film transistors Q in the switch module 110 where the one is located to be the current working switch, wherein the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one.

[0040] In the present embodiment, the number of switch modules 110 included in the level converter chip 10 in the schematic diagram should not be understood as a limitation on the level converter chip 10 provided in the embodiment of the present application.

[0041] The multiple switch modules 110 in the level converter chip 10 are used to receive the original signal and boost the original signal to obtain the first control signal; in other words, the multiple switch modules 110 in the level converter chip 10 are boost modules. The voltage value of the first control signal is greater than the voltage value of the original signal.

[0042] In this embodiment, the switch module 110 includes three thin film transistors Q as an example. It can be understood that the number of thin film transistors Q included in the switch module 110 can also be 2, or 4, or more than 4. The "plurality" in the plurality of thin film transistors Q included in the switch module 110 is greater than or equal to 2. Each thin film transistor Q includes a gate s, a source s, and a drain d.

[0043] It is understandable that in this embodiment, the number of thin film transistors Q included in each switch module 110 is the same as an example for illustration. It is understandable that in other embodiments, the number of thin film transistors Q included in each switch module 110 may also be different.

[0044] For the multiple thin film transistors Q in the same switch module 110, the drains d of the multiple thin film transistors Q in the same switch module 110 are electrically connected, and the sources of the multiple thin film transistors Q in the same switch module 110 are electrically connected. There is a parasitic capacitance between the gate g and the drain d of the thin film transistor Q, which is named as the gate-drain parasitic capacitance. The gate-drain parasitic capacitance of the multiple thin film transistors Q in the same switch module 110 is different. Therefore, the power consumption of the multiple thin film transistors Q in the same switch module 110 is different, which leads to different heat generated by different thin film transistors Q in the same switch module 110 when working. Generally speaking, when the gate-drain parasitic capacitance of the thin film transistor Q is larger, the power consumption is greater and the heat generated during operation is also greater; when the gate-drain parasitic capacitance of the thin film transistor Q is smaller, the power consumption is smaller and the heat generated during operation is also smaller. The specific types of the detection parameters will be described in detail later. When the level converter chip 10 is working, when the temperature of the level converter chip 10 is high and exceeds a certain temperature, the performance of the level converter chip 10 will be adversely affected.

[0045] The level converter chip 10 provided in the embodiment of the present application indicates that the temperature of the level converter chip 10 exceeds the standard when the control unit 150 determines that the temperature represented by the detection parameter of one of the currently working switch modules 110 is greater than or equal to a preset threshold. If the level converter chip 10 continues to work, the performance of the level converter chip 10 is poor.

[0046] When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold, it indicates that the control unit 150 controls the one to no longer be the current working switch, but enables another one of the plurality of thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0047] As the size of the display panel 1 becomes larger, the resolution becomes higher, and the refresh rate continues to rise, the frequency of the clock signal (CLK) of the level converter chip 10 also becomes higher. The temperature of the level converter chip 10 itself also continues to rise. The upper limit of the internal temperature of the level converter chip 10 is determined by the PN junction. The current maximum value of the PN junction temperature is usually 150°C. The temperature of the PN junction is attenuated when it is transferred to the surface of the level converter chip 10. Generally speaking, it satisfies: T c =T j -P*θ JC Among them, T c is the surface temperature of the level converter chip 10; T j is the temperature of the PN junction of the level converter chip 10, which is usually 150°C; P is the power dissipation of the level converter chip 10; θ JC is the thermal resistance coefficient of the level converter chip 10. Generally speaking, in order to reduce the surface temperature of the level converter chip 10, it is necessary to reduce the power dissipation of the level converter chip 10, or to reduce the thermal resistance coefficient θ JC , and the thermal resistance coefficient θ JC It is almost unchanged when the packaging conditions of the level converter chip 10 are constant. In addition, in the related art, the heat dissipation of the level converter chip 10 is increased by setting the number of circuit board layers. However, this method will increase the cost of the level converter chip 10.

[0048] In summary, each switch module 110 in the level converter chip 10 provided in the embodiment of the present application includes a plurality of thin film transistors Q, and the gate-drain parasitic capacitance of each thin film transistor Q in the same switch module 110 is different. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the plurality of thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the other one dissipates less power when working, and generates less heat when working, so that the level converter chip 10 has better performance.

[0049] Next, the specific implementation of the detection unit 131 in the level converter chip 10 provided in the embodiment of the present application is introduced.

[0050] See also Figure 3 , Figure 3Schematic diagram of a detection unit provided in one embodiment of the present application. The detection unit 131 can be applied to the aforementioned level converter chip 10. The detection unit 131 includes a temperature detection unit 131a. The temperature detection unit 131a is set at the PN junction of the thin film transistor Q. The temperature detection unit 131a includes a first resistor R1 and a second resistor R2. The first resistor R1 is a thermistor, and one end of the first resistor R1 is grounded. The second resistor R2 is a non-thermistor, and one end of the second resistor R2 is electrically connected to the other end of the first resistor R1 and serves as the output end 1311 of the temperature detection unit 131a, and the other end of the second resistor R2 is used to receive the power signal VDD. The preset threshold includes a preset voltage value. When the control unit 150 determines that the output voltage value of the output end is less than or equal to the preset voltage value, the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold.

[0051] The temperature detection unit 131 a is disposed corresponding to the PN junction of the thin film transistor Q, so that the temperature of the level converter chip 10 can be detected more accurately.

[0052] The first resistor R1 is a thermistor, and therefore, the resistance value of the first resistor R1 will change with the change of temperature. The first resistor R1 is connected in series with the second resistor R2, and therefore, when the power signal VDD (marked as VDD in the figure) is loaded to the other end of the second resistor R2, the first resistor R1 and the second resistor R2 will divide the voltage. When the resistance value of the first resistor R1 is different, since the voltage outputted by the output end is the voltage value of the first resistor R1, the voltage outputted by the output end of the detection unit 131 will change. Therefore, it can be determined whether the temperature represented by the detection parameter is less than or equal to the preset threshold value according to the voltage value outputted by the output end of the detection unit 131.

[0053] The detection unit 131 of the level converter chip 10 provided in the embodiment of the present application includes a temperature detection unit 131a, and the temperature detection unit 131a is set at the PN junction of the thin film transistor Q, so the temperature detection unit 131a can measure the temperature of the level converter chip 10 more accurately. In addition, since the first resistor R1 is a thermistor and the second resistor R2 is a non-thermistor, the other end of the second resistor R2 is used to receive the power signal VDD. The resistance value of the first resistor R1 will change with the change of temperature. When the power signal VDD is constant, the voltage value on the first resistor R1 will change with the change of the temperature of the level converter chip 10, and then, the voltage value of the output end will change with the change of the temperature of the level converter chip 10. Therefore, the control unit 150 can determine whether the parameter of one is less than or equal to the preset threshold value by the size of the output voltage value of the output end, and it is more accurate. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the plurality of thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0054] Furthermore, the first resistor R1 is a negative temperature coefficient thermistor, and the higher the temperature of the level converter chip 10 is, the smaller the output voltage value is.

[0055] The first resistor R1 is a negative temperature coefficient thermistor, and therefore, the first resistor R1 may decrease as the temperature increases.

[0056] The first resistor R1 is a negative temperature coefficient thermistor with high sensitivity. Therefore, it can improve the accuracy of determining whether the parameter of one of the two is less than or equal to the preset threshold value according to the output voltage value.

[0057] In one embodiment, the temperature represented by the preset voltage value is 80°. When the control unit 150 determines that the detection parameter of one is less than or equal to the preset threshold value according to the output voltage, the control unit 150 determines that the temperature of the level converter chip 10 is greater than or equal to 80°.

[0058] In this embodiment, the temperature represented by the preset voltage value is selected as 80°C, and it is determined whether the temperature of the level converter chip is greater than or equal to 80°C according to the output voltage value. When the temperature of the level converter chip is greater than or equal to 80°C, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the multiple thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0059] Next, the detection unit 131 provided in another embodiment of the present application is described.

[0060] Please also read Figure 4 , Figure 5 and Figure 6 , Figure 4 A schematic diagram of a detection unit provided in another embodiment of the present application; Figure 5 An equivalent schematic diagram of a thin film transistor in a level converter chip provided in one embodiment; Figure 6 for Figure 5 The schematic diagram of each voltage and current curve of the thin film transistor during the conduction process shown. The detection unit 131 includes a calculation unit 131b. The calculation unit 131b is used to calculate the rise time from a low level to a high level and the fall time from a high level to a low level of the one turned on among the multiple thin film transistors Q in each switch module 110. The detection parameters include the rise time and the fall time. The preset threshold includes a preset duration. When the control unit 150 determines that one of the rise time and the fall time is greater than or equal to the preset duration, the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold.

[0061] In this embodiment, the calculation unit 131b is used to calculate the rise time from a low level to a high level and the fall time from a high level to a low level of the one of the multiple thin film transistors Q in each switching module 110 that is turned on, and when one of the rise time and the fall time is greater than or equal to the preset duration, the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to a preset threshold.

[0062] Specifically, when the rise time from the low level to the high level of the thin film transistor Q is greater than or equal to the preset time length, the rise time of the thin film transistor Q is too long; when the fall time from the high level to the low level of the thin film transistor Q is greater than or equal to the preset time length, the fall time of the thin film transistor Q is too long.

[0063] When the rise time of the thin film transistor Q is too long, or the fall time of the thin film transistor Q is too long, the power consumption (also called dissipated power consumption) of the thin film transistor Q is large, and the heat of the level converter chip 10 is large.

[0064] In the level converter chip 10 provided in the embodiment of the present application, the detection unit 131 includes a calculation unit 131b, and the calculation unit 131b is used to calculate the rise time from low level to high level and the fall time from high level to low level of the one of the multiple thin film transistors Q in each switch module 110 that is turned on. When the control unit 150 determines that one of the rise time and the fall time is greater than or equal to the preset time, the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the multiple thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0065] See also Figure 5 , the thin film transistor Q includes a gate g, a source s and a drain d. In addition, the thin film transistor Q also includes a gate-drain parasitic capacitor Cgd, a gate-source parasitic capacitor Cgs and a drain-source parasitic capacitor Cgd. The gate-drain parasitic capacitor Cgd is a parasitic capacitor between the gate g and the drain d, the gate-source parasitic capacitor Cgs is a parasitic capacitor between the gate g and the source s, and the drain-source parasitic capacitor Cgd is a parasitic capacitor between the drain d and the source s.

[0066] The thin film transistor Q itself is a voltage-controlled element, but in actual situations, the process of the thin film transistor Q from being turned off to being turned on also requires current (i.e., charge). The reason is that there is a parasitic capacitance between any two of the gate g, source s, and drain d of the thin film transistor Q. That is, there is a gate-drain parasitic capacitance Cgd, a gate-source parasitic capacitance Cgs, and a drain-source parasitic capacitance Cgd.

[0067] The condition for the thin film transistor Q to be turned on is that the gate-source voltage Vgs of the gate g and the source s is greater than or equal to the threshold voltage Vgs(th), which is specifically achieved by charging the gate-source parasitic capacitance Cgs through the gate g current (also called gate g charge) received by the gate g. When the thin film transistor Q is fully turned on, no current needs to be provided. That is, the thin film transistor Q is a voltage-controlled element. The voltage and current curves of the thin film transistor Q during the conduction process are as follows: Figure 6 As shown. Figure 6 In the figure, the horizontal axis is time and the vertical axis is voltage. For the gate-source voltage Vgs of the thin film transistor Q, the gate-source voltage Vgs curve has a famous Miller platform. That is, the gate-source voltage Vgs of the thin film transistor Q remains unchanged for a certain period of time (the period of time t2 to t3 in the figure). Shortening this Miller platform can shorten the turn-off time and turn-on time of the thin film transistor Q.

[0068] like Figure 6 As shown, the gate-source voltage Vgs of the thin film transistor Q increases at the beginning (i.e., in the time period t0-t2), as the gate g charge increases. Entering the Miller platform time (t2-t3 time period), the gate g charge is used to charge the gate-drain parasitic capacitance Cgd, and the polarity of the gate g charge used to charge the gate-drain parasitic capacitance Cgd is opposite to the polarity of charging the drain d, that is, positive at the bottom and negative at the top. Therefore, it can also be regarded as the reverse discharge of the gate-drain parasitic capacitance Cgd. Eventually, the gate-drain d voltage Vgd changes from negative to positive, ending the Miller platform and entering the variable resistance area (corresponding to the t3-t4 time period). During the Miller platform time (t2-t3 time period), the drain-source s voltage Vds of the thin film transistor Q begins to decrease, and the duration of the Miller platform is the time when the drain-source s voltage Vds drops from the maximum value to the minimum value, that is, the turn-on time, or turn-off time of the thin film transistor Q. It can be seen that the on time and off time of the thin film transistor Q are proportional to the gate-drain parasitic capacitance Cgd. Therefore, the gate-drain parasitic capacitance Cgd can be adjusted by the rise time or fall time of the thin film transistor Q.

[0069] In one embodiment, the calculation unit 131b is used to calculate the time from 10% of the voltage value of the high level to 90% of the voltage value of the high level for the one turned on among the plurality of thin film transistors Q in each switch module 110 as the rising time. The calculation unit 131b is used to calculate the time from 90% of the voltage value of the high level to 10% of the voltage value of the high level for the one turned on among the plurality of thin film transistors Q in each switch module 110 as the falling time.

[0070] In this embodiment, the time from 10% of the voltage value of the high level to 90% of the voltage value of the high level of the thin film transistor Q is taken as the rise time, and the rise time can be calculated more accurately. In addition, the time from 90% of the voltage value of the high level to 10% of the high level is taken as the fall time, and the fall time can be calculated more accurately. Thus, the accuracy of the control unit 150 in judging that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold value according to the rise time and the fall time is improved. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold value, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the multiple thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0071] For further information, see Figure 7 , Figure 7 A schematic diagram of a calculation unit provided in one embodiment of the present application. The calculation unit 131b includes a crystal oscillator 1312 and a counter 1313. The crystal oscillator 1312 is used to generate a reference clock signal. The counter 1313 is electrically connected to the crystal oscillator 1312, and the counter 1313 is used to calculate the number of the reference clock signals between 10% of the voltage value of the high level and 90% of the voltage value of the high level of the one turned on among the multiple thin film transistors Q in each switch module 110 to obtain a first number, wherein the product of the first number and the reference time of the reference clock signal is the rise time. The counter 1313 is also used to calculate the number of the reference clock signals between 90% of the voltage value of the high level and 10% of the voltage value of the high level of the one turned on among the multiple thin film transistors Q in each switch module 110 to obtain a second number, wherein the product of the second number and the reference time of the reference clock signal is the fall time.

[0072] The reference clock signal may be a pulse signal. The duration of the reference clock signal is a reference time, and the reference time is a known constant. When the calculator is used to calculate the rise time of the thin film transistor, the calculator calculates the number of the reference clock signal between 10% of the voltage value of the high level and 90% of the voltage value of the high level of the thin film transistor Q to obtain a first number. The product of the first number and the reference time is the rise time.

[0073] When calculating the rise time, the counter 1313 is triggered at 10% of the high voltage and marked as the first trigger point; and is triggered at 90% of the high voltage and marked as the second trigger point. The counter 1313 starts counting at the first trigger point and stops counting at the second trigger point. The counter 1313 starts counting at the first trigger point and stops counting at the second trigger point, and the number remembered is the number of the reference clock signal, marked as the first number. Since the duration of the reference clock signal is the reference time, and the reference time is a known constant, the size of the first number can standardize the length of the rise time. The larger the first number, the longer the rise time; correspondingly, the smaller the first number, the shorter the rise time.

[0074] Accordingly, when calculating the fall time, the counter 1313 is triggered at 90% of the high voltage and marked as the third trigger point; and is triggered at 10% of the high voltage and marked as the fourth trigger point. The counter 1313 starts counting at the third trigger point and stops counting at the fourth trigger point. The counter 1313 starts counting at the third trigger point and stops counting at the fourth trigger point. The number remembered is the number of the reference clock signal, marked as the second number. Since the duration of the reference clock signal is the reference time, and the reference time is a known constant, the size of the second number can standardize the length of the fall time. The larger the second number, the longer the fall time; correspondingly, the smaller the second number, the shorter the fall time.

[0075] The thin film transistor Q changes from 90% of the voltage value of the high level to 10% of the voltage value of the high level by the reference clock signal to obtain a second number. The product of the second number and the reference time of the reference clock signal is the falling time.

[0076] It can be seen that the calculation unit 131b provided in the embodiment of the present application can calculate the rise time and the fall time relatively easily, quickly and accurately. Therefore, the control unit 150 can judge the accuracy when the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold value according to the rise time and the fall time. When the control unit 150 determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold value, the control unit 150 controls the one to no longer be the current working switch, but enables another one of the multiple thin film transistors Q in the switch module 110 where the one is located as the current working switch. Since the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one, the power consumption of the other one when working is smaller, and the heat generated when working is also smaller, so that the level converter chip 10 has better performance.

[0077] See also Figure 2 , Figure 8 , Figure 8 An implementation method provided Figure 2 The specific circuit structure diagram of the level converter chip shown in . The multiple switch modules 110 include a first switch module 111, a second switch module 112, a third switch module 113, a fourth switch module 114, a fifth switch module 115, a sixth switch module 116, a seventh switch module 117 and an eighth switch module 118. Take the first switch module 111, the second switch module 112, the third switch module 113, the fourth switch module 114, the fifth switch module 115, the sixth switch module 116, the seventh switch module 117 and the eighth switch module 118 as an example to illustrate. Among them, the three thin film transistors of the first switch module 111 are respectively labeled Q 11 , Q 12 and Q 13 The three thin film transistors of the second switch module 112 are respectively labeled Q 21 , Q 22 and Q 23 The three thin film transistors of the third switch module 113 are respectively labeled Q 31 , Q 32 and Q 33 The three thin film transistors of the fourth switch module 114 are respectively labeled Q 41 , Q 42 and Q 43 The three thin film transistors of the fifth switch module 115 are respectively labeled Q 51 , Q 52 and Q 53 The three thin film transistors of the sixth switch module 116 are respectively labeled Q 61 , Q 62 and Q63 The three thin film transistors of the seventh switch module 117 are respectively labeled Q 71 , Q 72 and Q 73 The three thin film transistors of the eighth switch module 118 are respectively labeled Q 81 , Q 82 and Q 83 The thin film transistor in each switch module includes a gate electrode g, a drain electrode d and a source electrode s.

[0078] In the Nth switch module, the gate of the thin film transistor working in the Nth switch module is the gate of the Nth switch module, the source of the thin film transistor working in the Nth switch module is the source of the Nth switch module; the drain of the thin film transistor working in the Nth switch module is the drain of the Nth switch module. Wherein, N can be equal to any one of one, two, three, four, five, six, seven, and eight. For example, in the first switch module, the gate of the thin film transistor working in the first switch module is the gate of the first switch module, the source of the thin film transistor working in the first switch module is the source of the first switch module; the drain of the thin film transistor working in the first switch module is the drain of the first switch module.

[0079] The first switch module 111, the second switch module 112, the fifth switch module 115 and the sixth switch module 116 are PMOS modules. The third switch module 113, the fourth switch module 114, the seventh switch module 117 and the eighth switch module 118 are NMOS modules. The gate of the first switch module 111 is used to receive the original signal A, and the source of the first switch module 111 is used to receive the power supply signal VDD. The gate of the second switch module 112 is used for the non-signal of the original signal (i.e., A non (in the figure, the upper end of A is marked with a horizontal line)), and the source of the second switch module 112 is used to receive the power supply signal VDD. The gate of the third switch module 113 is electrically connected to the drain of the second switch module 112, the drain of the third switch module 113 is electrically connected to the drain of the first switch module 111, and the source of the third switch module 113 is used to receive the gate-off voltage VGL signal. The gate of the fourth switch module 114 is electrically connected to the drain of the first switch module 111, the drain of the fourth switch module 114 is electrically connected to the drain of the second switch module 112, and the source of the fourth switch module 114 is used to receive the gate-off voltage VGL signal. The gate of the fifth switch module 115 is the output end (marked as OUT) of the level converter chip 10, and the source of the fifth switch module 115 is used to receive the gate-on voltage VGH. The source of the sixth switch module 116 is used to receive the gate-on voltage VGH. The gate of the seventh switch module 117 is electrically connected to the gate of the third switch module 113, the drain of the seventh switch module 117 is electrically connected to the drain of the fifth switch module 115, and the source of the seventh switch module 117 is used to receive the gate-off voltage VGL signal. The gate of the eighth switch module 118 is electrically connected to the drain of the first switch module, the drain of the eighth switch module 118 is electrically connected to the drain of the sixth switch module 116 , and the source of the eighth switch module 118 is used to receive the gate-off voltage VGL signal.

[0080] The first switch module 111, the second switch module 112, the fifth switch module 115 and the sixth switch module 116 are PMOS modules, that is, all thin film transistors Q in the first switch module 111, the second switch module 112, the fifth switch module 115 and the sixth switch module 116 are PMOS transistors. The third switch module 113, the fourth switch module 114, the seventh switch module 117 and the eighth switch module 118 are NMOS modules, that is, all thin film transistors Q in the third switch module 113, the fourth switch module 114, the seventh switch module 117 and the eighth switch module 118 are NMOS transistors. The on-state voltage of the PMOS thin film transistor Q is less than zero; the on-state voltage of the NMOS thin film transistor Q is greater than zero.

[0081] The plurality of switch modules 110 of the level converter chip 10 provided in the embodiment of the present application include a first switch module 111, a second switch module 112, a third switch module 113, a fourth switch module 114, a fifth switch module 115, a sixth switch module 116, a seventh switch module 117 and an eighth switch module 118, wherein the first switch module 111, the second switch module 112, the fifth switch module 115 and the sixth switch module 116 are PMOS modules, and the third switch module 114 is a PMOS module. 13. The fourth switch module 114, the seventh switch module 117 and the eighth switch module 118 are NMOS modules, and the plurality of switch modules 110 can boost the received original signal to obtain the first control signal by configuring the connection relationship of the first switch module 111, the second switch module 112, the third switch module 113, the fourth switch module 114, the fifth switch module 115, the sixth switch module 116, the seventh switch module 117 and the eighth switch module 118. The number of switch modules 110 used in the level converter chip 10 provided in the embodiment of the present application is small, the volume is small, and the cost is low.

[0082] Further, in this embodiment, the source of the second switch module 112 is electrically connected to the source of the first switch module 111. The source of the fourth switch module 114 is electrically connected to the source of the third switch module 113. The source of the sixth switch module 116 is electrically connected to the source of the fifth switch module 115. The source of the seventh switch module 117 is electrically connected to the source of the third switch module 113. The source of the eighth switch module 118 is electrically connected to the source of the third switch module 113.

[0083] In this embodiment, the corresponding electrodes of different switch modules 110 that receive the same signal are electrically connected, so that the corresponding electrodes of different switch modules 110 can receive the same signal without having to connect too many connection points from the outside world. As a result, the number of connection points connected to the outside world in the multiple switch modules 110 is relatively small, and the structure is relatively simple.

[0084] For example, the source of the first switch module 111 receives the power signal VDD, and the source of the second switch module 112 is electrically connected to the source of the first switch module 111, so the source of the second switch module 112 can receive the power signal VDD. It can be understood that in other embodiments, the source of the second switch module 112 may not be electrically connected to the source of the first switch module 111, as long as the source of the first switch module 111 receives the power signal VDD and the source of the second switch module 112 can receive the power signal VDD.

[0085] See also Fig. 9 and Fig.10 , Fig. 9 for Figure 8 Equivalent schematic diagram of thin film transistors working in each switch module; Fig.10 for Fig. 9 The control timing diagram of multiple switch modules in the level converter chip shown in . The control unit 150 has a second control signal when enabling another one of the multiple thin film transistors Q as the current switch. The control time of the second control signal of the control unit 150 includes a first control time and a second control time that are consecutive in sequence. The second control signal is used for: During the first control time: the gate of the first switch module 111 (i.e., A in the figure) is used to receive a high level signal, the first switch module 111, the fourth switch module 114, the fifth switch module 115 and the eighth switch module 118 are all closed, and the second switch module 112, the third switch module 113, the sixth switch module 116 and the seventh switch module 117 are all closed.

[0086] The second control signal is used for: within the second control time, the gate of the first switch module 111 (i.e., point A in the figure) is used to receive a low-level signal, the first switch module 111, the fourth switch module 114, the fifth switch module 115 and the eighth switch module 118 are all turned on; the sixth switch module 116 and the seventh switch module 117 are both turned off, wherein the second control time is after the first control time.

[0087] The signal received by the gate of the thin film transistor Q in the first switch module 111 is marked as A; the signal received by the gate of the thin film transistor Q in the second switch module 112 is marked as A negative (marked by a short horizontal line above A in the figure); the signal received by the gate of the thin film transistor Q in the third switch module 113 is marked as B; the signal received by the gate of the thin film transistor Q in the fourth switch module 114 is marked as B negative (marked by a short horizontal line above B in the figure); the gate of the thin film transistor Q in the fifth switch module 115 is marked as OUT; the signal received by the gate of the thin film transistor Q in the sixth switch module 116 is OUT negative (marked by a short horizontal line above OUT in the figure); the gate of the thin film transistor Q in the seventh switch module 117 is electrically connected to the gate of the thin film transistor Q in the third switch module 113, so the gate of the thin film transistor Q in the seventh switch module 117 is also B; the signal received by the gate of the thin film transistor Q in the eighth switch module 118 is marked as B negative (marked by a short horizontal line above B in the figure). Among them, the source of the thin film transistor Q in the first switch module 111 and the source of the thin film transistor Q in the second switch module 112 respectively receive the power signal VDD; the source of the thin film transistor Q in the third optical switch module 110, the source of the thin film transistor Q in the fourth switch module 114, the source of the thin film transistor Q in the seventh switch module 117, and the source of the thin film transistor Q in the eighth switch module 118 respectively receive the gate-off voltage VGL signal; the source of the thin film transistor Q in the fifth switch module 115 and the source of the thin film transistor Q in the sixth switch module 116 respectively receive the gate-on voltage VGH.

[0088] Among them, in the first control time: when A is a high level, A is not a low level, the thin film transistor Q of the second switch module 112 is turned on (also called turned on), B is the power signal VDD, the thin film transistor Q of the third switch module 113 is turned on, B is not the gate-off voltage VGL, the thin film transistor Q in the fourth switch module 114 and the thin film transistor Q in the eighth switch module 118 are both turned off, the thin film transistor Q in the seventh switch module 117 is turned on, out is not the gate-off voltage VGL, and the thin film transistor Q in the sixth switch module 116, OUT is the gate-on voltage VGH.

[0089] In the second control time: when A is at a low level, the thin film transistor Q of the first switch module 111 is turned on (also called turned on), B is not the power signal VDD, the thin film transistor Q in the fourth switch module 114 is turned on, B is the gate-off voltage VGL, the thin film transistor Q in the eighth switch module 118 is turned on, the thin film transistor Q in the seventh switch module 117 is turned off, OUT is the gate-off voltage VGL, the thin film transistor Q in the fifth switch module 115 is turned on, OUT is not the gate-on voltage VGH, and the thin film transistor Q in the sixth switch module 116 is turned off; in this way, A is amplified to the waveform required by OUT. That is, the original received signal (A) is boosted to the first control signal (OUT).

[0090] Among them, Fig.10 In the figure, the first waveform to the second waveform is called the first step (First Step), and the second waveform to the third waveform is called the second step (Second Step). After the first and second steps, the original receiving signal (A) is boosted to the first control signal (OUT).

[0091] Generally speaking, the power supply signal VDD is a DC voltage with a voltage value of 3.3V; the gate-on voltage VGH is 30V, or about 30V; and the gate-off voltage VGL signal VGL is -9V, or about -9V.

[0092] The essence of the level converter chip 10 is to convert a low-level original received signal A (i.e., a low-level clock signal, which can also be marked as CLK) into a high-level clock signal, and the converted high-level clock signal is the first control signal. The first control signal output by the level converter chip 10 is used to control the conduction or shutoff of the driving thin film transistor 310 in the array substrate 30.

[0093] The conversion process of the level converter chip 10 converting the low-level original received signal into the high-level first control signal is the cause of the emission of the level converter chip 10. That is, the turning on or off of each thin film transistor Q in each switch module 110 (such as the first switch module 111 to the eighth switch module 118 described above) in the level converter chip 10 causes the level converter chip 10 to generate heat. The frequent turning on or off of each thin film transistor Q in each switch module 110 (such as the first switch module 111 to the eighth switch module 118 described above) in the level converter chip 10 will cause the power consumption of the level converter chip 10 to increase. Generally speaking, the dissipated power consumption of each thin film transistor Q in each switch module 110 (such as the first switch module 111 to the eighth switch module 118 described above) in the level converter chip 10 is mainly reflected in the conduction loss and the turn-off loss. Generally speaking, the dissipated power consumption Psw of the thin film transistor Q satisfies formula (1).

[0094] Psw=0.5× Vin × Io × (tr + tf) × f SW (1).

[0095] Among them, the coefficient of 0.5 is because the conduction curve of the thin film transistor Q is regarded as approximately linear, and when converted into area power, the coefficient is 0.5; Vin refers to the input voltage of the thin film transistor Q, and Io refers to the output current of the thin film transistor Q; tr refers to the rise time of the thin film transistor Q, that is, the time for the drain-source voltage of the thin film transistor Q to rise from 10% to 90%; tf refers to the fall time of the thin film transistor Q, that is, the time for the drain-source voltage of the thin film transistor Q to fall from 90% to 10%; fsw refers to the switching frequency of the thin film transistor Q.

[0096] It can be seen from this that a method needs to be found to reduce the power dissipation Psw of the thin film transistor Q, so as to solve the heating problem of the level converter chip 10 .

[0097] The level converter chip 10 provided in one embodiment of the present application starts from the rise time and fall time (tr+tf) of the thin film transistor Q, reduces the on time and off time of each thin film transistor Q in the level converter chip 10, and thus reduces the dissipated power consumption of the thin film transistor Q.

[0098] In a level converter chip 10 provided in one embodiment of the present application, a switch module 110 of the level converter chip 10 includes a plurality of thin film transistors Q, and the gate-drain parasitic capacitances of the plurality of thin film transistors Q are different in size. For example, when the switch module 110 includes three thin film transistors Q, the gate-drain parasitic capacitances of the three thin film transistors Q are large, medium, and small, respectively. When it is detected that the temperature is too high or the rise time and fall time (tr+tf) of the thin film transistor Q are too long, the control unit 150 switches the working switch of the corresponding switch module 110 to the thin film transistor Q with a smaller gate-drain parasitic capacitance, thereby reducing the dissipated power consumption of the thin film transistor Q.

[0099] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in the field can change, modify, replace and modify the above embodiments within the scope of the present application, and these improvements and modifications are also regarded as the scope of protection of the present application.

Claims

1. A level converter chip, characterized in that: The level converter chip comprises: A plurality of switch modules, for receiving an original signal and boosting the original signal to obtain a first control signal; the switch module comprises a plurality of thin film transistors, each thin film transistor comprises a drain, a source and a gate, the plurality of thin film transistors in the same switch module: the drains are electrically connected, the sources are electrically connected, and the gate-drain parasitic capacitance of each thin film transistor is different; A plurality of detection modules, each detection module corresponds to a switch module, and different detection modules correspond to different switch modules, the detection module includes a plurality of detection units, the detection unit corresponds to a thin film transistor, and is used to detect a parameter of the thin film transistor to obtain a detection parameter; and a control unit, controlling one of the plurality of thin film transistors in each switch module to be a current working switch, and when the control unit determines that the temperature represented by the detection parameter of the one is greater than or equal to a preset threshold, the control unit controls the one to no longer be the current working switch, and enables another one of the plurality of thin film transistors in the switch module where the one is located to be the current working switch, wherein the gate-drain parasitic capacitance of the other one is smaller than the gate-drain parasitic capacitance of the one; Wherein, the detection unit includes a temperature detection unit, and the temperature detection unit is arranged corresponding to the PN junction of the thin film transistor, and the temperature detection unit includes: A first resistor, wherein the first resistor is a thermistor, and one end of the first resistor is grounded; a second resistor, wherein the second resistor is a non-thermistor, one end of the second resistor is electrically connected to the other end of the first resistor and serves as an output end of the temperature detection unit, and the other end of the second resistor is used to receive a power signal; The preset threshold includes a preset voltage value. When the control unit determines that the output voltage value of the output end is less than or equal to the preset voltage value, the control unit determines that the temperature represented by the detection parameter of one is greater than or equal to the preset threshold.

2. The level converter chip according to claim 1, characterized in that: The first resistor is a negative temperature coefficient thermistor, and the higher the temperature of the level converter chip is, the smaller the output voltage value is.

3. The level converter chip according to claim 1, wherein: The temperature represented by the preset voltage value is 80°. When the control unit determines that the detection parameter of one is less than or equal to the preset threshold value according to the output voltage, the control unit determines that the temperature of the level converter chip is greater than or equal to 80°.

4. The level converter chip according to claim 1, wherein: The detection unit comprises: A calculation unit, the calculation unit is used to calculate the rise time from a low level to a high level and the fall time from a high level to a low level of the one turned on among the plurality of thin film transistors in each switch module; The detection parameters include the rise time and the fall time; The preset threshold includes a preset duration. When the control unit determines that one of the rise time and the fall time is greater than or equal to the preset duration, the control unit determines that the temperature represented by the detection parameter of the one is greater than or equal to the preset threshold.

5. The level converter chip as claimed in claim 4, characterized in that: The calculation unit is used to calculate the time from 10% of the high level voltage value to 90% of the high level voltage value of the turned-on one of the plurality of thin film transistors in each switch module as the rising time; The calculation unit is used to calculate the time from 90% of the voltage value of the high level to 10% of the high level for the turned-on one of the plurality of thin film transistors in each switch module as the fall time.

6. The level converter chip as claimed in claim 5, characterized in that: The computing unit comprises: a crystal oscillator, the crystal oscillator being used to generate a reference clock signal; and a counter, the counter being electrically connected to the crystal oscillator, the counter being used to count the number of the reference clock signals of the one of the plurality of thin film transistors turned on in each switch module from 10% of the voltage value of the high level to 90% of the voltage value of the high level to obtain a first number, wherein the product of the first number and the reference time of the reference clock signal is the rise time; The counter is also used to calculate the number of the reference clock signals of the one of the multiple thin film transistors in each switching module that is turned on from 90% of the voltage value of the high level to 10% of the high level to obtain a second number, wherein the product of the second number and the reference time of the reference clock signal is the fall time.

7. The level converter chip according to claim 1, wherein: The plurality of switch modules include a first switch module, a second switch module, a third switch module, a fourth switch module, a fifth switch module, a sixth switch module, a seventh switch module and an eighth switch module; The first switch module, the second switch module, the fifth switch module and the sixth switch module are PMOS modules, and the third switch module, the fourth switch module, the seventh switch module and the eighth switch module are NMOS modules; The gate of the first switch module is used to receive the original signal, and the source of the first switch module is used to receive a power supply signal; The gate of the second switch module is used for the non-signal of the original signal, and the source of the second switch module is used for receiving the power supply signal; The gate of the third switch module is electrically connected to the drain of the second switch module, the drain of the third switch module is electrically connected to the drain of the first switch module, and the source of the third switch module is used to receive a gate closing voltage signal; The gate of the fourth switch module is electrically connected to the drain of the first switch module, the drain of the fourth switch module is electrically connected to the drain of the second switch module, and the source of the fourth switch module is used to receive a gate closing voltage signal; The gate of the fifth switch module is the output end of the level converter chip, and the source of the fifth switch module is used to receive a gate-on voltage; The source of the sixth switch module is used to receive the gate-on voltage; The gate of the seventh switch module is electrically connected to the gate of the third switch module, the drain of the seventh switch module is electrically connected to the drain of the fifth switch module, and the source of the seventh switch module is used to receive the gate closing voltage signal; The gate of the eighth switch module is electrically connected to the drain of the first switch module, the drain of the eighth switch module is electrically connected to the drain of the sixth switch module, and the source of the eighth switch module is used to receive the gate closing voltage signal.

8. The level converter chip as claimed in claim 7, characterized in that: The control unit has a second control signal when enabling another one of the plurality of thin film transistors as a current working switch, and the second control signal is used to: During the first control time: the gate of the first switch module is used to receive a high level signal, the first switch module, the fourth switch module, the fifth switch module and the eighth switch module are all turned off, and the second switch module, the third switch module, the sixth switch module and the seventh switch module are all turned off; During the second control time, the gate of the first switch module is used to receive a low-level signal, and the first switch module, the fourth switch module, the fifth switch module and the eighth switch module are all turned on; the sixth switch module and the seventh switch module are both turned off, wherein the second control time is after the first control time.

9. A display panel, characterized in that: The display panel comprises: The level converter chip according to any one of claims 1 to 8; An array substrate includes a plurality of driving thin film transistors, wherein the gates of the driving thin film transistors are used to receive the first control signal and control the corresponding driving thin film transistors to be turned on or off under the control of the first control signal.

Images