Current detection circuit and power supply chip, electronic equipment

Abstract

A current detection circuit, a power chip, and an electronic device belong to the technical field of inductor current detection. The fifth field effect tube reduces the current of a first PMOS tube to generate a detection current. The first field effect tube and the second field effect tube are included in the common gate amplifier as a feedforward path of a feedback system, and the third field effect tube is used as a feedback link of a negative feedback loop, so that the first PMOS tube and the fifth field effect tube have similar source-drain voltages, thereby improving the accuracy of current detection; at the same time, if the inductor current is negative, the first PMOS tube will generate a negative voltage drop, that is, the source voltage of the fourth field effect tube will be higher than the voltage of the first power supply, and the fourth field effect tube makes the source voltage of the second field effect tube still lower than the voltage of the first power supply and close to another input voltage of the common gate amplifier, so the fifth field effect tube still works and generates an accurate negative detection current, thereby realizing the simultaneous detection of positive inductor current and negative inductor current.

Description

Technical Field

[0001] The present application belongs to the technical field of inductor current detection, and in particular, relates to a current detection circuit, a power chip, and an electronic device. Background Art

[0002] In a current-mode DC-DC converter, the inductor current needs to be used as a feedback signal control loop to dynamically adjust the duty cycle of the control signal, so this type of converter requires inductor current detection technology. According to the location of the power tube, the inductor current detection technology can be divided into on-chip inductor current detection and off-chip inductor current detection. Traditional on-chip inductor current detection technology is based on detecting tube current. The advantages of this technology are high efficiency and easy integration, but the main problem is that it can only detect positive inductor current.

[0003] For example, a related current detection circuit such as Figure 1 As shown, the circuit in the dotted box corresponding to reference numeral 10 is a current detection circuit, the circuit in the dotted box corresponding to reference numeral 20 is a current mirror, U1 is a comparator, the signal corresponding to reference numeral 90 is a slope compensation current, and the bias currents I1 and I2 provide the same pull-down current for two identical PNP transistors Q1 and Q2. M1 is the power tube of the DC-DC converter. M2 is defined as a reference power tube, so the PMOS tubes M1 and M2 are scaled proportionally, so that the width-to-length ratio of the transistor on the output side of the circuit is much larger than the width-to-length ratio of the transistor on the detection side of the circuit. Therefore, the current on the detection side is not only much smaller than the current on the output side, but also proportional to it.

[0004] The output current is the difference between the current flowing through M1 (with a larger aspect ratio) and the current flowing through another small current source I1. The sense current flowing through the internal sense resistor R is the difference between the current flowing through M2 (with a smaller aspect ratio) and the current flowing through another small current source I2. Therefore, the current flowing through the sense resistor is basically proportional to the current flowing through the load and is much smaller than this current.

[0005] However, this current detection circuit can only detect the positive current flowing through the inductor L but cannot detect its negative current. When the negative current flows through the inductor, the voltage of node D will be higher than the power supply voltage VCC, and Q1 and Q2 cannot adjust the voltage of node A to make it higher than VCC like the voltage of node B. Therefore, the current detection amplifier will be in an open-loop state, and the detection current will no longer be proportional to the negative load current.

[0006] Therefore, the related current detection circuit cannot detect the negative current of the inductor. Summary of the invention

[0007] The purpose of the present application is to provide a current detection circuit, a power chip, and an electronic device, aiming to solve the problem that the related current detection circuit cannot detect the negative current of the inductor.

[0008] The embodiment of the present application provides a current detection circuit connected to a DC-DC converter, wherein the DC-DC converter includes a first PMOS transistor and a first NMOS transistor; the current detection circuit includes a first field effect transistor, a second field effect transistor, a third field effect transistor, a fourth field effect transistor, a fifth field effect transistor, a first current, a second current source, a third current source, and a fourth current source;

[0009] The source of the fourth field effect transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, the drain of the fourth field effect transistor is connected to the source of the second field effect transistor and the positive electrode of the first current source, the source of the fifth field effect transistor and the source of the first PMOS transistor are connected to the first power supply, the drain of the fifth field effect transistor is connected to the source of the first field effect transistor and the source of the third field effect transistor, the gate of the second field effect transistor is connected to the gate of the first field effect transistor, the drain of the first field effect transistor and the positive electrode of the third current source, the drain of the second field effect transistor is connected to the gate of the third field effect transistor and the positive electrode of the second current source, and the drain of the third field effect transistor and the positive electrode of the fourth current source serve together as the output current output terminal of the current detection circuit to output the output current;

[0010] The source of the first NMOS tube, the cathode of the first current source, the cathode of the second current source, the cathode of the third current source and the cathode of the fourth current source are connected to a power ground.

[0011] In one embodiment, it further includes a first switch, a second switch, a sixth field effect transistor and a fifth current source;

[0012] A first end of the first switch is connected to the drain of the fourth field effect transistor and the positive electrode of the first current source, and a second end of the first switch is connected to the source of the second field effect transistor and the second end of the second switch;

[0013] The source of the sixth field effect transistor is connected to the first power supply, the drain of the sixth field effect transistor is connected to the positive electrode of the fifth current source and the first end of the second switch, and the negative electrode of the fifth current source is connected to the power ground.

[0014] In one embodiment, the current I5 of the fifth current source is obtained by the following calculation formula: (I5+I2)R M6 =(I4+I3)R M5

[0015] Where I2 is the current of the second current source, R M6is the equivalent on-resistance of the sixth field effect transistor, I4 is the current of the fourth current source, I3 is the current of the third current source, R M5 is the equivalent on-resistance of the fifth field effect transistor.

[0016] In one embodiment, at the same time, at most one of the first switch SW1 and the second switch SW2 is closed.

[0017] In one of the embodiments, a third switch is further included;

[0018] A first end of the third switch is connected to the drain of the fifth field effect transistor, and a second end of the third switch is connected to the source of the first field effect transistor and the source of the third field effect transistor.

[0019] In one embodiment, the current I4 of the fourth current source I4 is calculated by the following formula: mp R mp +(I1+I2)R M4 =I M5 R M5

[0020] Among them, I M5 is the source-drain current of the fifth field effect transistor M5, R mp is the equivalent on-resistance of the first PMOS tube MP, I1 is the current of the first current source, I2 is the current of the second current source, R M4 is the equivalent on-resistance of the fourth field effect transistor, R M5 is the equivalent on-resistance of the fifth field effect transistor.

[0021] In one embodiment, the output current I out Satisfies the following calculation formula:

[0022] Among them, R mp The equivalent on-resistance of the first PMOS tube, I mp is the source-drain current of the first PMOS tube.

[0023] In one embodiment, the first PMOS tube is a power upper tube.

[0024] An embodiment of the present invention further provides a power chip, wherein the power chip includes the above-mentioned current detection circuit.

[0025] An embodiment of the present invention further provides an electronic device, comprising a first PMOS transistor, a first NMOS transistor, an inductor, a capacitor, a load resistor, and the above-mentioned current detection circuit;

[0026] The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the first end of the inductor, and the second end of the inductor is connected to the positive electrode of the capacitor and the positive electrode of the load resistor;

[0027] The negative electrode of the capacitor and the negative electrode of the load resistor are connected to the power ground.

[0028] Compared with the prior art, the embodiment of the present invention has the following beneficial effects: since the fifth field effect tube is used to reduce the current of the first PMOS tube to generate a detection current, the common gate amplifier including the first field effect tube and the second field effect tube serves as a feedforward path of the feedback system, and the third field effect tube serves as a feedback link of the negative feedback loop, so that the first PMOS tube and the fifth field effect tube have similar source-drain voltages, thereby improving the accuracy of current detection; at the same time, if the inductor current is negative, the first PMOS tube will generate a negative voltage drop, that is, the source voltage of the fourth field effect tube will be higher than the voltage of the first power supply, and the fourth field effect tube makes the source voltage of the second field effect tube still lower than the voltage of the first power supply, and is close to another input voltage of the common gate amplifier, so in this case the fifth field effect tube still works and generates an accurate negative detection current, thereby realizing the simultaneous detection of the positive inductor current and the negative inductor current. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0030] Figure 1 is an exemplary circuit schematic diagram of a related current detection circuit;

[0031] Figure 2 An exemplary circuit schematic diagram of a current detection circuit provided in an embodiment of the present application;

[0032] Figure 3 Another exemplary circuit schematic diagram of a current detection circuit provided in an embodiment of the present application;

[0033] Figure 4 Another exemplary circuit schematic diagram of a current detection circuit provided in an embodiment of the present application;

[0034] Figure 5 An exemplary circuit diagram of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0035] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0037] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0038] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0039] Figure 2 The structure diagram of the current detection circuit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0040] The above-mentioned current detection circuit is connected to a DC-DC converter, and the DC-DC converter includes a first P-channel metal oxide semiconductor (positive-channel metal oxide semiconductor, PMOS) tube MP and a first N-type metal oxide semiconductor (NMOS) tube MN; the current detection circuit includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a first current source I1, a second current source I2, a third current source I3 and a fourth current source I4;

[0041] The source of the fourth field effect transistor M4 is connected to the drain of the first PMOS transistor MP and the drain of the first NMOS transistor MN, the drain of the fourth field effect transistor M4 is connected to the source of the second field effect transistor M2 and the positive electrode of the first current source I1, the source of the fifth field effect transistor M5 and the source of the first PMOS transistor MP are connected to the first power supply VDD, the drain of the fifth field effect transistor M5 is connected to the source of the first field effect transistor M1 and the source of the third field effect transistor M3, the gate of the second field effect transistor M2 is connected to the gate of the first field effect transistor M1, the gate of the first field effect transistor M1, the drain of the first field effect transistor M1 and the positive electrode of the third current source I3, the drain of the second field effect transistor M2 is connected to the gate of the third field effect transistor M3 and the positive electrode of the second current source I2, and the drain of the third field effect transistor M3 and the positive electrode of the fourth current source I4 serve together as an output current output terminal of the current detection circuit to output the output current Iout.

[0042] The source of the first NMOS transistor MN, the cathode of the first current source I1, the cathode of the second current source I2, the cathode of the third current source I3 and the cathode of the fourth current source I4 are connected to the power ground.

[0043] It should be noted that the first PMOS transistor MP and the first NMOS transistor MN are power transistors of the DC-DC converter.

[0044] Among them, the source of the fourth field effect transistor M4, the drain of the first PMOS transistor MP and the drain of the first NMOS transistor MN are connected to the node LX; the voltage of the common connection point of the drain of the fifth field effect transistor M5, the source of the first field effect transistor M1 and the source of the third field effect transistor M3 is V1; the voltage of the common connection point of the drain of the fourth field effect transistor M4, the source of the second field effect transistor M2 and the positive electrode of the first current source I1 is V2.

[0045] Since the fifth field effect transistor M5 is used to reduce the current of the first PMOS tube to generate a detection current, the common gate amplifier including the first field effect transistor M1 and the second field effect transistor M2 is used as the feedforward path of the feedback system, and the third field effect transistor M3 is used as the feedback link of the negative feedback loop, so that the first PMOS tube MP and the fifth field effect transistor M5 have similar source-drain voltages, thereby improving the accuracy of current detection. At the same time, if the inductor current is negative, the first PMOS tube MP will generate a negative voltage drop, that is, the source voltage of the fourth field effect transistor M4 will be higher than the voltage Vdd of the first power supply. The fourth field effect transistor M4 makes the source voltage of the second field effect transistor M2 still lower than the voltage Vdd of the first power supply, and is close to the other input voltage of the common gate amplifier. Therefore, in this case, the fifth field effect transistor M5 still works and thereby generates an accurate negative detection current Iout, thereby realizing the simultaneous detection of the positive inductor current and the negative inductor current. The second current source I2 and the third current source I3 are used to provide a current load for the common gate amplifier circuit.

[0046] It should be noted that, in one embodiment, the first field effect transistor M1 , the second field effect transistor M2 , the third field effect transistor M3 , the fourth field effect transistor M4 , and the fifth field effect transistor M5 are all P-type field effect transistors.

[0047] The five field effect transistors are implemented using the same type of field effect transistors, which simplifies the process.

[0048] When the first PMOS tube MP is turned on, it works as a switch, its source-drain voltage is low, and its own equivalent on-resistance R mp is inversely proportional to the width-to-length ratio. Therefore, its drain-source voltage can be expressed as I mp R mp , I mp is the source-drain current of the first PMOS tube MP. Since V1 and V2 are similar, we can conclude that:

[0049] I mp R mp +(I1+I2)R M4 =I M5 R M5 (1)

[0050] Among them, I M5 is the source-drain current of the fifth field effect transistor M5, R mp is the equivalent on-resistance of the first PMOS tube MP, R M4 is the equivalent on-resistance of the fourth field effect transistor M4, R M5 is the equivalent on-resistance of the fifth field effect transistor M5. Therefore, the width-to-length ratio of the fifth field effect transistor M5 is Setting it to a smaller value can make I M5 Maintain relative I mp A lower value saves power. If it is too small, it will cause a large mismatch, thereby affecting the accuracy of the detection current. In addition, considering that the temperature of the first PMOS tube MP will increase during operation, the fifth field effect tube M5 needs to be placed near it so that the two have the same temperature.

[0051] Since there is a mismatch between the first PMOS tube MP and the fifth field effect tube M5, and there is an offset voltage in the common gate amplifier, I out There will be a certain error. In order to improve the detection accuracy, it is necessary to use a trimming circuit to provide a trimmed bias current. When the first PMOS tube MP is turned on, the node LX is at a high level, the load current is set to 0, and the current I4 of the fourth current source I4 is trimmed to make Iout 0. The trimmed I4 can be obtained from the following calculation formula:

[0052] I mp R mp +(I1+I2)RM4 =I M5 R M5 (2)

[0053] In addition, by Figure 2 We can get:

[0054] I4+I3+I out =I M5 (3)

[0055] Therefore, combining (1)(2)(3), after adjusting I4, the detected current I out The calculation formula is:

[0056]

[0057] like Figure 3 As shown, the current detection circuit further includes a first switch SW1, a second switch SW2, a sixth field effect transistor M6 and a fifth current source I5.

[0058] A first end of the first switch SW1 is connected to the drain of the fourth field effect transistor M4 and the positive electrode of the first current source I1, and a second end of the first switch SW1 is connected to the source of the second field effect transistor M2 and the second end of the second switch SW2; a source of the sixth field effect transistor M6 is connected to the first power supply VDD, a drain of the sixth field effect transistor M6 is connected to the positive electrode of the fifth current source I5 and the first end of the second switch SW2, and a negative electrode of the fifth current source I5 is connected to the power ground.

[0059] At the same time, at most one of the first switch SW1 and the second switch SW2 is closed.

[0060] It should be noted that a main branch and a secondary branch are respectively provided for the on and off states of the first PMOS transistor MP. The main branch includes the fourth field effect transistor M4, the first switch SW1 and the second field effect transistor M2, and the secondary branch includes the sixth field effect transistor M6, the second switch SW2 and the second field effect transistor M2.

[0061] When the first PMOS tube MP is turned on, the main branch including the first PMOS tube MP works, and the third field effect tube M3 outputs a positive or negative current.

[0062] When the first PMOS tube MP is turned off, the secondary branch is turned on, and the third field effect tube M3 outputs zero current, that is, the output current Iout is 0. When the main branch is working, if the source-drain current Imp of the first PMOS tube MP is negative, the fourth field effect tube M4 connected in series with the first PMOS tube MP provides a forward voltage drop, ensuring that the voltage V2 is still lower than Vdd, so that the differential input voltages V1 and V2 of the common gate amplifier circuit can be kept close, so that the fifth field effect tube M5 can still work normally and generate a more accurate detection current.

[0063] When the first switch SW1 is closed and the second switch SW2 is turned off, Figure 2 The same is not repeated here.

[0064] When the first PMOS transistor MP is turned off, the first switch SW1 is turned off and the second switch SW2 is closed, the secondary branch works. In this case, by adjusting the bias current I5, the gate voltage and current of the third field effect transistor M3 can be controlled, so that the output current Iout is 0.

[0065] When the first PMOS tube MP is turned off, the node LX is at a low level, the load current is set to 0, and the current I5 (the fifth current source) is adjusted so that I out is 0. The adjusted fifth current source I5 can be obtained from the following formula:

[0066] (I5+I2)R M6 =(I4+I3)R M5

[0067] Among them, R M6 is the equivalent on-resistance of the sixth field effect transistor M6.

[0068] like Figure 4 As shown, the current detection circuit further includes a third switch SW3; a first end of the third switch SW3 is connected to the drain of the fifth field effect transistor M5, and a second end of the third switch SW3 is connected to the source of the first field effect transistor M1 and the source of the third field effect transistor M3.

[0069] In order to match the first switch SW1 and the second switch SW2 , a third switch SW3 is added to the detection branch, and the third switch SW3 is always closed during the detection phase.

[0070] An embodiment of the present invention further provides a power chip, which includes the above-mentioned current detection circuit.

[0071] The embodiment of the present invention further provides an electronic device, such as Figure 5 As shown, the electronic device includes a first PMOS transistor MP, a first NMOS transistor MN, an inductor L, a capacitor C, a load resistor RL and the above-mentioned current detection circuit;

[0072] The drain of the first PMOS transistor MP is connected to the drain of the first NMOS transistor MN and the first end of the inductor L. The second end of the inductor L is connected to the positive electrode of the capacitor C and the positive electrode of the load resistor RL. The negative electrode of the capacitor C and the negative electrode of the load resistor RL are connected to the power ground.

[0073] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0074] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A current detection circuit, characterized in that: connected to a DC-DC converter, the DC-DC converter comprising a first PMOS tube and a first NMOS tube; the current detection circuit comprising a first field effect tube, a second field effect tube, a third field effect tube, a fourth field effect tube, a fifth field effect tube, a first current, a second current source, a third current source and a fourth current source; The source of the fourth field effect transistor is connected to the drain of the first PMOS transistor and the drain of the first NMOS transistor, the drain of the fourth field effect transistor is connected to the source of the second field effect transistor and the positive electrode of the first current source, the source of the fifth field effect transistor and the source of the first PMOS transistor are connected to the first power supply, the drain of the fifth field effect transistor is connected to the source of the first field effect transistor and the source of the third field effect transistor, the gate of the second field effect transistor is connected to the gate of the first field effect transistor, the drain of the first field effect transistor and the positive electrode of the third current source, the drain of the second field effect transistor is connected to the gate of the third field effect transistor and the positive electrode of the second current source, and the drain of the third field effect transistor and the positive electrode of the fourth current source serve together as the output current output terminal of the current detection circuit to output the output current; The source of the first NMOS tube, the cathode of the first current source, the cathode of the second current source, the cathode of the third current source and the cathode of the fourth current source are connected to a power ground.

2. The current detection circuit according to claim 1, characterized in that: Also includes a first switch, a second switch, a sixth field effect transistor and a fifth current source; A first end of the first switch is connected to the drain of the fourth field effect transistor and the positive electrode of the first current source, and a second end of the first switch is connected to the source of the second field effect transistor and the second end of the second switch; The source of the sixth field effect transistor is connected to the first power supply, the drain of the sixth field effect transistor is connected to the positive electrode of the fifth current source and the first end of the second switch, and the negative electrode of the fifth current source is connected to the power ground.

3. The current detection circuit according to claim 2, characterized in that: The current I5 of the fifth current source is obtained from the following calculation formula: (I5+I2)R M6 =(I4+I3)R M5 Where I2 is the current of the second current source, R M6 is the equivalent on-resistance of the sixth field effect transistor, I4 is the current of the fourth current source, I3 is the current of the third current source, R M5 is the equivalent on-resistance of the fifth field effect transistor.

4. The current detection circuit according to claim 2, characterized in that: At the same time, at most one of the first switch and the second switch is closed.

5. The current detection circuit according to claim 2, characterized in that: Also including a third switch; A first end of the third switch is connected to the drain of the fifth field effect transistor, and a second end of the third switch is connected to the source of the first field effect transistor and the source of the third field effect transistor.

6. The current detection circuit according to claim 1, characterized in that: The current I4 of the fourth current source I4 is obtained by the following calculation formula: mp R mp +(I1+I2)R M4 =I M5 R M5 Among them, I M5 is the source-drain current of the fifth field effect transistor M5, R mp is the equivalent on-resistance of the first PMOS tube MP, I1 is the current of the first current source, I2 is the current of the second current source, R M4 is the equivalent on-resistance of the fourth field effect transistor, R M5 is the equivalent on-resistance of the fifth field effect transistor.

7. The current detection circuit according to claim 6, characterized in that: The output current I out Satisfy the following calculation formula: Among them, R mp The equivalent on-resistance of the first PMOS tube, I mp is the source-drain current of the first PMOS tube.

8. The current detection circuit according to claim 1, characterized in that: The first PMOS tube is a power upper tube.

9. A power chip, characterized in that: The power chip comprises the current detection circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device comprises a first PMOS transistor, a first NMOS transistor, an inductor, a capacitor, a load resistor, and a current detection circuit as claimed in any one of claims 1 to 8; The drain of the first PMOS tube is connected to the drain of the first NMOS tube and the first end of the inductor, and the second end of the inductor is connected to the positive electrode of the capacitor and the positive electrode of the load resistor; The negative electrode of the capacitor and the negative electrode of the load resistor are connected to the power ground.

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