Display panel and display device

Abstract

The present application provides a display panel and a display device, wherein the display panel includes: an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, the array substrate includes: a first common electrode, including a plurality of sub-common electrodes, a first slit is formed between two adjacent sub-common electrodes, and the first slit is located in a pixel opening region; a second common electrode, which is located on a different conductive layer of the array substrate from the first common electrode, and the second common electrode at least partially overlaps with the first slit in the stacking direction of the array substrate. By arranging the second common electrode in the array substrate, the second common electrode at least partially overlaps with the first slit in the stacking direction of the array substrate, so as to compensate for the influence of the first slit in the first common electrode on the electric field.

Description

Technical Field

[0001] The present application mainly relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display principle of TFT LCD (Thin film transistor liquid crystal display): Under the action of an external electric field, the arrangement direction of liquid crystal molecules will change to varying degrees, thereby controlling the degree of light passing through the liquid crystal and achieving control of different grayscale brightness. Generally, the change in the orientation of liquid crystal molecules that occurs when the external electric field reaches a certain intensity is called Fredericksz transition. Using the Fredericksz transition principle, different liquid crystals can show various display modes. The display modes commonly used in TFT LCDs include TN display mode, IPS display mode, and VA display mode. Among them, the deformation technology FFS (Fringe Field Switching) of IPS is a kind of wide-viewing angle display mode. Because of its better viewing angle and color display, and higher transmittance, it is currently widely promoted and used in various panel manufacturers. Generally, the pixel electrode and COM electrode in the driving backplane are both located in the pixel opening area, and the two electrodes need to use transparent ITO material to allow the backlight to pass through.

[0003] As the development of the In-cell touch technology of the current touch screen gradually matures, it has obvious advantages over the previous On-cell touch technology, such as reduced thickness, reduced cost, reduced weight, less power consumption, etc. Since the current In-cell touch technology mainly needs to consider cost reduction, for large-size and high-resolution display devices, the number of touch channels of the IC will affect the number of ICs. In order to ensure the sensitivity of the touch, the size of the touch block is generally required to be within a certain range. When the touch block area is too large, the load inside the touch block will increase, resulting in limited touch sensitivity. Therefore, if the load size within the block can be reduced, the touch block area can be appropriately increased, thereby reducing costs. At the same time, when designing touch blocks in pixels, there will be differences between the design of conventional pixels and the design of touch pixels, such as aperture ratio and storage capacitance, resulting in a large difference between the pixel display at the segmentation and other normal pixels. Summary of the invention

[0004] The main purpose of the present application is to provide a display panel and a display device to solve the problem that the segmentation of common electrodes in existing touch pixels affects the pixel display.

[0005] To solve the above problems, the present application provides a display panel, which includes: an array substrate, a color filter substrate, and a liquid crystal layer arranged between the array substrate and the color filter substrate, the array substrate includes: a first common electrode, including a plurality of sub-common electrodes, a first slit is formed between two adjacent sub-common electrodes, and the first slit is located in the pixel opening area; a second common electrode, which is located on a different conductive layer of the array substrate from the first common electrode, and the second common electrode at least partially overlaps with the first slit in the stacking direction of the array substrate.

[0006] In one embodiment, the array substrate further includes: a scan line, arranged along a first direction; a data line, arranged along a second direction, the scan line and the data line define a plurality of sub-pixel regions, and the pixel opening region is located within the sub-pixel region; the second common electrode includes: a first strip electrode, arranged along the first direction, the first strip electrode at least partially overlaps with the first slit in the stacking direction of the array substrate; a second strip electrode, arranged along the first direction, the second strip electrode overlaps with the scan line in the stacking direction of the array substrate; wherein the first strip electrode is connected to the second strip electrode.

[0007] In one embodiment, the array substrate further includes: a touch line, which is arranged along the second direction, the touch line and the second common electrode are located in the same conductive layer of the array substrate, and the touch line is located in the pixel opening area; the first strip electrode includes a first branch electrode and a second branch electrode, and the first branch electrode and the second branch electrode are respectively located on both sides of the touch line; the second strip electrode includes a third branch electrode and a fourth branch electrode, and the third branch electrode and the fourth branch electrode are respectively located on both sides of the touch line; wherein the first branch electrode is connected to the third branch electrode, and the second branch electrode is connected to the fourth branch electrode.

[0008] In one embodiment, the width of the first strip electrode is greater than the width of the first slit, and the first strip electrode covers the first slit in the stacking direction of the array substrate.

[0009] In one embodiment, the first strip electrode overlaps with two adjacent sub-common electrodes in the stacking direction of the array substrate to form a first overlapping region and a second overlapping region respectively, and the width of the first overlapping region and the second overlapping region is greater than 0.5 μm and less than 1.5 μm.

[0010] In one embodiment, the array substrate further includes: a pixel electrode, which is located on different conductive layers of the array substrate from the first common electrode and the second common electrode, respectively; the pixel electrode includes a plurality of third strip electrodes, a second slit is formed between two adjacent third strip electrodes, and a second slit covers the first slit in the stacking direction of the array substrate.

[0011] In one embodiment, a second slit overlaps with two adjacent sub-common electrodes in the stacking direction of the array substrate to form a third overlapping region and a fourth overlapping region, respectively, and the sum of the widths of the third overlapping region and the fourth overlapping region is greater than 0.3 μm and less than 0.7 μm.

[0012] In one embodiment, in the same sub-pixel region, the number of the third strip electrodes is 7.

[0013] In one embodiment, the array substrate further includes a thin film transistor, and the second common electrode and the source and drain of the thin film transistor are located in the same conductive layer of the array substrate.

[0014] In order to solve the above problems, the present application also provides a display device, which includes a display panel and a backlight module. The display panel is the display panel described in any one of the above embodiments.

[0015] Through the above method, while ensuring the exposure disconnection distance at the touch division, a second common electrode is added below to compensate the electric field, so as to avoid sacrificing the number of pixel slits to affect the storage capacitor Cst and the light transmission efficiency; and the second common electrode includes a plurality of strip electrodes, and a plurality of strip electrodes are used to form a mesh connection, which can maximize the size of the opening area and reduce the load of the touch block, thereby effectively improving the display quality of the pixel. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0017] Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application;

[0018] Figure 2a It is a structural schematic diagram of an embodiment of a touch pixel of a display panel provided by the present application;

[0019] Figure 2b yes Figure 2a Schematic diagram of some structural details in;

[0020] Figure 3 is a structural schematic diagram of an embodiment of touch area segmentation;

[0021] Figure 4 is a structural schematic diagram of an embodiment of a normal touch pixel provided by the present application;

[0022] Figure 5It is a structural schematic diagram of an embodiment of touch pixel demarcation provided by the present application;

[0023] Figure 6 yes Figure 5 A partial enlarged schematic diagram of area A at the middle touch boundary;

[0024] Figure 7 is a structural schematic diagram of a second embodiment of a normal touch pixel provided by the present application;

[0025] Figure 8 It is a structural diagram of an embodiment of the slit7 block provided by the present application;

[0026] Fig. 9 It is a structural diagram of an embodiment of the slit6 block provided by the present application;

[0027] Fig.10 yes Figure 2a A partial enlarged schematic diagram in the embodiment;

[0028] Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure at G-G';

[0029] Fig.12 is a structural schematic diagram of an embodiment of a non-touch pixel of a display panel provided by the present application;

[0030] Fig.13 is based on Figure 2a and Fig.12 Schematic diagram of touch-controlled block pixel structure of two types of pixels;

[0031] Fig.14 yes Fig.13 A mesh schematic diagram of the second common electrode;

[0032] Fig.15 yes Fig.13 A partial enlarged schematic diagram of the middle T region;

[0033] Fig.16 It is a structural schematic diagram of an embodiment of a display device provided in the present application. Description of the drawings:

[0035] Display panel 100; array substrate 10; color filter substrate 20; liquid crystal layer 30; first common electrode 11; sub-common electrode 11a; second common electrode 12; first strip electrode 121; first branch electrode 121a; second branch electrode 121b; second strip electrode 122; third branch electrode 122a; fourth branch electrode 122b; scan line 13a; data line 13b; touch line 14; pixel electrode 15; third strip electrode 15a; thin film transistor 16; backlight module 200; display device 300; first slit I; second slit II. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be appreciated that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the art without making creative work are within the scope of protection of the present application.

[0037] The terms "first", "second", etc. in this application are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0038] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0039] At present, the touch technologies of TFT LCD touch screens generally include: OGS technology, In-cell technology and On-cell technology, among which OGS (one glass solution) is the main solution used in fully laminated LCD capacitive touch screens. It integrates the touch layer and the protective layer glass together, coats the ITO (indium tin oxide) conductive layer on the inner side of the protective glass, and directly coats and photolithographs the protective glass, thus saving a piece of glass and one lamination, making the LCD touch screen thinner and lighter, and reducing costs. However, since the OGS protective glass and the touch screen are integrated together, it usually needs to be strengthened first, then coated, etched, and finally cut. Cutting on the tempered glass is very troublesome, and some capillary cracks will form on the edge of the glass, which will reduce the strength of the glass. Among them, On-cell technology refers to the solution of embedding the touch screen between the color filter substrate and the polarizer of the display screen, that is, equipping the LCD panel with a touch sensor. Its technical difficulty is simpler than Incell. It is currently mostly used in Samsung Amoled panel products. Technically, it has not yet overcome the problems of thinness and uneven color when touching.

[0040] The In-cell technology refers to the method of embedding the touch panel function into the liquid crystal pixels, that is, embedding the touch sensor function inside the display screen. Incell places the ITO touch film under the upper glass substrate of the display panel and integrates it with the liquid crystal layer. The innovation of the In-cell touch panel is that the circuit is loaded on the liquid crystal, so that the LCD screen has the perception and touch input capabilities of the traditional touch screen. The In-cell touch panel is not only more accurate, but also eliminates the need for a touch panel, making the entire touch screen thinner and lighter. Traditional touch screens are difficult to see the display content clearly in the sun, but now that there is no touch panel, there is naturally no parallax, and readability is also improved.

[0041] In FFS display, the current In-cell touch technology mainly needs to consider cost reduction. For large-size and high-resolution display devices, the number of touch channels of the IC will affect the number of ICs. In order to ensure the sensitivity of touch, the size of the touch block is generally required to be within a certain range. When the touch block area is too large, the load inside the touch block will increase, resulting in limited touch sensitivity. Therefore, if the load size inside the block can be reduced, the touch block area can be appropriately increased, thereby reducing costs. At the same time, when designing touch blocks in pixels, there will be differences between the design of conventional pixels and the design of touch pixels, such as aperture ratio and storage capacitance, resulting in a large difference between the pixel display at the segmentation and other normal pixels.

[0042] Therefore, the present application provides a display panel 100 and a display device to solve the above problems.

[0043] See also Figure 1 , Figure 2a and Figure 2b As shown, Figure 1 is a schematic structural diagram of an embodiment of a display panel provided by the present application; Figure 2a It is a structural schematic diagram of an embodiment of a touch pixel of a display panel provided by the present application; Figure 2b yes Figure 2a Schematic diagram of some structural details in ; among them, Figure 1 As shown, the display panel 100 includes: an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 disposed between the array substrate 10 and the color filter substrate 20; more specifically, as shown Figure 2a and Figure 2b As shown, the array substrate 10 includes: a first common electrode 11 and a second common electrode 12; wherein the first common electrode 11 includes a plurality of sub-common electrodes 11a, a first slit I is formed between two adjacent sub-common electrodes 11a, and the first slit I is located in the pixel opening area; the second common electrode 12 and the first common electrode 11 are respectively located in different conductive layers of the array substrate 10, and the second common electrode 12 at least partially overlaps with the first slit I in the stacking direction of the array substrate 10.

[0044] For general In-cell Touch products, the common driving technology is TDDI, namely Touch and Display Driver Integration. TDDI technology integrates the touch chip and the display chip into a single chip. Figure 3 As shown in the example, Figure 3 It is a structural diagram of an embodiment of touch area block; in the panel design example, the common electrode ITO (needed to be used as a COM electrode during display) is divided into several blocks (i.e., the first common electrode 11 described in the present application) according to a certain size, and each block is used as an independent Touch block (touch block). Each Touch block can connect the Touch ITO to the Tx signal line (touch signal line) through a connecting hole, and the Tx signal line is respectively connected to the touch channel of the IC. In actual display, part of the display time will be used as the Touch acquisition time for touch recognition.

[0045] It can be understood that the electric field for driving the liquid crystal deflection in the FFS display panel 100 is composed of a pixel electrode and a COM electrode. Both electrodes are located in the Array driving backplane. Different color resists (R / G / B) and a light-shielding black matrix (BM) for color display are deposited on the CF color film substrate 20. The liquid crystal is located between the Array substrate (array substrate 10) and the CF substrate (color film substrate 20). For the actual display panel 100 drive, according to the pixel arrangement position and the driving scheme, it can be divided into 1G1D / DualGate / Tri-gate and other schemes. Compared with the 1G1D driving scheme, the Dual Gate / Tri-gate and other schemes can save the number of driving channels of the data line 13b, thereby effectively reducing the number of ICs and reducing the panel cost. The gate driving end can currently adopt the GOA scheme. Therefore, considering the cost reduction, the Tri-gate driving scheme is currently widely used. Different from the traditional 1G1D scheme, in simple terms, for pixel arrangement, the traditional pixel is rotated 90 degrees and placed horizontally, such as Figure 4 As shown, Figure 4 This is a schematic diagram of the structure of a touch pixel embodiment provided by the present application; a traditional In-cell pixel includes: a gate drive signal gate, a data signal data, a drive TFT, a pixel ITO Slit, a whole Com-ITO, and a black matrix BM. The non-BM area is the actual display opening area, and the metal signal line on the same layer next to the data is the touch signal line Tx. Taking the pixel embodiment of the present application as an example, if the slit meets the engineering preparation requirements, a maximum of 7 slits can be made. In actual display, the number of slits will affect the storage capacitor Cst and the light transmission efficiency (light efficiency).

[0046] In one embodiment, based on normal pixels, the pixel design at the touch division will be adjusted accordingly. In the pixel opening area, because the COM-ITO (first common electrode 11) needs to be divided into blocks, the entire first common electrode 11 needs to be disconnected. Generally, the horizontal disconnection position will be selected within the display area or on the Gate line (scanning line 13a). In traditional design, when the division position is on the Gate, because the Gate line is a high-voltage signal, the common electrode needs to wrap the scanning line 13a to achieve signal shielding and avoid light leakage. The disconnection of ITO itself also requires an exposure distance, so the scanning line 13a needs to be made very wide to ensure the wrapping amount and exposure distance of the scanning line 13a, but this method will cause a significant decrease in the display opening area, affecting the penetration rate.

[0047] Therefore, based on this situation, there are Figure 5 As shown, Figure 51 is a schematic diagram of a structure of an embodiment of the touch pixel boundary provided by the present application; COM segmentation is performed in the display opening area, that is, COM-ITO disconnection is performed in the area between the pixel ITO Slits, such as Figure 6 As shown in the partial enlarged figure, Figure 6 yes Figure 5 A partial enlarged diagram of the touch boundary area A; As can be seen from the enlarged diagram of the touch boundary area A, for currently commonly used exposure machines, a is the exposure spacing of the same layer of ITO, which is generally set to 3um or above. Since COM-ITO needs to wrap the pixel ITO at a certain distance b or c to ensure that the edge electric field of the two will not affect the display, b is generally about 2um according to experience. Therefore, the distance between the two pixel ITO slits at this position should be at least 7um. Therefore, based on this space requirement, different from Figure 4 For normal pixel display, the touch signal can only reduce one slit to meet the requirement, that is, there are only 6 slits.

[0048] like Figure 7 As shown, Figure 7 is a structural diagram of a second embodiment of a normal touch pixel provided by the present application; based on Figure 5 Regarding the design requirements for touch pixels, since the number of slits will affect Cst and light efficiency, when the normal pixel and the touch pixel differ by one slit, the display characteristics between the normal pixel and the touch pixel will be quite different. Therefore, in order to ensure the consistency of pixel display, a compatible design is chosen, that is, the 7 slits of the normal pixel are changed to 6. However, this solution will sacrifice the capacitance and light efficiency advantages of the overall pixel.

[0049] based on Figure 4 and Figure 7 Normal sub-pixel matching for different slit numbers Figure 5 The two display pixels are composed of touch pixels in Figure 8 and Fig. 9 As shown, Figure 8 It is a structural diagram of an embodiment of the slit7 block provided by the present application; Fig. 9 Schematic diagram of the structure of the slit6 block embodiment provided by the present application; generally, the pixels at the COM disconnection position will have some design differences from other pixels. Figure 8 As shown, for the design of pixel color film, one pixel will contain 3 sub-pixels, namely Figure 4 and Figure 7The pixel in is a sub-pixel. Since the penetration rate of B (Blue) in the LCD color resistor is the smallest and the penetration rate of G (Green) is the highest, when some factors affecting the aperture ratio design are placed on the B pixel, the sacrificed aperture has the smallest impact on the penetration. Because the touch pixel division position is generally affected by the transfer hole design or the slight influence of the electric field at the division point, the actual penetration will be affected. Therefore, the division point is generally selected on the B sub-pixel, such as Figure 8 and Fig. 9 As shown, for the embodiments of 7 slits and 6 slit sub-pixels, the dividing points are all set on the middle B sub-pixel.

[0050] Therefore, based on the above-mentioned embodiment scheme, the display panel 100 provided by the present application retains the original COM electrode division within the pixel opening area. In order to ensure the original light effect and Cst requirements, the Slit7 root design is maintained in the pixel, and the COM electrode is adjusted at the division slit design, such as Figure 2a As shown, by providing the second common electrode 12 in the array substrate 10 , the second common electrode 12 at least partially overlaps with the first slit I in the stacking direction of the array substrate 10 , so as to compensate for the influence of the first slit I in the first common electrode 11 on the electric field.

[0051] Optionally, in one embodiment, if Figure 2a As shown, in the solution of the present application, the array substrate 10 further includes: a scan line 13a and a data line 13b, wherein the scan line 13a is arranged along a first direction; the data line 13b is arranged along a second direction, the scan line 13a and the data line 13b define a plurality of sub-pixel regions, and the pixel opening region is located within the sub-pixel region; the second common electrode 12 includes: a first strip electrode 121 and a second strip electrode 122, wherein the first strip electrode 121 is arranged along the first direction, and the first strip electrode 121 at least partially overlaps with the first slit I in the stacking direction of the array substrate 10; the second strip electrode 122 is arranged along the first direction, and the second strip electrode 122 overlaps with the scan line 13a in the stacking direction of the array substrate 10; wherein the first strip electrode 121 is connected to the second strip electrode 122.

[0052] Optionally, in one embodiment, if Figure 2aAs shown, in the solution of the present application, the array substrate 10 also includes: a touch line 14, which is arranged along the second direction, the touch line 14 and the second common electrode 12 are located in the same conductive layer of the array substrate 10, and the touch line 14 is located in the pixel opening area; the first strip electrode 121 includes a first branch electrode 121a and a second branch electrode 121b, and the first branch electrode 121a and the second branch electrode 121b are respectively located on both sides of the touch line 14; the second strip electrode 122 includes a third branch electrode 122a and a fourth branch electrode 122b, and the third branch electrode 122a and the fourth branch electrode 122b are respectively located on both sides of the touch line 14; wherein the first branch electrode 121a is connected to the third branch electrode 122a, and the second branch electrode 121b is connected to the fourth branch electrode 122b.

[0053] The present application scheme is based on the current IGZO technology. Taking the FFS display panel 100 as an example, the common IGZO display screen process sequence and film thickness are as follows:

[0054] M1 (4000Å) → GI (4000Å) → IGZO (1500Å) → M2 (4000Å) → PVX1 (3000Å) → PFA (20000Å) → 1-ITO (600Å) → PVX2 (2000Å) → 2-ITO (500Å).

[0055] Among them, M1 is used as the Gate signal (scan line 13a), M2 is used as the Data signal (data line 13b), IGZO or Oxide is used as a semiconductor, 1-ITO is COM ITO, and 2-ITO is pixel ITO. When COM-ITO is connected to the M2 layer (Tx) signal as a COM electrode, since it is impossible to directly connect C-ITO and M2, P-ITO is required for bridging. The punching relationship is: PAS2 hole (punching for PVX2) is used to connect P-ITO and C-ITO, PAS1 and PAS2 holes (punching for PVX2 / PFA) are used to connect P-ITO and M2, and indirectly realize the connection between M2 and C-ITO. When M2 (drain) is connected to pixel ITO, PAS1 and PAS2 holes are required for connection.

[0056] Understandably, see Fig.10 As shown, Fig.10 yes Figure 2a A partial enlarged schematic diagram of the embodiment; in order to keep the original COM segmentation within the pixel opening area, and to ensure the original light effect and Cst requirements, the third strip electrode 15a (Slit) is kept in the pixel with 7 strips. Figure 5 The design of the third strip electrode 15a at the split point is adjusted; further, refer to Fig.11 As shown, Fig.11 yes Fig.10 Schematic diagram of the cross-sectional structure at G-G' in FIG. M1 (scanning line 13a) is provided between the Glass layer and the GI layer.

[0057] Optionally, in one embodiment, the width of the first strip electrode 121 is greater than the width of the first slit I, and the first strip electrode 121 covers the first slit I in the stacking direction of the array substrate 10. It can be understood that since the first strip electrode 121 needs to perform electric field compensation on the first common electrode 11, it is necessary to set the width thereof to be greater than the width of the first slit I so as to cover the width of the first slit I and ensure the effect of the pixel electric field.

[0058] Optionally, in one embodiment, the first strip electrode 121 overlaps with two adjacent sub-common electrodes 11 a in the stacking direction of the array substrate 10 to form a first overlapping region and a second overlapping region respectively, and the width of the first overlapping region and the second overlapping region is greater than 0.5 μm and less than 1.5 μm.

[0059] Understandable, such as Fig.11 As shown, the COM electrode segmentation area distance B value (i.e., the width of the first slit I) is set to an exposure safety value of about 3um, and an SD (M2) layer (i.e., the second common electrode 12) is set below the first common electrode 11 (COM electric field) as a compensation electric field of the first common electrode 11, and is connected to the COM signal through signal switching to be used as a COM electrode; in one embodiment, the wrapping amounts C1 and C2 of the SD wrapping spacing B are about 1um, that is, the widths of the first overlapping area and the second overlapping area are about 1um.

[0060] Optionally, in one embodiment, if Figure 2a and Fig.11 As shown, the array substrate 10 also includes: a pixel electrode 15, which is located on different conductive layers of the array substrate 10 from the first common electrode 11 and the second common electrode 12, respectively; the pixel electrode 15 includes a plurality of third strip electrodes 15a, and a second slit II is formed between two adjacent third strip electrodes 15a, and a second slit II covers the first slit I in the stacking direction of the array substrate 10.

[0061] Optionally, in one embodiment, a second slit II overlaps with two adjacent sub-common electrodes 11a in the stacking direction of the array substrate 10 to form a third overlapping area and a fourth overlapping area, respectively, and the sum of the widths of the third overlapping area and the fourth overlapping area is greater than 0.3 μm and less than 0.7 μm.

[0062] It is understandable that in order to ensure the pixel electric field effect, the original design Fig.11As shown, A1 and A2 are required to be greater than about 2um. In this design, due to the electric field compensation effect of the first strip electrode 121 (SD) in the second common electrode 12, the values ​​of A1 and A2 can be very small. Fig.11 In the design of the third strip electrode 15a (slit) itself with a 3.5um spacing, A1 and A2 can be 0.5um in total, A1 and A2 can be equal or unequal (in the original solution, generally in order to maximize the space, b=c≥2um). The 3.5um spacing value in the above description is only an embodiment. In actual design, this value can be designed according to actual conditions and is not specifically limited here; the corresponding A1 and A2 can be positive or negative values, among which the smaller the value of the first strip electrode 121 is, the smaller the impact on the light effect will be, while ensuring that the line is not broken.

[0063] That is, compared with traditional FFS pixels, the touch ITO segmentation position needs to ensure sufficient electric field wrapping value for the pixel ITO. This proposal suggests that the ITO only ensures the exposed disconnection distance at the segmentation point, and increases the metal COM at the bottom to compensate for the electric field. At the same time, the mesh connection of the metal COM is increased in the horizontal direction, thereby completing the metal mesh connection of the entire touch block, which can maximize the size of the opening area and reduce the touch block load.

[0064] Optionally, in one embodiment, in the same sub-pixel region, the number of the third strip electrodes 15a is 7. Since the COM electrode is divided in the opening region, the number of the third strip electrodes 15a needs to be reduced to 6 to meet the display requirements. In this embodiment, the number of the third strip electrodes 15a is controlled to 7, which can also ensure Cst and light efficiency without affecting the display.

[0065] It can be understood that the solution of this application is applicable to pixel types corresponding to different FFS, that is, it is applicable to single-domain or dual-domain pixels, and is not affected by the inclination angle and width of the third strip electrode 15a. At the same time, the design values ​​in this application are only based on the design of this proposal, and the specific values ​​can be adjusted and modified accordingly according to the design.

[0066] like Figure 2a and Figure 4 As shown, the touch line 14 in the pixel is composed of Figure 4Move to the middle position of the third strip electrode 15a of the pixel next to the data line 13b (data signal line), and set the second common electrode 12 (SD layer) below the pixel division area and above the scan line 13a, that is, set the first strip electrode 121 below the pixel division area, and set the second strip electrode 122 above the scan line 13a, and both serve as COM common signals (recorded as SD-COM). Because the touch block needs to be divided, the second common electrode 12 and the touch line 14 (Tx) need to be disconnected (when the touch line 14 of this touch block passes through its own pixel, the second common electrode 12 (SD layer) and the touch line 14 signal at this position will be connected). In the center, due to the disconnection of the second common electrode 12, there is no second common electrode 12 under the P-ITO pixel, and there is a risk of light leakage at this location, so a small piece of BM layer is added for coverage. The SD-COM layers on both sides of the touch line 14 will be meshed, that is, the first common electrode 11 inside the touch block will be covered with a metal SD layer (second common electrode 12) except ITO. Since the resistance of the second common electrode 12 is much smaller than that of the ITO material, the overall COM load in the touch block will be greatly reduced, thereby being able to meet the needs of large-size touch blocks.

[0067] like Fig.12 As shown, Fig.12 This is a schematic diagram of the structure of an embodiment of a non-touch pixel of a display panel provided by the present application; the difference from the touch pixel is that the first common electrode 11 and the second common electrode 12 are not disconnected in the middle position, and the other designs are the same. Through the design of this proposal, the touch pixel and the normal pixel can maintain the same number of third strip electrodes 15a (slit), which can minimize the impact of touch on normal pixels and maximize the compatible design.

[0068] See also Fig.13 , Fig.14 and Fig.15 As shown, Fig.13 is based on Figure 2a and Fig.12 Schematic diagram of touch-controlled block pixel structure of two types of pixels; Fig.14 yes Fig.13 A mesh schematic diagram of the second common electrode; Fig.15 yes Fig.13 A local enlarged schematic diagram of the middle T area; based on Figure 2a and Fig.12The network design of the second common electrode 12 is shown in FIG. 1 . Assuming that Tx1 is the touch signal line of the upper touch block 1 in the figure, and Tx2 is the touch signal line of the lower touch block 2, when Tx1 passes through the middle of the touch block 1, the mesh connection of the second common electrode 12 will be connected to Tx1. When Tx1 passes through the middle of the lower touch block 2, the mesh connection of the second common electrode 12 of the touch block 2 will be disconnected from Tx1. Tx2 needs to be disconnected from the second common electrode 12 of the touch block 1 on the right side, and will be connected to the second common electrode 12 of the lower touch block 2. The second common electrode 12 on the left side of the touch block 1 and the second common electrode 12 on the right side will be connected through the two holes in the enlarged figure, that is, the mesh connection on the left and right is completed. The specific punching method is: PAS2 hole connects COM-ITO and P-ITO, and PAS2+PFA sleeve hole completes the connection between P-ITO and SD. Since PAS2 only punches holes to COM-ITO, the hole can be placed near the trench, thereby completing the metal mesh connection of the entire touch block, maximizing the size of the opening area and reducing the touch block load.

[0069] Optionally, in one embodiment, the array substrate 10 further includes a thin film transistor 16 , and the second common electrode 12 and the source and drain of the thin film transistor 16 are located in the same conductive layer of the array substrate 10 .

[0070] A corresponding sub-pixel can be electrically connected to the scan line 13a and the data line 13b of the adjacent thin film transistor 16 through the thin film transistor 16, and the common electrode is divided into a plurality of independent second common electrodes 12, each touch line is electrically connected to a second common electrode 12, and the touch line is electrically connected to one of the data lines 13b of the adjacent touch line through a switch element. During the display time, each second common electrode 12 is used to apply a common signal, and during the touch time period, each second common electrode 12 is used to apply a touch signal. That is, the second common electrode 12 can not only realize the touch function, but also serve as a common electrode. In one embodiment, the thin film transistor 16 includes a gate, an active layer, a drain and a source. The gate and the scan line 13a are located in the same layer and are electrically connected. The gate and the active layer are separated by an insulating layer, the source is electrically connected to the data line 13b, and the drain is electrically connected to the pixel electrode 15 through a contact hole.

[0071] To solve the above problems, the present application also provides a display device 300, such as Fig.16 As shown, Fig.16 3 is a schematic structural diagram of an embodiment of a display device provided in the present application; the display device 300 includes a display panel 100 and a backlight module 200, wherein the display panel 100 is the display panel 100 described in any one of the above embodiments.

[0072] The present application provides a display panel 100, which includes: an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30 arranged between the array substrate 10 and the color filter substrate 20, the array substrate 10 includes: a first common electrode 11, including a plurality of sub-common electrodes 11a, a first slit I is formed between two adjacent sub-common electrodes 11a, and the first slit I is located in a pixel opening area; a second common electrode 12, which is located on a different conductive layer of the array substrate 10 from the first common electrode 11, and the second common electrode 12 at least partially overlaps with the first slit I in the stacking direction of the array substrate 10.

[0073] Through the above method, the ITO at the touch division of the display panel 100 only ensures the exposure disconnection distance, and the second common electrode 12 is added below to compensate the electric field. At the same time, the mesh connection of the second common electrode 12 is increased in the horizontal direction, thereby completing the metal mesh connection of the entire touch block, which can maximize the size of the opening area, reduce the touch block load, and effectively improve the display quality of the pixel.

[0074] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, characterized in that: The display panel includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate, wherein the array substrate includes: A first common electrode, comprising a plurality of sub-common electrodes, wherein a first slit is formed between two adjacent sub-common electrodes, and the first slit is located in the pixel opening area; wherein each of the sub-common electrodes serves as an independent touch control block; A second common electrode, which is located on a different conductive layer of the array substrate from the first common electrode, and the second common electrode at least partially overlaps with the first slit in a stacking direction of the array substrate; The array substrate further includes: A scanning line is arranged along a first direction; The data lines are arranged along the second direction, the scan lines and the data lines define a plurality of sub-pixel regions, and the pixel opening regions are located in the sub-pixel regions; The second common electrode comprises: A first strip electrode is arranged along the first direction, wherein at least a portion of the first strip electrode overlaps with the first slit in a stacking direction of the array substrate; A second strip electrode is arranged along the first direction, and the second strip electrode overlaps with the scanning line in the stacking direction of the array substrate; Wherein, the first strip electrode is connected to the second strip electrode; The array substrate further includes: a touch line, arranged along the second direction, the touch line and the second common electrode being located on the same conductive layer of the array substrate, and the touch line being located in the pixel opening region; The first strip electrode includes a first branch electrode and a second branch electrode, and the first branch electrode and the second branch electrode are respectively located on two sides of the touch control line; The second strip electrode includes a third branch electrode and a fourth branch electrode, and the third branch electrode and the fourth branch electrode are respectively located on two sides of the touch line; The first branch electrode is connected to the third branch electrode, and the second branch electrode is connected to the fourth branch electrode.

2. The display panel according to claim 1, characterized in that: The width of the first strip electrode is greater than the width of the first slit, and the first strip electrode covers the first slit in a stacking direction of the array substrate.

3. The display panel according to claim 2, characterized in that: The first strip electrode overlaps with two adjacent sub-common electrodes in the stacking direction of the array substrate to form a first overlapping area and a second overlapping area respectively. The width of the first overlapping area and the second overlapping area is greater than 0.5 μm and less than 1.5 μm.

4. The display panel according to claim 1, characterized in that: The array substrate further includes: A pixel electrode is located on different conductive layers of the array substrate from the first common electrode and the second common electrode. The pixel electrode includes a plurality of third strip electrodes, a second slit is formed between two adjacent third strip electrodes, and one second slit covers the first slit in the stacking direction of the array substrate.

5. The display panel according to claim 4, characterized in that: One of the second slits overlaps with two adjacent sub-common electrodes in the stacking direction of the array substrate to form a third overlapping region and a fourth overlapping region, respectively. The sum of the widths of the third overlapping region and the fourth overlapping region is greater than 0.3 μm and less than 0.7 μm.

6. The display panel according to claim 4, characterized in that: In the same sub-pixel area, the number of the third strip electrodes is 7.

7. The display panel according to claim 1, characterized in that: The array substrate further includes a thin film transistor, and the second common electrode and the source and drain of the thin film transistor are located in the same conductive layer of the array substrate.

8. A display device, characterized in that: The display device comprises a display panel and a backlight module, and the display panel is the display panel as claimed in any one of claims 1 to 7.

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