A low thermal resistance gallium nitride device structure

Abstract

This invention discloses a low thermal resistance gallium nitride (GaN) device structure. The device structure includes an isolation layer, an active layer, and a dielectric slot array. The active layer is located on the upper surface of the isolation layer, and the width of the isolation layer is greater than that of the active layer, forming a boss structure. The two ends of the upper surface of the active layer are connected to a source electrode and a drain electrode, respectively. A gate metal is deposited on the upper surface of the barrier layer between the source and drain electrodes to form a gate electrode. A slot array is disposed in the active layer between the gate and drain electrodes, comprising multiple slots arranged in a row, and the slots are filled with dielectric material. By introducing a dielectric slot array, this invention achieves a reduction in the device's peak temperature of nearly 50°C without reducing the device's current output capability at saturation, while simultaneously obtaining a highly uniform temperature distribution. This can be used to solve reliability problems such as self-heating effects caused by high temperatures in HEMT power electronic devices.

Description

Technical Field

[0001] This invention relates to the field of GaN HEMT devices in the semiconductor technology field, and particularly to a low thermal resistance gallium nitride device structure. Background Technology

[0002] Gallium nitride (GaN), as a third-generation semiconductor material, exhibits enormous application potential in the field of power devices due to its wide bandgap, high breakdown voltage, and high electron mobility. Compared to traditional silicon (Si) devices, GaN power devices have lower on-resistance and higher operating frequencies, giving them significant advantages in high-efficiency and high-density power conversion.

[0003] In the field of power electronics, GaN power devices can support higher switching frequencies and greater power densities, enabling miniaturization and weight reduction of devices. This is particularly important for applications requiring high-frequency, high-efficiency conversion, such as server power supplies, electric vehicle chargers, and renewable energy systems. The high-frequency characteristics of GaN devices also make them widely used in wireless charging and 5G communication base stations, offering higher energy efficiency and smaller size. GaN power devices are expected to occupy a larger share of the future power electronics market, driving the development of various electronic devices towards higher performance and higher energy efficiency.

[0004] Over the past three decades, most research on GaN-based power devices has focused on AlGaN / GaN heterojunction materials. GaN can form modulated-doped AlGaN / GaN heterojunction structures with AlGaN, and the two-dimensional electron gas conductive channels formed at room temperature exhibit high electron concentration and high electron mobility. Although GaN power devices outperform Si devices in high-temperature and high-pressure environments, giving them unique advantages in aerospace, military, and industrial high-temperature applications, their high two-dimensional electron gas concentration often results in considerable current capability. However, under prolonged high-power operation, the heat generation of these devices cannot be ignored. Higher junction temperatures accelerate lattice collisions within GaN, causing lattice scattering, leading to decreased current capability, threshold voltage drift, and increased leakage current, severely impacting device performance and reliability.

[0005] To address the issues caused by the high junction temperature of GaN devices, researchers often have to make trade-offs between device heat dissipation and current capability during the device design phase, aiming to find a satisfactory compromise. Currently, most manufacturers typically address the heat dissipation problem by optimizing the packaging process and implementing external heat dissipation devices. These solutions all have their limitations.

[0006] For example, in the existing technical solution of low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure and preparation method (Zhang Jincheng, Hao Lu, Liu Zhihong et al. Low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure and preparation method [P]. Shaanxi Province: CN112216739B, 2022-08-12.), the device material structure includes: a silicon substrate layer (1); a high thermal conductivity dielectric layer (2) located on the upper surface of the silicon substrate layer (1) and forming a first patterned interface with the silicon substrate layer (1); a buffer layer (3) located on the upper surface of the high thermal conductivity dielectric layer (2) and forming a second patterned interface with the high thermal conductivity dielectric layer (2); a channel layer (4) located on the upper surface of the buffer layer (3); and a composite barrier layer (5) located on the upper surface of the channel layer (4). The fabrication method of the device material structure includes the following steps: obtaining an initial substrate, wherein the initial substrate is a silicon substrate with a target crystal orientation; sequentially fabricating a nucleation layer and a transition layer on the initial substrate; sequentially fabricating a buffer layer, a channel layer, and a composite barrier layer on the transition layer; flipping the sample and fabricating a transition substrate on the lower surface of the flipped composite barrier layer using wafer bonding technology; removing the initial substrate, the nucleation layer, and the transition layer to expose the buffer layer; etching the surface of the buffer layer to form a second patterned surface; and depositing a high thermal conductivity material on the second patterned surface of the buffer layer to form a high thermal conductivity dielectric layer. A portion of the high thermal conductivity dielectric layer is formed by etching the surface of another silicon substrate layer with a target crystal orientation to form a first patterned surface; the high thermal conductivity material is deposited on the first patterned surface of the silicon substrate layer to form a second portion of the high thermal conductivity dielectric layer; the first portion of the high thermal conductivity dielectric layer is bonded to the second portion of the high thermal conductivity dielectric layer using wafer bonding technology to form the high thermal conductivity dielectric layer, wherein an uneven first patterned interface is formed between the high thermal conductivity dielectric layer and the silicon substrate layer and an uneven second patterned interface is formed between the high thermal conductivity dielectric layer and the buffer layer; the transition substrate is removed to obtain a low thermal resistance silicon-based gallium nitride microwave and millimeter-wave device material structure.

[0007] The existing technology involves fabricating a groove structure on the substrate, which requires pattern transfer and etching before epitaxy. This is not only difficult to implement technically, but also cannot guarantee against defects after epitaxy. Furthermore, this technology is a purely heat-conducting solution that increases the contact area; the dielectric material determines the heat conduction effect, which has significant limitations and cannot achieve substantial cooling. Summary of the Invention

[0008] The purpose of this invention is to address the overheating problem of GaN HEMT devices. Based on existing planar GaN HEMT devices, an improvement is proposed: a low thermal resistance GaN device structure. Without reducing the device's saturation current output capability, a slot array with polarization effect is introduced into the barrier layer and buffer layer. This alters the distribution of conductive channels, forming multiple temperature centers. The peak temperature center point shifts towards the drain, away from the gate, achieving a reduction of nearly 50°C in the device's peak temperature. Simultaneously, a highly uniform temperature distribution is obtained, improving the device's temperature stability. This invention can be used to solve reliability problems such as self-heating caused by high temperatures in HEMT power electronic devices. It will have wide applications in power electronic devices such as mobile phone fast charging, new energy vehicles, and charging piles, possessing significant application value, especially in high-temperature scenarios and special applications.

[0009] The objective of this invention is achieved by at least one of the following technical solutions.

[0010] A low thermal resistance gallium nitride device structure includes an isolation layer, an active layer, a source electrode, a drain electrode, a gate electrode, a dielectric slot array, and a passivation layer.

[0011] The isolation layer comprises a substrate, a nucleation layer, and a buffer layer stacked sequentially from bottom to top;

[0012] The active layer consists of an intrinsic layer, an insertion layer, and a barrier layer stacked sequentially from bottom to top;

[0013] The active layer is located on the upper surface of the isolation layer, and the width of the isolation layer is greater than that of the active layer, forming a boss structure;

[0014] The two ends of the upper surface of the active layer are connected to the source electrode and the drain electrode, respectively; gate metal is deposited on the upper surface of the barrier layer between the source electrode and the drain electrode to form the gate electrode;

[0015] A slot array is provided in the active layer between the gate electrode and the drain electrode. The slot array includes multiple slots arranged in a row. The slots in the slot array extend downwards through the barrier layer and the insertion layer into the intrinsic layer. The slots are filled with dielectric material.

[0016] Except for the locations where the source electrode, drain electrode, and gate electrode are connected, the upper surface of the active layer is covered with a passivation layer to protect the active layer.

[0017] Furthermore, the substrate is a silicon carbide substrate or a silicon substrate.

[0018] Furthermore, the intrinsic layer and the barrier layer in the active layer form a heterojunction with polarization effect, including gallium nitride / aluminum gallium nitride.

[0019] Furthermore, using reactive ion etching or inductively coupled plasma etching equipment, fluorine-based plasma is employed to form slot arrays.

[0020] Furthermore, the slot array is located within the active layer, and its area accounts for 1% to 99% of the active layer area between the gate electrode and the drain electrode.

[0021] Furthermore, the structural pattern of the slots in the slot array can be any shape or combination thereof, including rectangular.

[0022] Furthermore, one or more slots in the slot array extend downward into the active layer.

[0023] Furthermore, the filling material of the slots in the slot array is a dielectric material with low thermal resistance and polarization effect, including aluminum nitride or aluminum gallium nitride.

[0024] Furthermore, the source and drain electrodes employ a multilayer metal stack, consisting of Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 100 / 10 / 100 nm, respectively.

[0025] Furthermore, the gate electrode employs a multilayer metal stack, consisting of Ni / Au layers from bottom to top, with thicknesses of 50 / 200 nm.

[0026] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0027] 1. This invention achieves a device with high temperature reliability by introducing a dielectric slot array with polarization effect. Under the structure of the invention, the peak temperature of the device is reduced and the self-heating effect is greatly improved.

[0028] 2. The temperature center of the device is shifted from the gate edge near the drain to the socket tip closest to the drain, effectively reducing gate leakage current and greatly improving device reliability.

[0029] 3. In terms of process implementation, compared with conventional HEMT devices, only one more photolithography, etching and deposition process is required, and the process steps are simple.

[0030] 4. Compared to relying on subsequent methods (such as packaging) to reduce device heat generation, this new structure solves the problem at its source, greatly reducing packaging costs. Attached Figure Description

[0031] Figure 1 This is a structural diagram of the isolation layer in an embodiment of the present invention;

[0032] Figure 2 This is a diagram of the active layer structure in an embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of a conventional HEMT device in an embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of the low thermal resistance gallium nitride device structure in an embodiment of the present invention;

[0035] Figure 5 This is a schematic diagram of the low thermal resistance gallium nitride device structure in an embodiment of the present invention;

[0036] Figure 6 This is a schematic diagram of the low thermal resistance gallium nitride device structure in an embodiment of the present invention;

[0037] Figure 7 This is a magnified view of the lattice temperature details of the patented HEMT device with a slot array structure in an embodiment of the present invention at a gate voltage of 0.5V and a drain voltage of 30V.

[0038] Figure 8 This is a comparison of the output curves of the patented HEMT device with a slot array structure and a conventional HEMT device under a gate voltage of 0.5V in this embodiment of the invention.

[0039] Figure 9 This is a comparison chart of the output curves of the patented HEMT device with a slot array structure and a conventional HEMT device after drain current saturation in this embodiment of the invention. Detailed Implementation

[0040] The specific implementation of the present invention will be further described below with reference to the accompanying drawings and embodiments. However, the implementation and protection of the present invention are not limited thereto. It should be noted that any processes or process parameters that are not described in particular below are those that can be implemented by those skilled in the art with reference to the prior art.

[0041] Comparative example:

[0042] Conventional HEMT devices such as Figure 3 As shown, it includes an isolation layer 1, an active layer 2, a source electrode 3, a drain electrode 4, a gate electrode 5, and a passivation layer 7.

[0043] like Figure 1 As shown, the isolation layer 1 includes a substrate 01, a nucleation layer 02 and a buffer layer 03 stacked sequentially from bottom to top;

[0044] like Figure 2 As shown, the active layer 2 includes an intrinsic layer 04, an insertion layer 05, and a barrier layer 06 stacked sequentially from bottom to top;

[0045] The active layer 2 is located on the upper surface of the isolation layer 1. The width of the isolation layer 1 is greater than that of the active layer 2, forming a boss structure.

[0046] The two ends of the upper surface of the active layer 2 are connected to the source electrode 3 and the drain electrode 4, respectively; gate metal is deposited on the upper surface of the barrier layer 2 between the source electrode 3 and the drain electrode 4 to form the gate electrode 5.

[0047] Except for the locations where the source electrode 3, drain electrode 4 and gate electrode 5 are connected, the upper surface of the active layer 2 is covered with a passivation layer 7 to protect the active layer 2.

[0048] Example:

[0049] In one embodiment, such as Figure 4 As shown, a low thermal resistance gallium nitride device structure includes an isolation layer 1, an active layer 2, a source electrode 3, a drain electrode 4, a gate electrode 5, a dielectric slot array 6, and a passivation layer 7.

[0050] In one embodiment, such as Figure 1 As shown, the isolation layer 1 includes a substrate 01, a nucleation layer 02 and a buffer layer 03 stacked sequentially from bottom to top;

[0051] In one embodiment, such as Figure 2 As shown, the active layer 2 includes an intrinsic layer 04, an insertion layer 05, and a barrier layer 06 stacked sequentially from bottom to top;

[0052] The active layer 2 is located on the upper surface of the isolation layer 1. The width of the isolation layer 1 is greater than that of the active layer 2, forming a boss structure.

[0053] The two ends of the upper surface of the active layer 2 are connected to the source electrode 3 and the drain electrode 4, respectively; gate metal is deposited on the upper surface of the barrier layer 2 between the source electrode 3 and the drain electrode 4 to form the gate electrode 5.

[0054] A slot array 6 is provided in the active layer 2 between the gate electrode 5 and the drain electrode 4. The slot array 6 includes multiple slots arranged in a row. The slots in the slot array 6 extend downward through the barrier layer 06 and the insertion layer 05 into the intrinsic layer 04. The slots are filled with dielectric material.

[0055] Except for the locations where the source electrode 3, drain electrode 4 and gate electrode 5 are connected, the upper surface of the active layer 2 is covered with a passivation layer 7 to protect the active layer 2.

[0056] In one embodiment, such as Figure 5 As shown, a low thermal resistance gallium nitride device structure is presented. Figure 4 Based on this, the spacing of the slot array and the interface area occupied by the barrier layer 06 and intrinsic layer 04 are changed. The number of slots is determined according to the actual application. The height of the slot from the surface of the active layer 2 gradually increases, decreases or remains the same along the direction from the gate electrode 5 to the drain electrode 4.

[0057] In one embodiment, such as Figure 6 As shown, a low thermal resistance gallium nitride device structure is presented. Figure 4 Based on this, the slot array 6 with a rectangular slot cross-section is replaced with a slot array 6 with a triangular slot cross-section. The slot cross-section includes rectangles, triangles, trapezoids and other shapes.

[0058] In one embodiment, the source electrode 3 and the drain electrode 4 are multilayer metal stacks, which are Ti / Al / Ni / Au from bottom to top, with thicknesses of 20 / 100 / 10 / 100nm respectively.

[0059] In one embodiment, the gate electrode 5 is a multilayer metal stack, consisting of Ni / Au layers from bottom to top, with a thickness of 50 / 200 nm.

[0060] In the Silvaco simulation example Figure 7 This is a magnified view of the lattice temperature details of a HEMT device with a slot array structure using this invention at a gate voltage of 0.5V and a drain voltage of 30V. It shows that for every N slots introduced, N+1 temperature centers are introduced, with the temperature peak appearing on the right side of the slot closest to the drain. Furthermore, the Silvaco lattice temperature distribution diagram shows that a conventional HEMT device has only one temperature center with a peak temperature as high as 451.7K; while the HEMT device with the slot array structure of this invention, by changing the path of the conductive channel, introduces multiple temperature centers, reducing the peak temperature to only 406.1K, a difference of nearly 50℃. Simultaneously, because the patented structure moves the temperature center away from the gate, it greatly alleviates the self-heating effect and improves temperature reliability.

[0061] In the Silvaco simulation example Figure 8 This is a comparison of the output curves of the HEMT device with the slot array structure of this invention and a conventional HEMT device at a gate voltage of 0.5V. As the drain voltage scans from 0 to 40V, the saturation current of the HEMT device with the slot array structure of this invention is almost the same as that of the conventional HEMT device. In fact, as the gate voltage increases, due to the self-heating effect, the saturation current of the patented HEMT device with the slot array structure will exceed that of the conventional device.

[0062] In the Silvaco simulation example Figure 9 This is a comparison of the output curves of the HEMT device with the slot array structure of this invention and a conventional HEMT device after drain current saturation. At a gate voltage of 0.5V, and after the device enters saturation output mode, the HEMT device with the slot array structure is more than three times less affected by self-heating than the conventional device. The degradation of the conventional HEMT device exceeds that of the HEMT device with the slot array structure as the gate voltage continues to increase. The saturation current of the conventional HEMT device at a drain voltage of 40V is 1.620mA, which is lower than the saturation current of the patented HEMT device with the slot array structure at a drain voltage of 30V (1.623mA).

[0063] The above embodiments are merely preferred examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, can make various modifications and changes in form and detail according to the method of the present invention without departing from the principles and scope of the present invention. However, these modifications and changes based on the present invention are still within the protection scope of the claims of the present invention.

Claims

1. A low thermal resistance gallium nitride device structure, characterized in that, It includes an isolation layer (1), an active layer (2), a source electrode (3), a drain electrode (4), a gate electrode (5), a dielectric slot array (6), and a passivation layer (7). The isolation layer (1) includes a substrate (01), a nucleation layer (02) and a buffer layer (03) stacked sequentially from bottom to top; The active layer (2) includes an intrinsic layer (04), an insertion layer (05) and a barrier layer (06) stacked sequentially from bottom to top. The active layer (2) is located on the upper surface of the isolation layer (1), and the width of the isolation layer (1) is greater than that of the active layer (2), forming a boss structure; The two ends of the upper surface of the active layer (2) are connected to the source electrode (3) and the drain electrode (4), respectively; gate metal is deposited on the upper surface of the barrier layer (06) between the source electrode (3) and the drain electrode (4) to form the gate electrode (5). A slot array (6) is provided in the active layer (2) between the gate electrode (5) and the drain electrode (4). The slot array (6) includes multiple slots arranged in a row. The slots in the slot array (6) extend downward through the barrier layer (06) and the insertion layer (05) into the intrinsic layer (04). The slots are filled with dielectric material. The filling material of the slots in the slot array (6) is a dielectric material with low thermal resistance and polarization effect. The filling material includes aluminum nitride or aluminum gallium nitride. Except for the positions where the source electrode (3), drain electrode (4) and gate electrode (5) are connected, the upper surface of the active layer (2) is covered with a passivation layer (7) to protect the active layer (2).

2. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, The substrate (01) is a silicon carbide substrate or a silicon substrate.

3. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, In the active layer (2), the intrinsic layer (04) and the barrier layer (06) form a heterojunction with polarization effect, including gallium nitride / aluminum gallium nitride.

4. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, Using reactive ion etching or inductively coupled plasma etching equipment, a fluorine-based plasma is used to form a slot array (6).

5. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, The slot array (6) is located in the active layer (2) and its area accounts for 1% to 99% of the area of ​​the active layer (2) between the gate electrode (5) and the drain electrode (4).

6. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, The slots in the slot array (6) have a rectangular shape.

7. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, The source electrode (3) and drain electrode (4) are made of multilayer metal stacks, which are Ti / Al / Ni / Au from bottom to top.

8. The low thermal resistance gallium nitride device structure according to claim 1, characterized in that, The gate electrode (5) adopts a multilayer metal stack, which consists of Ni / Au from bottom to top.

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