Integrated circuit device and method of manufacturing the same

Abstract

Disclosed is an integrated circuit device including: a fin-type active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer disposed on the substrate and covering a lower portion of a sidewall of the fin-type active region, the isolation layer including an insulating liner disposed conformally on the lower portion of the sidewall of the fin-type active region and an insulating fill layer on the insulating liner; a cap layer surrounding an upper surface and the sidewall of the fin-type active region, including a second semiconductor material different from the first semiconductor material, wherein the cap layer has an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure disposed on the cap layer and extending in a second direction perpendicular to the first direction.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0131580, filed with the Korean Intellectual Property Office on October 22, 2019, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuit devices and methods of manufacturing the same, and more specifically, to integrated circuit devices including fin-type active regions and methods of manufacturing the integrated circuit devices. Background Technology

[0004] The recent trend towards lighter, thinner, smaller, and shorter electronic products has increased the demand for highly integrated integrated circuit (IC) devices. However, as IC devices shrink, short-channel effects can occur in transistors, potentially reducing their reliability. IC devices incorporating finned active regions have been proposed to mitigate these short-channel effects. However, reducing the size of the finned active region may increase the likelihood of damage (e.g., surface oxidation), thus potentially decreasing the reliability of the IC device. Summary of the Invention

[0005] Some aspects of this disclosure provide integrated circuit devices with reduced size and high reliability.

[0006] Some aspects of this disclosure provide methods for manufacturing integrated circuit devices with reduced size and high reliability.

[0007] According to some aspects of the present invention, an integrated circuit device includes: a fin-type active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and comprising a first semiconductor material; an isolation layer disposed on the substrate and covering a lower portion of a sidewall of the fin-type active region, the isolation layer comprising an insulating liner disposed on the lower portion of the sidewall of the fin-type active region and an insulating fill layer on the insulating liner; a capping layer surrounding the upper surface and sidewall of the fin-type active region, comprising a second semiconductor material different from the first semiconductor material, wherein the capping layer has an upper surface, sidewalls, and a faceted surface between the upper surface and the sidewalls; and a gate structure disposed on the capping layer and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

[0008] According to some aspects of the inventive concepts, an integrated circuit device includes a fin-type active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer disposed on the substrate and covering a lower portion of a sidewall of the fin-type active region, the isolation layer including an insulating liner disposed on the lower portion of the sidewall of the fin-type active region and an insulating fill layer on the insulating liner; a cap layer surrounding an upper surface and a sidewall of the fin-type active region, wherein the cap layer includes a second semiconductor material different from the first semiconductor material, and the cap layer includes an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure disposed on the cap layer and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, wherein, on the sidewall of the fin-type active region, a bottom surface of the cap layer contacts an upper surface of the insulating liner.

[0009] According to some aspects of the inventive concepts, an integrated circuit device includes a first fin-type active region disposed on a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; a second fin-type active region disposed on the substrate, spaced apart from the first fin-type active region in a second direction perpendicular to the first direction, wherein the second fin-type active region extends in the first direction, includes the first semiconductor material, and has a first sidewall facing the first fin-type active region and a second sidewall opposite the first sidewall; a first cap layer surrounding an upper surface and a sidewall of the first fin-type active region, the first cap layer including a second semiconductor material different from the first semiconductor material, and the first cap layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; a second cap layer surrounding an upper surface and a sidewall of the second fin-type active region and including the second semiconductor material, the second cap layer including a first portion disposed on the first sidewall of the second fin-type active region and a second portion disposed on the second sidewall of the second fin-type active region and having a bottom surface disposed at a level higher than a bottom surface of the first portion; and a gate structure intersecting the first fin-type active region and the second fin-type active region and extending in the second direction.

[0010] According to another aspect of the inventive concept, a method of manufacturing an integrated circuit device includes forming a fin-type active region including a first semiconductor material on a substrate, the fin-type active region extending in a first direction parallel to an upper surface of the substrate; forming an isolation layer covering a lower portion of a sidewall of the first fin-type active region, the isolation layer including an insulating liner and an insulating fill layer; forming a cap layer on an exposed surface of the fin-type active region, the cap layer including a second semiconductor material different from the first semiconductor material; shaping the cap layer such that the cap layer has an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall, wherein the cap layer is shaped by performing a re-etching process on the cap layer; and forming a gate structure on the cap layer, the gate structure extending in a second direction perpendicular to the first direction and perpendicular to the upper surface of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0011] Examples of embodiments of the inventive concept can be more clearly understood by the following detailed description together with the accompanying drawings, in which:

[0012] Figure 1 is a layout view of an integrated circuit device according to some embodiments;

[0013] Figure 2 is a cross-sectional view of an integrated circuit device along a line X1-X1' in Figure 1

[0014] Figure 3 is a cross-sectional view of an integrated circuit device along a line Y1-Y1' in Figure 1

[0015] Figure 4 is a magnified view of a CX1 portion of Figure 3

[0016] Figure 5 is a cross-sectional view of an integrated circuit device according to some embodiments;

[0017] Figure 6 is a cross-sectional view of an integrated circuit device according to some embodiments;

[0018] Figure 7 is a cross-sectional view of an integrated circuit device according to some embodiments;

[0019] Figure 8 is a cross-sectional view of an integrated circuit device according to some embodiments;

[0020] Figure 9 is a layout view of an integrated circuit device according to some embodiments;

[0021] Figure 10 is a cross-sectional view of an integrated circuit device along​​​Figure 9 is a cross-sectional view along the line X2-X2' in

[0022] Figure 11 is a cross-sectional view along the line X2-X2' in Figure 9 is a cross-sectional view along the line Y2-Y2' in

[0023] Figure 12A to Figure 20B is a cross-sectional view along the line X2-X2' in Figure 12A , Figure 13A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and 20A is a cross-sectional view along the line X2-X2' in Figure 9 and Figure 12B , Figure 13B , Figure 14 , Figure 15 , Figure 16B , Figure 17B , Figure 18B , Figure 19B and Figure 20B is a cross-sectional view along the line Y2-Y2' in Figure 9 . DETAILED DESCRIPTION

[0024] Aspects of the present disclosure will now be described in more detail with reference to the figures.

[0025] Figure 1 is a layout view of the integrated circuit device 100 according to some embodiments. Figure 2 is a cross-sectional view along the line X1-X1' in Figure 1 is a cross-sectional view along the line X1-X1' in Figure 3 is a cross-sectional view along the line Y1-Y1' in Figure 1 is a cross-sectional view along the line Y1-Y1' in Figure 4 is a magnified view of the region CX1 of Figure 3 For ease of description and for ease of illustration, Figure 1 only some components (e.g., fin-type active regions FA and gate structures GS) of the integrated circuit device 100 are shown.

[0026] Referring to Figure 1 to Figure 4 , the first semiconductor layer 112 can be disposed on a first upper surface 110F1 of the substrate 110, and the fin-type active regions FA including the first semiconductor layer 112 can protrude from a second upper surface 110F2 of the substrate 110. The fin-type active regions FA can protrude in a first direction (i.e., a direction parallel to the second upper surface 110F2 of the substrate 110) from the first semiconductor layer 112. Figure 1The isolation layer 114 can be disposed on the substrate 110. The isolation layer 114 can extend over the lower portions of the two sidewalls of the fin-type active region FA. The isolation layer 114 can be disposed on the substrate 110.

[0027] According to some embodiments, the substrate 110 can include a Group IV semiconductor (e.g., silicon (Si) or germanium (Ge)), a compound semiconductor including Group IV-IV elements (e.g., silicon germanium (SiGe) or silicon carbide (SiC), or a compound semiconductor including Group III-V elements (e.g., gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP)). The substrate 110 can include a conductive region, e.g., a doped well or a doped structure. The fin-type active region FA can be an active region that constitutes an NMOS transistor, or an active region that constitutes a PMOS transistor.

[0028] According to some embodiments, the first semiconductor layer 112 can include a first semiconductor material. For example, the first semiconductor material can be different from a material used to form the substrate 110. According to some embodiments, the substrate 110 can include silicon (Si), and the first semiconductor layer 112 can include silicon germanium (Ge). According to some embodiments, the substrate 110 can include silicon germanium having a first content (e.g., concentration) of germanium, and the first semiconductor layer 112 can include silicon germanium having a second content (e.g., concentration) of germanium, where the second content is different from the first content.

[0029] As Figure 3 and Figure 4 As best shown, the isolation layer 114 can include an insulating liner 114L and an insulating fill layer 114F. The insulating liner 114L can be formed to cover the second upper surface 110F2 of the substrate 110, and the lower portions of the sidewalls FAS of the fin-type active region FA. The insulating fill layer 114F can be on the insulating liner 114L and can surround the lower portions of the sidewalls FAS of the fin-type active region FA. For example, the insulating liner 114L can include, but is not limited to, an oxide layer formed according to a process that oxidizes surfaces of the fin-type active region FA, and the insulating fill layer 114F can include, but is not limited to, fluorine silicate glass (FSG), undoped silicate glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), or tetraethyl orthosilicate zircon (TOSZ).

[0030] As in Figure 4As best seen, the cap layer 120 can be disposed on an upper portion of the sidewall FAS of the fin-shaped active region FA and on the upper surface FAU of the fin-shaped active region FA. The cap layer 120 can include a second semiconductor material. The second semiconductor material can be different than a first semiconductor material included in the fin-shaped active region FA (e.g., included in the first semiconductor layer 112). According to some embodiments, the second semiconductor material can include silicon and the first semiconductor material can include silicon germanium. According to some embodiments, the second semiconductor material can include silicon germanium having a first content of germanium and the first semiconductor material can include silicon germanium having a second content of germanium different than the first content. However, the inventive concepts are not limited thereto.

[0031] The cap layer 120 can have an upper surface 120U, a sidewall 120S, and a facet surface 120F. The facet surface 120F can be inclined at a first angle θ1 with respect to the first upper surface 110F1 of the substrate 110. In some embodiments, the first angle θ1 can be between about 30° and about 60°. For example, the facet surface 120F can preferably be oriented to a crystal plane parallel to the (111) plane of a silicon crystal structure, and the first angle θ1 of the facet surface 120F can be between about 41° and about 46°. However, the inventive concepts are not limited thereto.

[0032] The cap layer 120 can have a first thickness t11 on the upper surface FAU of the fin-shaped active region FA and can have a second thickness t12 on the sidewall FAS of the fin-shaped active region FA or at an edge of the facet surface. The second thickness t12 can be less than the first thickness t11. The first thickness t11 can be, but is not limited to, about to about between about 10 nm and about 50 nm.

[0033] According to some embodiments, the cap layer 120 can be formed on the fin-shaped active region FA via an epitaxy process using the second semiconductor material and an etch-back process performed after the epitaxy process. As a result of the epitaxy process and the subsequent etch-back process, the cap layer 120 can be formed to have a shape including the facet surface 120F. The cap layer 120 can act as a protective layer that prevents loss of germanium from the surfaces of the fin-shaped active region FA and / or prevents damage to the surfaces of the fin-shaped active region FA during one or more subsequent fabrication processes.

[0034] As best seen in FIG. 1A, the fin-shaped active region FA can include a first semiconductor layer 112 and a second semiconductor layer 114. The first semiconductor layer 112 can include a first semiconductor material. The second semiconductor layer 114 can include a second semiconductor material. The second semiconductor material can be different than the first semiconductor material. According to some embodiments, the first semiconductor material can include silicon germanium and the second semiconductor material can include silicon. According to some embodiments, the first semiconductor material can include silicon germanium having a first content of germanium and the second semiconductor material can include silicon germanium having a second content of germanium different than the first content. However, the inventive concepts are not limited thereto. Figure 4As shown, the cap layer 120 can be formed on the upper portions of the sidewalls FAS of the fin active regions FA and on the upper surfaces FAU of the fin active regions FA, and can not be formed on the lower portions of the sidewalls FAS of the fin active regions FA that are covered by the insulating liner 114L. In other words, the lower portions of the sidewalls FAS of the fin active regions FA that are covered by the insulating liner 114L can be absent of the cap layer 120. The bottom surface 120L of the cap layer 120 can contact the upper surface of the insulating liner 114L and can be disposed at the same level as the upper surface of the isolation layer 114.

[0035] The gate structures GS extending in a second direction (i.e., the Y direction) parallel to the first upper surface 110F1 of the substrate 110 can be disposed on the cap layer 120 and the isolation layer 114. For example, as shown, the first gate structure GS1 and the second gate structure GS2 can be spaced apart from each other and can each extend in the second direction and can intersect the fin active regions FA extending in the first direction. Figure 1 Figure 1 As shown, the first gate structure GS1 and the second gate structure GS2 can be spaced apart from each other and can each extend in the second direction and can intersect the fin active regions FA extending in the first direction.

[0036] The gate structures GS can include a gate electrode 132, a gate insulating layer 134, a gate cap layer 136, and a gate spacer 138.

[0037] The gate electrode 132 can include doped polysilicon, a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal silicide, or a combination thereof. For example, the gate electrode 132 can include, but is not limited to, aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo), tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), titanium nitride (TiN), tungsten nitride (WN), titanium aluminum (TiAl), aluminum titanium nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), or a combination thereof. According to some embodiments, the gate electrode 132 can include a work function metal containing layer and an interstitial filling metal layer. The layer containing the work function metal can include at least one metal selected from Ti, W, ruthenium (Ru), niobium (Nb), Mo, hafnium (Hf), nickel (Ni), cobalt (Co), platinum (Pt), ytterbium (Yb), terbium (Tb), dysprosium (Dy), erbium (Er), and palladium (Pd). The interstitial filling metal layer can include a W layer or an Al layer. According to some embodiments, the gate electrode 132 can include, but is not limited to, a stack structure of TiAlC / TiN / W, a stack structure of TiN / TaN / TiAlC / TiN / W, or a stack structure of TiN / TaN / TiN / TiAlC / TiN / W.

[0038] ​The gate insulating layer 134 can be disposed to extend over a bottom surface and sidewalls of the gate electrode 132 in the second direction. The gate insulating layer 134 can be between the gate electrode 132 and the cap layer 120, and between the gate electrode 132 and an upper surface of the isolation layer 114. Because the cap layer 120 covers the upper surface FAU of the fin-type active region FA and an upper portion of the sidewall FAS of the fin-type active region FA, the gate insulating layer 134 can not contact the fin-type active region FA.

[0039] According to some embodiments, the gate insulating layer 134 can include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than a silicon oxide layer, or a combination thereof. The high-k dielectric layer can include a metal oxide or a metal oxynitride. For example, a high-k dielectric layer usable as the gate insulating layer 134 can be formed of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), or a combination thereof, but the inventive concept is not limited thereto.

[0040] The gate cover layer 136 can be disposed on the gate electrode 132. The gate cover layer 136 can cover an upper surface of the gate electrode 132 and can extend in the second direction (i.e., the Y direction). According to some embodiments, the gate cover layer 136 can include silicon nitride or silicon oxynitride. Figure 1

[0041] The gate spacers 138 can be disposed on two sidewalls of the gate electrode 132 and two sidewalls of the gate cover layer 136. The gate spacers 138 can each extend on the two sidewalls of the gate electrode 132 in an extension direction of the gate electrode 132, and the gate insulating layer 134 can be between the gate electrode 132 and the gate spacers 138. According to some embodiments, the gate spacers 138 can include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon carbon nitride (SiC x N y ), silicon carbon oxynitride (SiO x C y N z ), or a combination thereof.

[0042] According to some embodiments, the gate spacers 138 can include a plurality of layers formed of different materials. Although in the drawings, the gate spacers 138 are illustrated as a single layer, the gate spacers 138 can include a plurality of layers formed of different materials. For example, the gate spacers 138 can include a first layer formed of silicon nitride and a second layer formed of silicon oxynitride. Figure 2 ​Each gate spacer 138 includes a single layer, but each gate spacer 138 can include a first spacer layer (not shown), a second spacer layer (not shown), and a third spacer layer (not shown) sequentially stacked on each sidewall of the gate electrode 132. According to some embodiments, the first and third spacer layers can include silicon nitride, silicon oxide, or silicon oxynitride. The second spacer layer can include an insulating material having a lower dielectric constant than the dielectric constant of the first spacer layer. According to some embodiments, the second spacer layer can be or can include an air space.

[0043] The source / drain region 140 can be disposed on respective sides of two adjacent gate structures GS facing each other in the fin-shaped active region FA. The source / drain region 140 can fill an interior of a recessed region 140R extending from each respective side of the two adjacent gate structures GS to an interior of the fin-shaped active region FA. A horizontal level of a bottom surface of the recessed region 140R can be higher than a horizontal level LV1 of the second upper surface 110F2 of the substrate 110 and can be lower than an upper surface level LV2 of the isolation layer 114 (e.g., a horizontal level of a bottom surface of a portion of each gate structure GS in contact with the isolation layer 114). Although not shown in the drawings, the source / drain region 140 can have a polygonal shape with sidewalls having a tilt in the second direction (Y direction).

[0044] According to some embodiments, the source / drain region 140 can include a plurality of semiconductor layers filling an interior of the recessed region 140R. For example, the plurality of semiconductor layers can include, but are not limited to, a doped Si layer, a doped Ge layer, a doped SiC layer, a doped SiGe layer, or a doped InGaAs layer. The plurality of semiconductor layers can have different impurity concentrations from each other. According to some embodiments, when the fin-shaped active region FA is an active region for an NMOS transistor, the source / drain region 140 can include SiC doped with a first impurity or Si doped with a first impurity, and the first impurity can be phosphorus (P), arsenic (As), antimony (Sb), etc. According to some embodiments, when the fin-shaped active region FA is an active region for a PMOS transistor, the source / drain region 140 can include SiGe doped with a first impurity, and the first impurity can be boron (B), gallium (Ga), etc.

[0045] The gate-to-gate insulating layer 150 can be disposed between two adjacent gate structures GS and can cover the source / drain region 140 and the isolation layer 114. The gate-to-gate insulating layer 150 can include silicon oxide, silicon nitride, a TEOS layer, or an ultra-low-k (ULK) layer having an ultra-low dielectric constant between about 2.2 and about 2.4. The ULK layer can include a SiOC layer or a SiCOH layer.

[0046] The width of the gate structure GS and the length of the channel region can be reduced due to the scaling trend of the integrated circuit device described above. A method of forming a fin-type active region FA by using a second semiconductor material (e.g., silicon germanium) has been proposed to improve the performance of the integrated circuit device. However, the silicon germanium is susceptible to oxidation or damage in a process of removing the sacrificial gate structure for forming the gate electrode and / or in a process of forming the gate insulating layer. In particular, the surface oxidation of the fin-type active region FA having a reduced size can cause an increase in the interface defect density of the gate insulating layer or time-dependent dielectric breakdown (TDDB), and thus the reliability of the integrated circuit device is degraded.

[0047] According to some of the above-described embodiments, the cap layer 120 including the second semiconductor material can be formed on the surface of the fin-type active region FA by using an epitaxial process and a subsequent etch-back process. Since the cap layer 120 can prevent the surface of the fin-type active region FA from being oxidized or damaged in a subsequent process of removing the dummy gate electrode and / or in a process of forming the gate insulating layer, the increase in the interface defect density of the gate insulating layer 134 or the occurrence of TDDB can be prevented, and the integrated circuit device 100 can have high reliability.

[0048] Figure 5 is a cross-sectional view of an integrated circuit device 100A according to some embodiments. Figure 5 is a cross-sectional view of a portion of the integrated circuit device 100A corresponding to the region CX1 of Figure 3 is an enlarged cross-sectional view of the portion of Figure 1 to Figure 4 and Figure 5 The same reference numbers in

[0049] Referring to Figure 5 , the fin-type active region FA can include an inner region 112B and a surface region 112S. The surface region 112S can indicate a portion of the fin-type active region FA located within a first distance d11 from a surface (e.g., the sidewall FAS and the upper surface FAU) of the fin-type active region FA, and the inner region 112B can indicate a portion of the fin-type active region FA beyond the first distance d11 from the surface (e.g., the sidewall FAS and the upper surface FAU) of the fin-type active region FA. In other words, the surface region 112S can be a portion of the fin-type active region FA having a distance from the sidewall FAS of the fin-type active region FA that is less than the first distance d11, and the inner region 112B can be a portion of the fin-type active region FA having a distance from the sidewall FAS of the fin-type active region FA that is greater than the first distance d11.

[0050] According to some embodiments, the surface region 112S can include silicon germanium having a first germanium content, and the inner region 112B can include silicon germanium having a second germanium content smaller than the first germanium content. For example, in the epitaxial process and the subsequent etch-back process for forming the cap layer 120, the surface region 112S can be formed by germanium atoms within the fin active region FA being diffused or moved near the surface of the fin active region FA. For example, in the epitaxial process and the subsequent etch-back process for forming the cap layer 120, silicon germanium within the fin active region FA can be condensed, and thus the amount of germanium included in the surface region 112S (e.g., the first germanium content) can be greater than the amount of germanium included in the inner region 112B (e.g., the second germanium content).

[0051] According to some embodiments, the surface region 112S can have a first band gap energy Eg1, the inner region 112B can have a second band gap energy Eg2, the cap layer 120 can have a third band gap energy Eg3, and a relationship Eg1 < Eg2 < Eg3 can be established. That is, the cap layer 120 can have a larger band gap energy than the inner region 112B, which in turn has a larger band gap energy than the surface region 112S. Since the surface region 112S between the cap layer 120 and the inner region 112B has the smallest band gap energy, i.e., the first band gap energy Eg1, the carrier mobility in the channel region of the fin active region FA can be improved.

[0052] According to some of the above-described embodiments, since the surface region 112S of the fin active region FA adjacent to the cap layer 120 has the smallest band gap energy, i.e., the first band gap energy Eg1, the electrical performance of the integrated circuit device 100A can be improved. Furthermore, since the cap layer 120 can prevent the surface of the fin active region FA from being oxidized or damaged, an increase in the interface defect density of the gate insulating layer 134 or the occurrence of TDDB can be prevented, and the integrated circuit device 100A can have high reliability.

[0053] Figure 6 is a cross-sectional view of an integrated circuit device 100B according to some embodiments. Figure 6 is a cross-sectional view of a portion of the integrated circuit device 100B corresponding to the region CX1 of Figure 3 is an enlarged cross-sectional view of the portion of Figure 1 to Figure 5 and Figure 6 The same reference numbers in

[0054] Reference is made to Figure 6The cap layer 120B can have an upper surface 120U, a sidewall 120S, and a facet surface 120F. The cap layer 120B can have a thickness that decreases as a distance from a top of the sidewall FAS of the fin-shaped active region FA increases. For example, the cap layer 120B can have a first thickness t11 on the upper surface FAU of the fin-shaped active region FA, and can have a second thickness t12 on the sidewall FAS of the fin-shaped active region FA or at an edge of the facet surface 120F, and the second thickness t12 is less than the first thickness t11. The cap layer 120B can also have a third thickness t13 at a lower portion of the sidewall FAS of the fin-shaped active region FA, and the third thickness t13 is less than the first thickness t11 or the second thickness t12. For example, the first thickness t11 can be between about 1 nm and about 10 nm, the second thickness t12 can be between about 0.1 nm and about 1 nm, and the third thickness t13 can be between about 0.1 nm and about 1 nm, but the inventive concepts are not limited thereto. between about 0.1 nm and about 1 nm, but the inventive concepts are not limited thereto.

[0055] According to some embodiments, the cap layer 120B can be formed on the fin-shaped active region FA via an epitaxy process by using a second semiconductor material, and a subsequent etch-back process. For example, the cap layer 120B can be formed by performing a first etch-back process by using a first etchant gas including germane (GeH4) and then performing a second etch-back process using a second etchant gas including hydrogen chloride (HCl). Alternatively, the cap layer 120B can be formed by performing an etch-back process using an etchant gas including at least one of germane (GeH4), chlorine (Cl2), and hydrogen chloride (HCl). However, the inventive concepts are not limited thereto, and the cap layer 120B can be formed by any one of various combinations of an epitaxy process and an etch-back process.

[0056] The cap layer 120B can serve as a protective layer that prevents loss of germanium from a surface of the fin-shaped active region FA or damages a surface of the fin-shaped active region FA in a subsequent manufacturing process.

[0057] Figure 7 is a cross-sectional view of an integrated circuit device 100C according to some embodiments. Figure 7 is an enlarged cross-sectional view of a portion of the integrated circuit device 100C corresponding to the region CX1 of Figure 3 Figure 1 to Figure 6 and Figure 7 like reference numerals refer to like elements throughout.

[0058] Referring to Figure 7 ​​​​​​An interface layer 160 can be further formed between the cap layer 120 and the gate structure GS and between the isolation layer 114 and the gate structure GS. The interface layer 160 can be disposed between the cap layer 120 and the gate insulating layer 134, and thus the cap layer 120 and the interface layer 160 can be formed between the fin active region FA and the gate insulating layer 134.

[0059] According to some embodiments, the interface layer 160 can include at least one of silicon nitride, silicon oxynitride, and silicon carbonitride. For example, the interface layer 160 can include a material layer formed by first forming the cap layer 120 and then performing a plasma nitridation process on respective exposed surfaces of the cap layer 120 and the isolation layer 114. For example, the interface layer 160 can be formed by converting a portion of the cap layer 120 having a relatively small thickness with respect to the exposed surface of the cap layer 120 into silicon nitride and / or a portion of the isolation layer 114 having a relatively small thickness with respect to the exposed surface of the isolation layer 114 into silicon nitride. However, the present inventive concept is not limited thereto.

[0060] According to some embodiments, the interface layer 160 can be formed to have a relatively small thickness, and thus the thickness of the cap layer 120 can be reduced. For example, because the interface layer 160 together with the cap layer 120 can prevent the surface of the fin active region FA from being oxidized or damaged, the integrated circuit device 100C can have high reliability.

[0061] Figure 8 is a cross-sectional view of an integrated circuit device 100D according to some embodiments. Figure 8 is a cross-sectional view of a portion of the integrated circuit device 100D corresponding to a region CX1 of Figure 3 is an enlarged cross-sectional view of a portion of Figure 1 to Figure 7 and Figure 8 The same reference numbers in

[0062] Referring to Figure 8 , the fin active region FA can have a circular upper surface FAU and a sidewall FAS connected to the upper surface FAU. Each of the upper surface FAU and the sidewall FAS of the fin active region FA can form a curved surface. The cap layer 120D can have a circular upper surface 120U, a sidewall 120S, and a curved surface 120FC between the upper surface 120U and the sidewall 120S.

[0063] According to some embodiments, the cap layer 120D can be formed on the fin active region FA via an epitaxial process by using a second semiconductor material, and a subsequent etch-back process. By further performing a hydrogen plasma annealing process after the etch-back process, silicon atoms can locally migrate around the surface of the fin active region FA, and thus the facet surface of the cap layer 120D can become the curved surface 120FC.

[0064] Figure 9 is a layout view of the integrated circuit device 200 according to some embodiments. Figure 10 is a cross-sectional view of the integrated circuit device 200 along the line X2-X2' in Figure 9 Figure 11 is a cross-sectional view of the integrated circuit device 200 along the line Y2-Y2' in Figure 9

[0065] Referring to Figure 9 to Figure 11 , the substrate 110 includes a first active region RX1, a second active region RX2, and a deep trench region DTA. The first active region RX1 and the second active region RX2 can be spaced apart from each other, with the deep trench region DTA between the first active region RX1 and the second active region RX2.

[0066] According to some embodiments, the first active region RX1 can be an active region for a PMOS transistor, and the second active region RX2 can be an active region for an NMOS transistor. According to some embodiments, the first active region RX1 can be an active region for an NMOS transistor having a first threshold voltage, and the second active region RX2 can be an active region for an NMOS transistor having a second threshold voltage different from the first threshold voltage.

[0067] According to some embodiments, the first active region RX1, the second active region RX2, and the deep trench region DTA can constitute a standard cell that performs a logic function. The standard cell can include various types of logic cells including a plurality of circuit devices such as transistors and registers. The logic cells may, for example, constitute AND, NAND, OR, NOR, XOR, XNOR, inverter (INV), adder (ADD), buffer (BUF), delay (DLY), filter (FIL), multiplexer (MXT / MXIT), or / and / inverter (OAI), and / or (AO), and / or / inverter (AOI), D flip-flop, reset flip-flop, master-slave flip-flop, and latch.

[0068] ​​The plurality of fin-type active regions FA can be disposed on the first active region RX1 to protrude from the second upper surface 110F2 of the substrate 110, and each of the plurality of fin-type active regions FA can extend in the first direction (i.e., the X direction). The plurality of fin-type active regions FA can be disposed on the second active region RX2 to protrude from the second upper surface 110F2 of the substrate 110, and each of the plurality of fin-type active regions FA can extend in the first direction (i.e., the X direction). Two sidewalls of the plurality of fin-type active regions FA can be covered by the isolation layer 114. In the deep trench region DTA, a deep trench 116T can be formed to have a certain depth from the second upper surface 110F2 of the substrate 110, and a deep trench isolation layer 11116 can fill the inside of the deep trench 116T.

[0069] The gate structures GS can each extend in the second direction (i.e., the Y direction) to intersect the plurality of fin-type active regions FA on the first active region RX1 and the second active region RX2. Detailed descriptions of the gate structures GS can be referred to the descriptions given above with reference to FIGS. 1A to 1C. Figure 1 to Figure 4 The descriptions given above.

[0070] The plurality of fin-type active regions FA intersecting the first active region RX1 can include a first fin-type active region F1 and a second fin-type active region F2 disposed side by side. The second fin-type active region F2 can include a first sidewall FAS1 facing the first fin-type active region F1, and a second sidewall FAS2 opposite the first sidewall FAS1.

[0071] The cover layer 120 can be disposed on the first fin-type active region F1 and the second fin-type active region F2. The cover layer 120 can have a shape that is asymmetric about each center of the first fin-type active region F1 and the second fin-type active region F2 in the second direction (i.e., the Y direction). For example, the cover layer 120 on the second fin-type active region F2 can include a first portion P1 disposed on the first sidewall FAS1 of the second fin-type active region F2, and a second portion P2 disposed on the second sidewall FAS2 of the second fin-type active region F2. The second portion P2 of the cover layer 120 can have a bottom surface higher than the first portion P1. For example, the bottom surface 120L2 of the second portion P2 can be disposed on the same second level LV2 as an upper surface of the deep trench isolation layer 116, and the bottom surface 120L1 of the first portion P1 can be disposed on a third level LV3 lower than the upper surface of the deep trench isolation layer 116. In other words, an upper surface of a portion of the insulating liner 114L on the second sidewall FAS2 can be disposed at the second level LV2, and an upper surface of a portion of the insulating liner 114L on the first sidewall FAS1 can be disposed at the third level LV3 lower than the second level LV2.

[0072] The cap layer 120 can be formed on the fin-type active region FA of both the first active region RX1 and the second active region RX2, or can be formed on the fin-type active region FA of one of the first active region RX1 and the second active region RX2.

[0073] The first contact 172 can be arranged to be connected to the source / drain region 140, and the second contact 174 can be arranged to be connected to the gate structure GS. The first contact 172 and the second contact 174 can include at least one of titanium nitride (TiN), titanium (Ti), tantalum nitride (TaN), tantalum (Ta), ruthenium (Ru), ruthenium nitride (RuN), tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), and alloys thereof.

[0074] Figure 12A to Figure 20B is a cross-sectional view illustrating a method of manufacturing the integrated circuit device 200 according to some embodiments. In detail, Figure 12A 、 Figure 13A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A and Figure 20A are cross-sectional views corresponding to the line X2-X2’ of Figure 9 , and Figure 12B 、 Figure 13B 、 Figure 14 、 Figure 15 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B and Figure 20B are cross-sectional views corresponding to the line Y2-Y2’ of Figure 9 .

[0075] Referring to Figure 12A and Figure 12B , the first semiconductor layer 112 can be formed using the first semiconductor material on the first upper surface 110F1 of the substrate 110. By using the first upper surface 110F1 of the substrate 110 as a seed layer, the first semiconductor layer 112 can be formed according to an epitaxial process. The epitaxial process can be a vapor phase epitaxy (VPE) process, a chemical vapor deposition (CVD) process (e.g., ultra-high vacuum CVD (UHV-CVD)), a molecular beam epitaxy process, or a combination thereof. In the epitaxial process, the first semiconductor layer 112 can be formed at a process pressure of about 50 to about 600 Torr by using a liquid or gaseous precursor as a precursor required for forming the first semiconductor layer 112.

[0076] Accordingly, the mask pattern 210 can be formed on the first semiconductor layer 112.

[0077] The mask pattern 210 can include a pad oxide layer 212 and a mask material layer 214. For example, the pad oxide layer 212 can include an oxide obtained by thermally oxidizing a surface of the first semiconductor layer 112. The mask material layer 214 can include a silicon nitride layer, a silicon oxynitride layer, a spin-on glass (SOG) layer, a spin-on hard mask (SOH) layer, an amorphous carbon layer, a photoresist layer, or a combination thereof.

[0078] Referring to Figure 13A and Figure 13B The isolation trenches 114T can be formed by removing the first semiconductor layer 112 and the substrate 110 by a certain thickness using the mask pattern 210 as an etching mask, forming a plurality of fin-type active regions FA. The plurality of fin-type active regions FA can protrude from the second upper surface 110F2 of the substrate 110 in the third direction (i.e., the Z direction), and can each extend in the first direction (i.e., the X direction).

[0079] Referring to Figure 14 The isolation layer 114 including the insulating liner layer 114L and the insulating fill layer 114F can be formed on the substrate 110.

[0080] The isolation layer 114 can be formed by first forming the insulating liner layer 114L on the sidewalls of the isolation trenches 114T, then forming the insulating fill layer 114F on the insulating liner layer 114L to fill the spaces between the plurality of fin-type active regions FA, and removing respective upper portions of the insulating liner layer 114L and the insulating fill layer 114F, thereby exposing upper surfaces of the plurality of fin-type active regions FA.

[0081] According to some embodiments, the insulating liner layer 114L can include an oxide layer formed by an oxidation process of oxidizing surfaces of the plurality of fin-type active regions FA, and the process of oxidizing the surfaces of the plurality of fin-type active regions FA can be, for example, an in-situ steam generation (ISSG) process, a thermal oxidation process, a UV oxidation process, or an O2 plasma oxidation process. The insulating liner layer 114L can have a thickness of about to about but the inventive concept is not limited thereto.

[0082] According to some embodiments, the insulating fill layer 114F can include an oxide layer formed by a flowable chemical vapor deposition (FCVD) process or a spin-on process. For example, the insulating fill layer 114F can include, but is not limited to, flowable fluorinated silicon glass (FSG), undoped silicon glass (USG), borophosphosilicate glass (BPSG), phosphosilicate glass (PSG), flowable oxide (FOX), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), or TOSZ.

[0083] Thereafter, a deep trench 116T can be formed by removing a portion of the spacer layer 114 and a portion of the substrate 110 in the deep trench region DTA, and a deep trench spacer layer 116 can be formed by filling an insulating material into the deep trench 116T. A bottom surface level LV0 of the deep trench spacer layer 116 can be lower than a bottom surface level LV1 of the spacer layer 114.

[0084] Referring to Figure 15 A respective upper portion of the spacer layer 114 and the deep trench spacer layer 116 can be removed by a recess process by a certain height. Accordingly, an upper surface of the deep trench spacer layer 116 can be on a second level LV2 lower than an upper surface of each fin-type active region FA, and a first sidewall FAS1 and a second sidewall FAS2 of each fin-type active region FA can be exposed.

[0085] A portion of the spacer layer 114 between the first fin-type active region Fl and the second fin-type active region F2 can be disposed at a third level LV3 (e.g., a level of the upper surface of the deep trench spacer layer 116) lower than the second level LV2, while a portion of the spacer layer 114 between the first fin-type active region Fl and the deep trench spacer layer 116 and a portion of the spacer layer 114 between the second fin-type active region F2 and the deep trench spacer layer 116 can be disposed at the same level (e.g., a level of the upper surface of the deep trench spacer layer 116) as the second level LV2. Accordingly, a portion of the insulating liner 114L between the first fin-type active region Fl and the second fin-type active region F2 can be disposed at the third level LV3 lower than the second level LV2 of the upper surface of the deep trench spacer layer 116, while a portion of the insulating liner 114L between the first fin-type active region Fl and the deep trench spacer layer 116 and a portion of the insulating liner 114L between the second fin-type active region F2 and the deep trench spacer layer 116 can be disposed at the same level as the second level LV2 of the upper surface of the deep trench spacer layer 116.

[0086] Referring to Figure 16A and Figure 16B A capping layer 120 can be formed on the exposed surfaces of the fin-type active regions FA.

[0087] According to some embodiments, the capping layer 120 can be formed using an epitaxy process and a subsequent etch-back process. The subsequent etch-back process can be performed by using an etchant gas including at least one of germane (GeH4), chlorine (CI2), and hydrogen chloride (HC1). According to some embodiments, the capping layer 120 can be formed using an epitaxy process and subsequent first and second etch-back processes.

[0088] According to some embodiments, the epitaxy process can be performed by using at least one of silane, disilane, dichlorosilane, trichlorosilane, and diisopropylaminosilane (DIPAS) as a material, by a VPE process, a CVD process such as a UHV-CVD process, a molecular beam epitaxy process, or a combination thereof. The epitaxy process can be performed at a process temperature of about 300°C to about 950°C and a pressure of about 10 to 600 Torr.

[0089] According to some embodiments, the etch-back process can be performed using an etchant gas including at least one of germane (GeH4), chlorine (Cl2), and hydrogen chloride (HCl). The first etch-back process can be performed using a first etchant gas including germane (GeH4) and hydrogen chloride (HCl), and the second etch-back process can be performed using a second etchant gas including hydrogen chloride (HCl). At least one of the first etch-back process and the second etch-back process can be performed at a process temperature of about 300°C to about 950°C and a pressure of about 10 to 600 Torr.

[0090] Referring to Figure 17A and Figure 17B A sacrificial gate structure DGS extending in the second direction is formed on the fin-type active region FA. According to some embodiments, the sacrificial gate insulating layer pattern 232, the sacrificial gate 234, and the hard mask pattern 236 can be sequentially stacked on the substrate 110, and then an insulating layer (not shown) covering the hard mask pattern 236, the sacrificial gate 234, and the sacrificial gate insulating layer pattern 232 can be formed using an atomic layer deposition (ALD) process or a CVD process, and then an anisotropic etching process can be performed on the insulating layer, thereby forming a gate spacer 138 on the respective sidewalls of the hard mask pattern 236, the sacrificial gate 234, and the sacrificial gate insulating layer pattern 232. The gate spacer 138 can include, but is not limited to, silicon nitride.

[0091] Referring to Figure 18A and Figure 18B The recessed region 140R can be formed by etching portions of the fin-type active region FA on both sides of the sacrificial gate structure DGS and the gate spacer 138. According to some embodiments, the process of forming the recessed region 140R can include a dry etching process, a wet etching process, or a combination thereof.

[0092] Thereafter, the source / drain region 140 can be formed by growing a semiconductor layer (not shown) on the inner wall of each recessed region 140R.

[0093] The semiconductor layer can be formed according to an epitaxy process by using the sidewall of each fin-shaped active region FA exposed on the inner wall of the recessed region 140R as a seed layer. The epitaxy process can be a VPE process, a CVD process such as a UHV-CVD process, a molecular beam epitaxy process, or a combination thereof.

[0094] Thereafter, an insulating layer (not shown) covering the sacrificial gate structure DGS and the source / drain regions 140 can be formed on the substrate 110 and can be planarized until the upper surface of the hard mask pattern 236 is exposed, thereby forming the gate-to-gate insulating layer 150.

[0095] Referring to Figure 19A and Figure 19B , the gate space GSS can be formed by removing the hard mask pattern 236 Figure 18A , the sacrificial gate 234 Figure 18A , and the sacrificial gate insulating layer pattern 232 Figure 18A .

[0096] According to some embodiments, the gate space GSS can be formed by removing the hard mask pattern 236 Figure 18A , the sacrificial gate 234 Figure 18A , and the sacrificial gate insulating layer pattern 232 Figure 18A using a wet etching process. The wet etching process can be performed using an etchant including, for example, HNO3, diluted hydrogen fluoride (DHF), NH4OH, tetramethylammonium hydroxide (TMAH), KOH, or a combination thereof. During the removal process, the cap layer 120 can be exposed via the gate space GSS, and the fin-shaped active regions FA can be covered by the cap layer 120 and can be prevented from being oxidized or damaged.

[0097] Referring to Figure 20A and Figure 20B , the gate insulating layer 134 can be formed on the pair of gate spacers 138 and the inner surface of the cap layer 120, i.e., on the inner wall of the gate space GSS of Figure 19A . During the formation of the gate insulating layer 134, the cap layer 120 can be exposed via the gate space GSS, and the fin-shaped active regions FA can be covered by the cap layer 120 and can be prevented from being oxidized or damaged.

[0098] Thereafter, a conductive layer (not shown) filling the gate space GSS can be formed on the gate insulating layer 134, and then the gate electrode 132 can be formed by etching back an upper portion of the conductive layer. Then, an insulating layer (not shown) filling a space between the pair of gate spacers 138 can be formed on the gate electrode 132 and the inter-gate insulating upper layer 150, and then an upper portion of the insulating layer can be removed until an upper surface of the inter-gate insulating layer 150 or the gate spacers 138 is exposed, thereby forming the gate cover layer 136. Thus, the gate structure GS including the gate electrode 132, the gate insulating layer 134, the gate cover layer 136, and the gate spacers 138 can be formed.

[0099] Then, an interlayer insulating layer (not shown) can be formed on the gate structure GS and the inter-gate insulating layer 150. Although not shown in the figure, a contact hole (not shown) exposing an upper surface of the source / drain region 140 and an upper surface of the gate electrode 132 can be formed by penetrating the interlayer insulating layer and the first contact 172 and the first contact 172. A second contact 174 connected to the source / drain region 140 and the gate electrode 132, respectively, can be formed by filling the contact hole with a conductive material.

[0100] In this way, the integrated circuit device 200 is completed. According to the manufacturing method described above, the cover layer 120 can be formed on the surface of the fin-type active region FA by an epitaxial process and a subsequent etching back process. Since the cover layer 120 can prevent the surface of the fin-type active region FA from being oxidized or damaged during a process of removing the sacrificial gate structure or during a process of forming the gate insulating layer 134, an increase in the interface defect density can be prevented. The occurrence of gate insulating TDDB of the gate insulating layer 134 can be prevented or TDDB can be prevented, and the integrated circuit device 200 can have high reliability.

[0101] Additionally or alternatively, after the cover layer 120 is formed, a plasma nitridation process can be further performed on the respective exposed surfaces of the cover layer 120 and the isolation layer 114. The plasma nitridation process can be performed using, for example, N2, NH3, N2H2, or N2H4. Due to the plasma nitridation process, a portion of the cover layer 120 around the surface and a portion of the isolation layer 114 around the surface can be converted into silicon nitride, and thus the interface layer 160 can be further formed. In this way, the integrated circuit device 100C can be manufactured. Figure 7 Since the interface layer 160 has a relatively strong silicon-nitrogen bond, the surface of the fin-type active region FA can be prevented from being oxidized or damaged in a subsequent process of removing the sacrificial gate structure DGS or in a subsequent process of forming the gate insulating layer 134.

[0102] Additionally or alternatively, after the formation of the cap layer 120, a hydrogen plasma anneal process can be further performed on the respective exposed surfaces of the cap layer 120 and the isolation layer 114. Due to the hydrogen plasma anneal process, silicon atoms can locally migrate around the surface of the fin-type active region FA, and thus the facet surface of the cap layer 120D can change to a curved surface 120FC. In this way, the integrated circuit device 100D of Figure 8 FIG. 1 can be manufactured.

[0103] While the present concept has been particularly shown and described with reference to examples of embodiments of the present concept, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit of the appended claims.

Claims

1. An integrated circuit device, comprising: a fin-type active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and comprising a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active region, the isolation layer comprising an insulating liner arranged on the lower portion of the sidewall of the fin-type active region and an insulating fill layer on the insulating liner; a cap layer surrounding an upper surface and an upper portion of the sidewall of the fin-type active region, comprising a second semiconductor material different from the first semiconductor material, wherein the cap layer comprises an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall, the facet surface being inclined at a first angle with respect to the upper surface of the substrate, and the first angle being between 30° and 60°; and a gate structure arranged on the cap layer and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction, wherein the cap layer has a first thickness on the upper surface of the fin-type active region, wherein the cap layer has a second thickness along the sidewall of the fin-type active region, and wherein the second thickness is smaller than the first thickness, wherein a junction between the upper surface of the fin-type active region and the sidewall of the fin-type active region is rounded, and a profile of the junction is different from a profile of the facet surface.

2. The integrated circuit device of claim 1, wherein, an upper surface of the insulating liner contacts a bottom surface of the cap layer, and wherein the bottom surface of the cap layer and an upper surface of the isolation layer are equidistant from the upper surface of the substrate.

3. The integrated circuit device of claim 1, wherein, the fin-type active region comprises silicon germanium, and wherein the cap layer comprises silicon.

4. The integrated circuit device of claim 1, wherein, the fin-type active region comprises a surface region and an inner region, the surface region being at a distance from the sidewall of the fin-type active region smaller than a first distance, the inner region being at a distance from the sidewall of the fin-type active region larger than the first distance, and wherein the surface region has a first germanium content, and the inner region has a second germanium content smaller than the first germanium content.

5. The integrated circuit device of claim 4, wherein the surface region of the fin-type active region has a first bandgap energy, wherein the inner region of the fin-type active region has a second bandgap energy, wherein the cap layer has a third bandgap energy, and wherein the third bandgap energy is larger than the second bandgap energy, and the second bandgap energy is larger than the first bandgap energy.

6. The integrated circuit device of claim 1, further comprising: an interface layer arranged between the cap layer and the gate structure, and the interface layer comprises the second semiconductor material, the second semiconductor material comprising a first concentration of nitrogen.

7. An integrated circuit device, comprising: a fin-type active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and comprising silicon germanium; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active region, the isolation layer comprising an insulating liner arranged on the lower portion of the sidewall of the fin-type active region and an insulating fill layer on the insulating liner; a cap layer surrounding an upper surface and a sidewall of the fin-shaped active region, the cap layer comprising silicon, and the cap layer comprising an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the cap layer and extending in a second direction parallel to an upper surface of the substrate and perpendicular to the first direction, wherein, on the sidewall of the fin-shaped active region, a bottom surface of the cap layer contacts an upper surface of the insulating liner, wherein the fin-shaped active region comprises a surface region and an inner region, the surface region being at a distance from the sidewall of the fin-shaped active region that is smaller than a first distance, the inner region being at a distance from the sidewall of the fin-shaped active region that is larger than the first distance, and wherein the surface region has a first germanium content and the inner region has a second germanium content that is smaller than the first germanium content.

8. The integrated circuit device of claim 7, wherein, an upper portion of the sidewall of the fin-shaped active region contacts the cap layer, and a lower portion of the sidewall of the fin-shaped active region contacts the insulating liner.

9. The integrated circuit device of claim 7, wherein, the facet surface is inclined with respect to the upper surface of the substrate at a first angle between 30° and 60°, wherein the cap layer has a first thickness on the upper surface of the fin-shaped active region, and wherein the cap layer has a second thickness at an edge of the facet surface that is smaller than the first thickness.

10. An integrated circuit device, comprising: a fin-shaped active region protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and comprising a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-shaped active region; a cap layer surrounding an upper surface and a sidewall of the fin-shaped active region, the cap layer comprising a second semiconductor material different from the first semiconductor material, wherein the cap layer comprises an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall, wherein the cap layer has a first thickness on the upper surface of the fin-shaped active region, wherein the cap layer has a second thickness along the sidewall of the fin-shaped active region, and wherein the second thickness is smaller than the first thickness; and a gate structure arranged on the cap layer and extending in a second direction parallel to the upper surface of the substrate and perpendicular to the first direction.

11. The integrated circuit device of claim 10, wherein, the isolation layer comprises an insulating liner arranged on the lower portion of the sidewall of the fin-shaped active region and an insulating fill layer on the insulating liner.

12. The integrated circuit device of claim 10, wherein, the facet surface is inclined with respect to the upper surface of the substrate at a first angle between 30° and 60°.

13. The integrated circuit device of claim 11, wherein, an upper surface of the insulating liner contacts a bottom surface of the cap layer, and the bottom surface of the cap layer is at a distance from the upper surface of the substrate that is as far as the upper surface of the isolation layer from the upper surface of the substrate.

14. The integrated circuit device of claim 10, wherein, the fin-shaped active region comprises silicon germanium, and wherein the cap layer comprises silicon.

15. The integrated circuit device of claim 10, wherein, the fin-shaped active region comprises a surface region and an inner region, the surface region being at a distance from the sidewall of the fin-shaped active region that is smaller than a first distance, the inner region being at a distance from the sidewall of the fin-shaped active region that is larger than the first distance, and the surface region has a first germanium content and the inner region has a second germanium content that is smaller than the first germanium content. wherein the surface region has a first germanium content and the interior region has a second germanium content that is less than the first germanium content.

16. The integrated circuit device of claim 15, wherein, The surface region of the fin-type active region has a first bandgap energy, wherein the interior region of the fin-type active region has a second bandgap energy, wherein the cap layer has a third bandgap energy, and wherein the third bandgap energy is greater than the second bandgap energy, and the second bandgap energy is greater than the first bandgap energy.

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