An ultra-low on-resistance fin-type heterojunction field effect transistor

Abstract

The application provides an ultra-low on-resistance fin-type heterojunction field effect transistor, comprising: a first conductive type substrate; a drain metal layer; a first conductive type drift layer; a first conductive type first conductive layer; the side of the first conductive type first conductive layer, which is away from the first conductive type drift layer, comprises at least one protrusion; a second conductive type first semiconductor layer; a second conductive type second semiconductor layer; a gate metal layer; a first conductive type second conductive layer; a passivation layer; and a source metal layer. The application utilizes the heterojunction interface electron accumulation effect, and on the basis of the super-junction structure, the on-resistance of the device is further reduced, and the power figure of merit is obviously improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more particularly to an ultra-low on-resistance fin heterojunction field-effect transistor. Background Technology

[0002] In Ga2O3 FinFETs, the introduction of heterogeneous P-type materials to form a superjunction structure results in lower on-resistance due to the higher drift region doping concentration. However, the low electron mobility of Ga2O3 means that even with increased doping concentration, the drift region resistance of Ga2O3 FinFETs remains relatively high. Furthermore, the critical breakdown field strength of the introduced heterogeneous P-type material is generally lower than that of Ga2O3, effectively limiting the device's breakdown voltage and preventing the efficient utilization of Ga2O3's high critical breakdown field. Therefore, the high breakdown voltage cannot compensate for the disadvantage in on-resistance in terms of power figure of merit, making the low electron mobility disadvantage of Ga2O3 more pronounced. Even though Ga2O3 FinFETs have a higher breakdown voltage than GaN FinFETs, the inferior on-resistance prevents an improvement in the device's power figure of merit, failing to fully utilize the superior performance of Ga2O3. Therefore, further reducing the on-resistance of the device is of great significance for vertical superjunction Ga2O3 devices. Summary of the Invention

[0003] In view of the problems existing in the prior art, the present invention proposes an ultra-low on-resistance fin heterojunction field-effect transistor, which mainly solves the problem that the on-resistance of the existing gallium oxide vertical superjunction field-effect transistor is still relatively high, thus affecting the device performance and application.

[0004] To achieve the above and other objectives, the technical solution adopted by the present invention is as follows.

[0005] This application provides an ultra-low on-resistance fin heterojunction field-effect transistor, comprising: a first conductivity type substrate; a drain metal layer disposed on one side of the first conductivity type substrate; a first conductivity type drift layer disposed on the side of the first conductivity type substrate opposite to the drain metal layer; a first conductivity type first conductive layer disposed on the side of the first conductivity type drift layer opposite to the first conductivity type substrate; the side of the first conductivity type first conductive layer opposite to the first conductivity type drift layer includes at least one protrusion; a second conductivity type first semiconductor layer disposed on both sides of the first conductivity type drift layer and extending to the side of the first conductivity type first conductive layer; a second conductivity type second... A semiconductor layer is disposed on both sides of the protrusion and covers the first semiconductor layer of the second conductivity type, wherein the first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type form heterojunction interfaces at their contact surfaces with the first conductive layer of the first conductivity type and the drift layer of the first conductivity type, respectively; a gate metal layer is disposed on the second semiconductor layer of the second conductivity type; a second conductive layer of the first conductivity type is disposed on the side of the protrusion away from the first conductive layer of the first conductivity type; a passivation layer covers the second semiconductor layer of the second conductivity type and the gate metal layer; and a source metal layer is disposed on the side of the second conductive layer of the first conductivity type away from the protrusion.

[0006] In one embodiment of this application, the ultra-low on-resistance fin heterojunction field-effect transistor further includes an unintentionally doped semiconductor layer disposed between the first conductivity type drift layer and the first conductivity type substrate, or disposed between the second conductivity type first semiconductor layer and the first conductivity type substrate.

[0007] In one embodiment of this application, the first conductivity type substrate is in ohmic contact with the drain metal layer, and the first conductivity type second conductivity layer is in ohmic contact with the source metal layer. The doping concentration of both the first conductivity type substrate and the first conductivity type second conductivity layer is 10. 18 cm -3 Up to 10 19 cm -3 between.

[0008] In one embodiment of this application, the doping concentration of the first conductive layer of the first conductivity type is 10. 15 cm -3 Up to 10 16 cm -3 between.

[0009] In one embodiment of this application, the doping concentration of the unintentionally doped semiconductor layer is 10. 14 cm -3 Up to 10 15 cm-3 between.

[0010] In one embodiment of this application, the first conductivity type drift layer and the second conductivity type first semiconductor layer have the same total width and doping concentration.

[0011] In one embodiment of this application, the second semiconductor layer of the second conductivity type includes a first sublayer and a second sublayer, wherein the doping concentration of the first sublayer is not lower than that of the first semiconductor layer of the second conductivity type, and the doping concentration of the second sublayer is greater than that of the first sublayer.

[0012] In one embodiment of this application, the doping concentration of the first conductivity type drift layer is higher than that of the first conductivity type first conductivity layer.

[0013] In one embodiment of this application, the first conductivity type substrate, the unintentionally doped semiconductor layer, the first conductivity type drift layer, the first conductivity type first conductive layer, and the first conductivity type second conductive layer are all made of β-Ga2O3 material, and are all N-type doped.

[0014] In one embodiment of this application, both the first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type are made of nickel oxide and are both P-type doped.

[0015] As described above, the ultra-low on-resistance fin-type heterojunction field-effect transistor proposed in this invention has the following beneficial effects.

[0016] This application forms a heterojunction interface at the contact surfaces with the first conductive layer and the drift layer of the first conductive type, respectively, using the first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type. Based on the existing superjunction structure, it utilizes the electron accumulation effect of the heterojunction interface to form a conductive channel not only in the fin-shaped channel region formed at the protrusion position, but also in the drift region of the superjunction structure, which can further reduce the on-resistance of the device and improve the performance of the device. Attached Figure Description

[0017] Figure 1 This is a cross-sectional view of a fin-type heterojunction field-effect transistor with ultra-low on-resistance according to an embodiment of this application.

[0018] Figure 2 This is a cross-sectional view of a fin heterojunction field-effect transistor with ultra-low on-resistance according to another embodiment of this application.

[0019] Figure 3 This is a cross-sectional structural diagram of a fin-type heterojunction field-effect transistor including multiple protrusions in one embodiment of this application.

[0020] Figure 4 This is a cross-sectional view of a fin heterojunction field-effect transistor with ultra-low on-resistance according to another embodiment of this application.

[0021] Figure 5 This is a comparison chart of the electrical performance simulation results of the transistor in the embodiment of this application and the existing Ga2O3 SJ FinFET.

[0022] Explanation of icon numbers:

[0023] 1-Drain metal layer; 2-Substrate of first conductivity type; 3-Unintentionally doped semiconductor layer; 4-Drift layer of first conductivity type; 5-First semiconductor layer of second conductivity type; 6-First conductive layer of first conductivity type; 7-First sub-layer; 8-Second sub-layer; 9-Gate metal layer; 10-Passivation layer; 11-Second conductive layer of first conductivity type; 12-Source metal layer. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0025] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] Please see Figure 1 , Figure 1This is a cross-sectional view of a fin heterojunction field-effect transistor with ultra-low on-resistance according to an embodiment of this application. The fin heterojunction field-effect transistor includes: a first conductivity type substrate 2; a drain metal layer 1 disposed on one side of the first conductivity type substrate 2; a first conductivity type drift layer 4 disposed on the side of the first conductivity type substrate 2 away from the drain metal layer 1; a first conductivity type first conductive layer 6 disposed on the side of the first conductivity type drift layer 4 away from the first conductivity type substrate 2; the side of the first conductivity type first conductive layer 6 away from the first conductivity type drift layer 4 includes at least one protrusion; a second conductivity type first semiconductor layer 5 disposed on both sides of the first conductivity type drift layer 4 and extending to the side of the first conductivity type first conductive layer 6; and a second conductivity type second semiconductor layer. On both sides of the protrusion, a first semiconductor layer 5 of the second conductivity type is covered, wherein the first semiconductor layer 5 of the second conductivity type and the second semiconductor layer of the second conductivity type form a heterojunction interface at the contact surface with the first conductive layer 6 of the first conductivity type and the drift layer 4 of the first conductivity type, respectively; a gate metal layer 9 is disposed on the second semiconductor layer of the second conductivity type; a second conductive layer 11 of the first conductivity type is disposed on the side of the protrusion away from the first conductive layer 4; a passivation layer 10 covers the second semiconductor layer of the second conductivity type and the gate metal layer 9; and a source metal layer 12 is disposed on the side of the second conductive layer 11 of the first conductivity type away from the protrusion.

[0027] In one embodiment, the passivation layer 10 may be SiO2, which serves as insulation and protection.

[0028] In one embodiment, an unintentionally doped semiconductor layer 3 may be disposed between the first conductivity type drift layer 4 and the first conductivity type substrate 2. The unintentionally doped semiconductor layer 3 employs unintentional doping and has an extremely low doping concentration, typically around 10⁻⁶. 14 cm -3 Up to 10 15 cm -3 between.

[0029] Please see Figure 2 , Figure 2 This is a cross-sectional view of a fin-type heterojunction field-effect transistor with ultra-low on-resistance according to another embodiment of this application. Figure 2 As shown, an unintentionally doped semiconductor layer 3 can also be provided between the first semiconductor layer 5 of the second conductivity type and the substrate 2 of the first conductivity type. By separating the drift region of the first conductivity type from the substrate 2 of the first conductivity type through the unintentionally doped semiconductor layer 3, the process complexity can be effectively reduced.

[0030] In one embodiment, the first conductivity type substrate 2, the unintentionally doped semiconductor layer 3, the first conductivity type drift layer 4, the first conductivity type first conductive layer 6, and the first conductivity type second conductive layer 11 are all made of β-Ga2O3 material and are all N-type doped.

[0031] In one embodiment, both the first semiconductor layer 5 of the second conductivity type and the second semiconductor layer of the second conductivity type are made of nickel oxide and are both P-type doped.

[0032] In one embodiment, the first conductivity type substrate 2 is in ohmic contact with the drain metal layer 1, and the first conductivity type second conductivity layer 11 is in ohmic contact with the source metal layer 12. The doping concentration of both the first conductivity type substrate 2 and the first conductivity type second conductivity layer 11 is 10. 18 cm -3 Up to 10 19 cm -3 between.

[0033] In one embodiment, the doping concentration of the first conductive layer 6 of the first conductivity type is 10. 15 cm -3 Up to 10 16 cm -3 between.

[0034] In one embodiment, the first conductivity type drift layer 4 and the second conductivity type first semiconductor layer 5 have the same total width and doping concentration. The doping concentration of the first conductivity type drift layer 4 is higher than that of the first conductivity type first conductive layer 6, which can effectively reduce the on-resistance of the device.

[0035] In one embodiment, the second semiconductor layer of the second conductivity type includes a first sublayer 7 and a second sublayer 8, wherein the doping concentration of the first sublayer 7 is not lower than that of the first semiconductor layer 5 of the second conductivity type, which can prevent the depletion effect on the channel from being too weak. The doping concentration of the second sublayer 8 is greater than that of the first sublayer 7, which can prevent premature surface breakdown.

[0036] Please see Figure 3 , Figure 3This is a cross-sectional schematic diagram of a fin-type heterojunction field-effect transistor including multiple protrusions in one embodiment of this application. Multiple protrusions can be formed on the side of the first conductive layer 6 of the first conductivity type away from the drift layer 4 of the first conductivity type. Here, only two protrusions forming two fin channels are used as an example for illustration. The number of protrusions is not limited to two; multiple protrusions arranged side-by-side can be provided according to actual device requirements, and this is not limited. The fin channels formed by the two protrusions are located on a superjunction structure, and the width and doping concentration of the two protrusions are exactly the same. By increasing the number of protrusions, the number of effective carrier channels is increased, which can reduce the on-resistance of the device.

[0037] Please see Figure 4 , Figure 4 This is a schematic cross-sectional view of a fin-type heterojunction field-effect transistor with ultra-low on-resistance according to another embodiment of this application. Figure 1 Compared to the structure shown, the difference lies in merging the first sublayer 7 and the second sublayer 8 into a single layer structure, that is, the first sublayer 7 and the second sublayer 8 use the same doping concentration, which can reduce the complexity of the process.

[0038] Please see Figure 5 , Figure 5 This is a comparison chart of the electrical performance simulation results of the transistor in the embodiment of this application and the existing Ga2O3 SJ FinFET. Figure 5 The present invention is a double-fin heterojunction field-effect transistor with two protrusions. As can be seen from the figure, the transistor of the present application embodiment has a significantly reduced on-resistance compared to the existing Ga2O3 SJ FinFET.

[0039] Based on the technical solutions of the above embodiments of this application, the gate oxide dielectric layer is removed from the existing gallium oxide superjunction fin field-effect transistor (Ga2O3 SJ FinFET). Utilizing the electron accumulation effect of the NiO / Ga2O3 heterojunction under a certain forward bias, surface conductive channels are generated not only in the fin channel region but also in the superjunction drift region. In contrast, conventional Ga2O3 SJ FinFETs not only lack surface conductive channels at the superjunction interface but also have a depletion region. This allows the on-resistance of the present invention (SJ Fin-HJFET) to be further significantly reduced even with the adoption of a superjunction structure, thereby significantly improving the power figure of merit of the device.

[0040] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An ultra-low on-resistance fin-type heterojunction field-effect transistor, characterized in that, include: First conductivity type substrate; A drain metal layer is disposed on one side of the substrate of the first conductivity type; A first conductivity type drift layer is disposed on the side of the first conductivity type substrate away from the drain metal layer; A first conductive layer of a first conductivity type is disposed on the side of the first conductivity type drift layer opposite to the first conductivity type substrate; the side of the first conductive layer opposite to the first conductivity type drift layer includes at least one protrusion. A first semiconductor layer of a second conductivity type is disposed on both sides of a drift layer of the first conductivity type and extends to the side of the first conductivity type first conductive layer. A second semiconductor layer of a second conductivity type is disposed on both sides of the protrusion and covers the first semiconductor layer of the second conductivity type. The first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type respectively form a heterojunction interface at the contact surface with the first conductive layer of the first conductivity type and the first drift layer of the first conductivity type. A gate metal layer is disposed on a second semiconductor layer of the second conductivity type; A second conductive layer of a first conductivity type is disposed on the side of the protrusion away from the first conductivity type drift layer; A passivation layer that covers the second semiconductor layer of the second conductivity type and the gate metal layer; A source metal layer is disposed on the side of the second conductive layer of the first conductivity type away from the protrusion; The doping concentration of the drift layer of the first conductivity type is higher than that of the first conductivity type of the first conductive layer.

2. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 1, characterized in that, It also includes an unintentionally doped semiconductor layer disposed between the first conductivity type drift layer and the first conductivity type substrate, or disposed between the second conductivity type first semiconductor layer and the first conductivity type substrate.

3. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 1, characterized in that, The first conductivity type substrate is in ohmic contact with the drain metal layer, and the first conductivity type second conductivity layer is in ohmic contact with the source metal layer. The doping concentration of both the first conductivity type substrate and the first conductivity type second conductivity layer is 10. 18 cm -3 Up to 10 19 cm -3 between.

4. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 1, characterized in that, The doping concentration of the first conductive layer of the first conductivity type is 10. 15 cm -3 Up to 10 16 cm -3 between.

5. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 2, characterized in that, The unintentionally doped semiconductor layer has a doping concentration of 10. 14 cm -3 Up to 10 15 cm -3 between.

6. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 1, characterized in that, The first conductivity type drift layer and the second conductivity type first semiconductor layer have the same total width and doping concentration.

7. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 1, characterized in that, The second semiconductor layer of the second conductivity type includes a first sublayer and a second sublayer, wherein the doping concentration of the first sublayer is not lower than that of the first semiconductor layer of the second conductivity type, and the doping concentration of the second sublayer is greater than that of the first sublayer.

8. The ultra-low on-resistance fin heterojunction field-effect transistor according to claim 2 or 5, characterized in that, The first conductivity type substrate, the unintentionally doped semiconductor layer, the first conductivity type drift layer, the first conductivity type first conductive layer, and the first conductivity type second conductive layer are all made of β-Ga2O3 material, and are all N-type doped.

9. The ultra-low on-resistance fin heterojunction field-effect transistor according to any one of claims 1-7, characterized in that, Both the first semiconductor layer of the second conductivity type and the second semiconductor layer of the second conductivity type are made of nickel oxide and are both P-type doped.

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