A high-efficiency multi-port parallel shared cache management system for switches

Abstract

This invention proposes a high-efficiency multi-port parallel shared cache management system for switches. It supports the formation of an SRAM array from m SRAM controllers, with unified management and allocation of page base addresses to achieve shared cache. It fully utilizes multiple read / write ports of multiple SRAMs, enabling the switch's input / output ports to access multiple SRAMs in parallel. The total bandwidth is calculated as: SRAM bit width × frequency × utilization rate × m. This invention includes a dynamic non-blocking polling master-slave state machine, allowing it to query other ports without blocking while serving one port, improving overall efficiency. It also includes a priority virtual output queue organized in a linked list format. All output ports share descriptor linked list nodes, achieving 100% utilization of the shared cache. Ports needing to store more descriptors can request more descriptor linked list nodes, while idle nodes are used by other ports, improving shared cache utilization and reducing resource waste.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and more specifically to a high-efficiency multi-port parallel shared cache management system for switches. Background Technology

[0002] With the rapid development of modern network technology, internet traffic has exploded, and businesses and households are increasingly demanding higher network bandwidth. Switches play a crucial role in networks. Shared buffer switches can effectively absorb sudden bursts of network traffic and reduce packet loss rates.

[0003] Traditional shared-buffer switches share a single Static Random-Access Memory (SRAM) or combine multiple SRAMs into a single SRAM. The read / write interfaces of this SRAM are time-division multiplexed to poll and serve each port, storing the data packets from each port into the buffer to achieve shared buffering.

[0004] Traditional shared buffer switches need to wait for one port to finish serving before querying the next port to see if it needs service, and then store / read the data packets of each port into / out of the shared buffer in turn.

[0005] Traditional shared-buffer switches manage data packets using descriptors, which are stored in a First-In-First-Out (FIFO) queue at each output port. The output port reads descriptors sequentially from the FIFO to output data packets in order. If the FIFO at each output port is set too small, it cannot store more descriptors when it is full, preventing further data packets from being sent to that output port, resulting in low utilization of the shared buffer. If the FIFO is set too large, allowing each output port to utilize the entire shared buffer area, it leads to resource waste, with a large number of FIFOs remaining idle.

[0006] The total bandwidth of the internal switching rate of a traditional shared cache switch is equal to the SRAM bit width × frequency × utilization. However, the bit width and frequency are limited by the manufacturing process, and the utilization is affected by the service polling of the ports and the storage management time of the shared cache. Therefore, it cannot be increased indefinitely, which has become a bottleneck that limits the further improvement of the switching rate of the shared cache switch. Summary of the Invention

[0007] The purpose of this invention is to provide a management system for switches that allows each port to access a shared cache in parallel, in order to meet the data storage capacity requirements of switches in the era of high-speed Internet.

[0008] To achieve the above-mentioned objectives, the present invention provides a high-efficiency multi-port parallel shared cache management system for switches, including multiple independent data packet receiving modules, page pointer management modules, descriptor management modules, an SRAM array with m SRAM controllers capable of independent polling and reading / writing, and multiple independent data packet sending modules corresponding to multiple output ports.

[0009] The data packet receiving module receives and temporarily stores data packets, and simultaneously requests free page pointers from the page pointer management module. It also temporarily stores the received free page pointers as page pointers. When the size of the temporarily stored data packet exceeds the preset page size, it selects an SRAM controller from the SRAM array based on the temporarily stored free page pointers and sends a write request. It also sends a preset page size of data from the temporarily stored data packet to the SRAM array. After sending, it requests a new free page pointer from the page pointer management module again. After all pages of the temporarily stored data packet have been sent, it sends a descriptor composed of the information used to manage the data packets to the descriptor management module.

[0010] The page pointer management module establishes a linked list of page pointers corresponding to each data packet based on the page pointer corresponding to each data packet. It manages multiple free page pointers corresponding to the base address of free pages in SRAM and uses dynamic non-blocking polling to provide polling services to the data packet receiving module and the data packet sending module. It satisfies the requests of the data packet receiving module and the data packet sending module for free page pointers or page pointers, and reclaims page pointers to make them free page pointers.

[0011] The descriptor management module receives descriptors from all data packet receiving modules, establishes a priority virtual output queue, and dynamically and non-blockingly polls the data packet sending modules to respond to their requests for descriptors.

[0012] Each SRAM controller in the SRAM array dynamically and non-blockingly polls multiple data packet receiving modules and multiple data packet sending modules, and autonomously selects the corresponding data packet receiving module and data packet sending module for writing and reading according to the request.

[0013] The data packet sending module requests a descriptor from the descriptor management module, selects the SRAM controller from the SRAM array based on the information in the descriptor, obtains data, sends the data packet to the output port, and sends the page pointer in the data packet to the page pointer management module.

[0014] Preferably, the data packet receiving module receives and temporarily stores the data packet according to the control signal of the input port.

[0015] Preferably, the descriptor includes: an error indicator bit, a CRC32 checksum, a home page pointer, a number of pages, a source port, a data packet priority, and destination port information.

[0016] Preferably, when the data packet receiving module requests a free page pointer from the page pointer management module, it sends relevant information, including: "whether to request a free page pointer for the first page of the data packet" and "port number".

[0017] Preferably, the page pointer management module includes:

[0018] The page pointer sending state machine responds to the request of the data packet receiving module, sends the free page pointer, and establishes the data packet page pointer linked list;

[0019] The page pointer receiving state machine responds to the request of the data packet sending module, reclaims the page pointer, and requests the page pointer sending state machine to send the next page pointer linked by the page pointer as the free page pointer;

[0020] A dynamic, non-blocking polling state machine is responsible for polling the state machines of the data packet receiving module and the data packet sending module.

[0021] The free page pointer queue is initialized after reset, stores the free page pointers, issues free page pointers according to the request of the page pointer sending state machine, and reclaims the page pointers according to the request of the page pointer receiving state machine, making them free page pointers.

[0022] Preferably, the page pointer sending state machine is a slave state machine of the write dynamic non-blocking state machine.

[0023] Preferably, the dynamic non-blocking polling state machine includes:

[0024] Write a dynamic non-blocking polling state machine to select the corresponding data packet receiving module based on the request from the data packet receiving module and whether the page pointer sending state machine is idle;

[0025] The system reads the dynamic non-blocking polling state machine and selects the corresponding data packet sending module based on the request from the data packet sending module and whether the page pointer receiving state machine is idle.

[0026] This invention proposes a high-efficiency multi-port parallel shared cache management system for switches. It supports the formation of an SRAM array using m SRAM controllers, with each SRAM controller managing one SRAM block. Page base addresses within the SRAM array are uniformly managed and allocated to achieve shared cache. Furthermore, it fully utilizes multiple read / write ports of multiple SRAM blocks, enabling the switch's input / output ports to access multiple SRAM blocks in parallel. This results in total bandwidth = SRAM bit width × frequency × utilization rate × m, solving the bottleneck caused by insufficient memory bandwidth in traditional shared cache switches. The invention includes a polling master-slave state machine, where the master state machine is a dynamic, non-blocking polling state machine. This allows the master state machine to query other ports without blocking while serving one port, improving overall efficiency. The invention also includes a priority virtual output queue organized in a linked list format. The output queues of each port are organized using a linked list, with all output ports sharing descriptor linked list nodes. All descriptor linked list nodes are sufficient to achieve 100% utilization of the shared cache. This design allows ports that need to store more descriptors to request more descriptor list nodes, while idle descriptor list nodes are used by other ports, improving the utilization of the shared cache and reducing resource waste. Attached Figure Description

[0027] Figure 1 This is a signal connection diagram between modules in the management system provided in an embodiment of the present invention;

[0028] Figure 2 A flowchart of the data packet receiving module provided in an embodiment of the present invention;

[0029] Figure 3 The organization method of the data packet page pointer linked list in the page pointer management module provided in the embodiments of the present invention;

[0030] Figure 4 The organization method of the descriptor linked list in the descriptor management module provided in the embodiments of the present invention;

[0031] Figure 5 This is a dynamic non-blocking polling state machine provided in an embodiment of the present invention;

[0032] Figure 6 A flowchart of the data packet sending module provided in an embodiment of the present invention. Detailed Implementation

[0033] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0034] This invention provides a high-efficiency multi-port parallel shared cache management system for switches, including a data packet receiving module, a page pointer management module, a descriptor management module, an SRAM array, and a data packet sending module. The signal connections between the modules are as follows: Figure 1 As shown.

[0035] The data packet receiving module is responsible for receiving data packets and sending them to the SRAM array. Each input port is equipped with one data packet receiving module. The data packet receiving module actively requests free page pointers from the page pointer management module and temporarily stores the received free page pointers. This module receives and temporarily stores data packets based on the control signals of the input port. Upon receiving a free page pointer, if the size of the temporarily stored data packet exceeds one page, each data packet receiving module independently interacts with the SRAM controller, selects an SRAM controller based on the temporarily stored free page pointer, issues a write request, and, after receiving a write permission response from the corresponding SRAM controller, sends one page of data to the SRAM array. After one page of data has been sent, the previously received free page pointer becomes invalid, and the module will request a new free page pointer from the page pointer management module again. After all pages of a data packet have been sent, the information used to manage this data packet is compiled into a descriptor and sent to the descriptor management module.

[0036] like Figure 2 As shown, each data packet receiving module operates independently, unaffected by other data packet receiving modules. Therefore, each data packet receiving module may be at different steps in the flowchart. The data packet receiving module receives data packets from the input port and temporarily stores them. When the temporarily stored data packets reach a page, it checks whether there is an available free page pointer. If there is, it proceeds to the next step; otherwise, it requests a free page pointer from the page pointer management module.

[0037] When requesting a free page pointer, the data packet receiving module needs to send relevant information, including: whether to request a free page pointer for the first page of the data packet, and the port number. The "whether to request a free page pointer for the first page of the data packet" determines whether the page pointer management module creates a new page pointer list for the new data packet or adds a new page pointer node to the existing page pointer list. Since the page pointer management module polls n data packet receiving modules, and multiple page pointer lists are being built simultaneously, the "port number" determines which port the list is created or modified for.

[0038] This invention manages SRAM in units of pages, with each page being 128 bytes. According to the IEEE 802.3 protocol, Ethernet data packets range from 64 to 1518 bytes in length. Choosing 128 bytes per page provides sufficient flexibility in page allocation while avoiding the management inefficiency caused by an excessive number of pages. Each SRAM controller contains a pseudo-dual-port SRAM, which contains p pages. In this embodiment, m SRAM controllers form an SRAM array, with a total of P = p × m pages. The free page pointer queue is initialized upon reset, containing P pages ranging from 0 to (P-1). A binary number of bits, corresponding to page P.

[0039] After the data packet receiving module obtains a valid free page pointer, it will select an SRAM controller based on the lower 1 bits. The selection of the SRAM controller based on the low 1 bits aims to distribute the SRAM controller accessed by each data packet receiving module as evenly as possible at any given time, thereby reducing the possibility of access conflicts. After selecting an SRAM controller, a write request and the high h=ql bits of the free page pointer are sent to it to select the specific page to write to in the selected SRAM controller.

[0040] After the data packet receiving module receives the write permission signal from the corresponding SRAM controller, it sends a page of data to the SRAM controller and sets the free page pointer status to invalid. If the complete data packet has been sent, it organizes the relevant information into a descriptor representing this data packet and sends it to the descriptor management module. If the complete data packet has not been sent, the above steps are repeated.

[0041] The page pointer management module manages the free page pointers corresponding to the base addresses of all free pages in SRAM and responds to page pointer requests from all input port data packet receiving modules and all output port data packet sending modules. The page pointer management module polls all data packet receiving modules, sending them free page pointers, and works with them to build a linked list of all pages for each data packet. For example, it polls n data packet sending modules, reclaims the page pointers they provide, and sends them the next page pointer linked to that page pointer. All data packet page pointer linked lists in the page pointer management module share all page pointer nodes. The number of page pointer nodes corresponds to the number of pages in all SRAM, with a total of P nodes. Each node stores... This q-bit data is both a page pointer and the address of the next page pointer node to which it is linked.

[0042] The composition of descriptors, the organization of the packet linked list in the page pointer management module, and the way descriptors are linked to packets, such as... Figure 3 As shown, each data packet has a separate descriptor, which stores the error indication, CRC32 check value, corresponding data packet home page pointer, page number, source port, priority, and destination port information.

[0043] The page pointer management module creates a linked list for each data packet, and all linked lists are stored together in a page pointer SRAM with a width of q bits and a depth of P. The page pointer management module uses a dynamic non-blocking polling state machine to poll and serve n data packet receiving modules. When serving a data packet receiving module, it retrieves a free page pointer from the free page pointer queue, sends this free page pointer to the data packet receiving module, and simultaneously completes the creation of the data packet page pointer linked list.

[0044] In this embodiment of the invention, the page pointer also serves as the page pointer SRAM address. The page pointer management module uses a dynamic non-blocking polling state machine to poll the n data packet sending modules. The data packet sending module sends a page pointer to the page pointer management module to obtain the next page pointer linked to that page pointer. When a page pointer 1 is sent to the page pointer management module to obtain the next page pointer 2 linked to it, page pointer 1 is recycled into the free page pointer queue, and then page pointer 1 is used as the address to read the page pointer SRAM. The data read is the next page pointer 2 linked to it.

[0045] The home page pointer in the descriptor serves two purposes. First, the data packet sending module uses the lower 1 bits of the home page pointer to select the corresponding SRAM controller, and sends the higher 10 bits of the home page pointer as the SRAM page base address to that SRAM controller to retrieve the data of the first page of the current data packet. Second, it sends the home page pointer to the page pointer management module to obtain the next page pointer it links to. The obtained next page pointer also serves the two purposes mentioned above.

[0046] The page pointer management module includes: a page pointer sending state machine, a page pointer receiving state machine, a dynamic non-blocking polling state machine, and a free page pointer queue. All free page pointers corresponding to the base addresses of free SRAM pages are uniformly managed and allocated by the page pointer management module, realizing the function of a shared cache.

[0047] The page pointer sending state machine is responsible for responding to requests from the data packet receiving module, sending it free page pointers, and building a separate linked list for each data packet based on the information provided. The page pointer sending state machine is a slave state machine of the write-dynamic non-blocking state machine, and it contains three states: WRITE_IDLE, TAIL_LINK, and TAIL_WRITE. WRITE_IDLE corresponds to idle state, TAIL_LINK corresponds to modifying the old page pointer node to link to the new page pointer node, and TAIL_WRITE corresponds to modifying the new page pointer node to link to itself.

[0048] The page pointer receiving state machine is responsible for responding to requests from the data packet sending module, reclaiming the page pointers it sends, and sending the next page pointer linked to by these page pointers. The page pointer receiving state machine is a slave state machine of the read dynamic non-blocking state machine, and it contains three states: RD_IDLE, PTR_RECLAIM, and PTR_TRANS. RD_IDLE corresponds to idle state, PTR_RECLAIM corresponds to reclaiming the page pointers sent by the data packet sending module, and PTR_TRANS corresponds to providing the data packet sending module with the next page pointer to link to.

[0049] The dynamic non-blocking polling state machine is responsible for polling all data packet receiving and sending modules. The page pointer management module contains both write and read dynamic non-blocking polling state machines. The write dynamic non-blocking polling state machine determines which data packet receiving module to serve based on requests from all data packet receiving modules and the idle status of the page pointer sending state machine. The read dynamic non-blocking polling state machine determines which data packet sending module to serve based on requests from all data packet sending modules and the idle status of the page pointer receiving state machine.

[0050] The free page pointer queue is a FIFO that stores free page pointers. It is initialized after reset, storing all free page pointers in it. Then, it sends a free page pointer to the state machine based on the page pointer's request, and reclaims the page pointer based on the state machine's request to the page pointer's receive state machine, making it a free page pointer.

[0051] The descriptor management module receives descriptors from all packet receiving modules, establishes a priority virtual output queue, and responds to descriptor requests from all packet sending modules. This includes: a priority virtual output queue establishment state machine, a priority virtual output queue reading state machine, a read-write mutual exclusion state machine, and header pointer / counter modification logic. The descriptors used to manage packets are organized into priority virtual output queues within the descriptor management module.

[0052] like Figure 4As shown in the embodiment of the invention, there are n output ports, and each output port has j priority queues. Therefore, the descriptor management module internally manages k = (n*j) descriptor linked lists, corresponding to the n ports and j priority queues for each port, thus implementing a priority virtual output queue. The descriptor management module maintains k head pointers, k tail pointers, and k descriptor counters. All k linked lists share a descriptor SRAM with a width equal to the descriptor width and a depth of d = P / 2. The depth d is chosen because this invention uses 128 bytes as a page, and the median size of data packets on the Internet is around 250 bytes, so one descriptor likely corresponds to two pages. The descriptor node queue is initialized after reset, consisting of d nodes from 0 to (d-1). A binary number of bits, corresponding to the addresses of d descriptor nodes. Each descriptor node stores the address of the next linked descriptor node and the descriptor itself.

[0053] The descriptor management module extracts the destination port and packet priority information from the received descriptors and links them to the corresponding descriptor lists. The descriptor management module polls for requests from the packet sending module, selects the appropriate descriptor list based on the provided destination port and packet priority information, and outputs the descriptor at the head of the list to the corresponding packet sending module.

[0054] The priority virtual output queue establishment state machine is responsible for linking descriptors to one of k linked lists based on the destination port and packet priority information in the descriptor, thus completing the packet forwarding function. It contains four states: WR_IDLE, WR_GET_DES, TAIL_WRITE, and OLD_TAIL_REWRITE. WR_IDLE corresponds to idle; WR_GET_DES corresponds to retrieving the descriptor to be linked; TAIL_WRITE corresponds to selecting the corresponding descriptor linked list based on the destination port and packet priority information in the descriptor, creating a new descriptor node for this descriptor, storing the descriptor, and linking this descriptor node to itself; OLD_TAIL_REWRITE corresponds to linking the descriptor node pointed to by the tail pointer of the selected descriptor linked list to this newly created descriptor node, and modifying the tail pointer to point to the newly created descriptor node.

[0055] The priority virtual output queue read state machine is responsible for selecting the corresponding descriptor list based on the destination port and packet priority information of the packet sending module, and outputting the descriptor in the descriptor node pointed to by the head pointer to the corresponding packet sending module. It contains three states: RD_IDLE, RD_GET_DES, and HEAD_WRITE; RD_IDLE corresponds to idle; RD_GET_DES corresponds to retrieving a descriptor from the selected descriptor list and sending it to the corresponding packet sending module; and HEAD_WRITE corresponds to modifying the head pointer of the selected descriptor list to point to the next descriptor node in the list.

[0056] A read-write mutual exclusion state machine is a state machine designed to prevent conflicts between the priority virtual output queue creation state machine and the priority virtual output queue read state machine. It contains three states: IDLE, READ, and WRITE; IDLE corresponds to idle; READ corresponds to the priority virtual output queue read state machine being executed; and WRITE corresponds to the priority virtual output queue creation state machine being executed.

[0057] The head pointer / counter modification logic is designed to help the priority virtual output queue establish a state machine and the priority virtual output queue read state machine jointly manage the k head pointers and k counters of the k linked lists. This logic will respond to the requests of these two state machines and modify the corresponding head pointers / counters.

[0058] The SRAM array forms the shared buffer in this system, responsible for distributing signal lines to the m SRAM controllers within the array. Each SRAM controller contains one SRAM block. The SRAM controllers poll all packet receiving and sending modules, responding to their read or write requests. Each SRAM controller can autonomously select one packet receiving or sending module to prioritize, based on the requests from the n input ports and n output ports. Each SRAM controller independently responds to the requests from all packet receiving and sending modules, with polling occurring independently and without interference. Furthermore, read and write polling do not interfere with each other, achieving parallel shared buffering.

[0059] Such as... are used in the page pointer management module, descriptor management module, and SRAM controller. Figure 5The diagram illustrates a dynamic non-blocking polling state machine design. The SRAM controller contains four state machines: a write dynamic non-blocking polling state machine (wr_ask0-wr_askn, n states); a read dynamic non-blocking polling state machine (rd_ask0-rd_askn, n states); a write state machine (a slave of the write dynamic non-blocking polling state machine, including WR_IDLE and WR_DATA states, completing the writing of one page of data); and a read state machine (a slave of the read dynamic non-blocking polling state machine, including RD_IDLE and RD_DATA states, completing the reading of one page of data). Each SRAM controller performs read polling and write polling independently to achieve parallel operation. The following section uses a simplified write dynamic non-blocking polling state machine as an example to illustrate the dynamic non-blocking polling state machine in this invention. When polling reaches wr_ask0, it is determined whether port 0 needs service. If port 0 needs service, it is determined whether the write state machine is idle. If the write state machine is idle, service to port 0 begins. Non-blocking means that after starting service on port 0, the dynamic non-blocking polling state machine immediately transitions to query whether subsequent ports need service, without waiting for port 0 to finish. For example, if ports 1 and 2 do not need service, but port 3 does, the write state machine is not idle at this time, so it remains in the wr_ask3 state, waiting for the write state machine to become idle. When the write state machine becomes idle, it immediately starts service on port 3 and immediately transitions to query whether subsequent ports need service.

[0060] Upon receiving a descriptor from the packet sending module, the information within it is extracted to determine the destination port and priority, in order to select a descriptor list. After selecting a descriptor list, an idle descriptor node is retrieved from the descriptor node queue. Next, it is checked whether this descriptor list is empty. If it is empty, the descriptor is stored there, and this descriptor node is linked to itself. Both the head and tail pointers are then modified to point to this descriptor node, and the corresponding descriptor counter is updated. If the list is not empty, the descriptor is stored there, and this descriptor node is linked to itself. The descriptor node pointed to by the tail pointer is linked to the newly created descriptor node, the tail pointer is then modified to point to the newly created descriptor node, and the corresponding descriptor counter is updated.

[0061] Upon receiving the request descriptor information from the packet sending module, the destination port and priority information are extracted. A linked list is selected, and the descriptors in the descriptor node pointed to by the head pointer of the linked list are sent to the packet sending module. The head pointer is then modified to point to the next descriptor node linked to the current descriptor node, and the corresponding descriptor counter is modified.

[0062] The descriptor management module collects the counter information of all descriptor linked lists and sends it to the data packet sending module as the status of the priority virtual output queue, so that the module can work with the priority scheduling algorithm to select the priority queue.

[0063] like Figure 6 As shown, each data packet sending module operates independently, unaffected by other data packet sending modules. Therefore, each data packet sending module may be at different steps in the flowchart. The data packet sending module selects a priority queue based on the priority virtual output queue status and priority scheduling algorithm sent by the descriptor management module, and requests a descriptor from that queue. Upon receiving a descriptor, it extracts relevant information from the data packet, including the home page pointer. The lower 1 bits of the home page pointer are used to select the SRAM controller, and the higher 1 bits are sent to the corresponding SRAM controller to select the page to be read. After receiving the read permission signal from the SRAM controller, it accepts one page of data and adds the corresponding control signal, sending it to the output port. At this point, the page pointer is invalid. This page pointer is sent to the page pointer management module to obtain the next page pointer linked to it. After receiving the page pointer from the page pointer management module, it performs a check. If the received page pointer is the same as the sent page pointer, it means that the page pointer node is linked to itself. Only the last page pointer node in the data packet page pointer linked list is linked to itself. At this point, the data packet has been sent completely. The received page pointer is set to invalid, and the descriptor is set to invalid. If the received page pointer is different from the sent page pointer, then the page pointer is valid, and the above steps continue.

[0064] The packet sending module is responsible for requesting descriptors from the descriptor management module, retrieving data from the SRAM array based on the home page pointer in the descriptor, and sending the data packet to the external device. Each output port is equipped with one packet sending module. The packet sending module selects a queue based on the priority scheduling algorithm and the availability of priority virtual output queues provided by the descriptor management module, and sends a descriptor request to the descriptor management module. Upon receiving a descriptor, it extracts the home page pointer, selects an SRAM controller, and issues a read request. After receiving a read permission response from the corresponding SRAM controller, it receives one page of data from the SRAM array and sends it along with relevant control signals to the output port. At this point, the current page pointer has expired. The module retrieves the next page pointer linked to the current page pointer by sending the current page pointer to the page pointer management module, continuing until all pages of this data packet have been sent to the output port.

[0065] The forwarding process of a data packet in the system is as follows:

[0066] (1) All data packet receiving modules independently store data packets according to the control signals of their respective input ports.

[0067] (2) The data packet receiving module sends a request to the page pointer management module to request a free page pointer, and indicates "whether to request a free page pointer for the first page of the data packet" and "port number" to help the page pointer management module build a data packet page pointer linked list.

[0068] (3) The page pointer management module polls all data packet receiving modules and selects one to serve first. It requests a new free page pointer from the free page pointer queue for the selected module and sends this free page pointer to the corresponding data packet receiving module. Based on the information provided by the data packet receiving module, a linked list is built. If the free page pointer is requested for a new data packet, a new page pointer linked list is built for that data packet; if the free page pointer is requested for a data packet that has already requested a free page pointer, the free page pointer is linked to the page pointer linked list that was previously built for that data packet.

[0069] (4) The data packet receiving module receives the free page pointer, extracts the information of the free page pointer, and sends a write request to the corresponding SRAM controller.

[0070] (5) Each SRAM controller independently polls the data packet receiving modules of all input ports, and after determining which port to serve, sends a write permission response signal to it.

[0071] (6) After receiving the write permission response from the corresponding SRAM controller, the data packet receiving module sends one page of data from the data packet to it.

[0072] (7) If the data packet is not completely sent after sending one page of data, a new free page pointer is requested from the page pointer management module. If the data packet is completely sent after sending one page of data, the corresponding information is combined into a descriptor and sent to the descriptor management module.

[0073] (8) The descriptor management module receives descriptors from all data packet receiving modules. This module extracts these descriptors in turn, links the descriptor to one of the k descriptor linked lists according to the destination port and priority information in the descriptor, and establishes a priority virtual output queue. It then outputs the empty / full information of the priority virtual output queue to the data packet sending module.

[0074] (9) The data packet sending module of all output ports will select a priority queue based on the priority virtual output queue empty / full information sent by the descriptor management module and the priority scheduling algorithm, and send the descriptor request information to the descriptor management module, including the destination port and priority.

[0075] (10) The descriptor management module will poll all data packet sending modules and find the descriptor node pointed to by the head pointer of the corresponding descriptor linked list according to the information provided by the module. The module will send the descriptor to the data packet sending module and modify the head pointer of the linked list to point to the next descriptor node.

[0076] (11) After receiving the descriptor, the data packet sending module will extract the data packet home page pointer from it and send this page pointer to the corresponding SRAM controller to request to read the data.

[0077] (12) Each SRAM controller independently polls the data packet sending modules of all output ports. After determining which port to serve, it sends a corresponding read permission response signal and then sends a page of data.

[0078] (13) After receiving the data, the data packet sending module will add the corresponding control signal to it and send it to the output port. At the same time, if the data packet is not completely sent, it will send the current page pointer to the page pointer management module to request the next page pointer linked to the current page pointer.

[0079] (14) The page pointer management module will poll all data packet sending modules and select one port for priority service. Based on the current page pointer sent, this module will reclaim the current page pointer, obtain the next page pointer linked by the current page pointer, and send the next page pointer to the corresponding data packet sending module.

[0080] (15) After receiving the new page pointer, the data packet sending module will compare it with the old page pointer. If the two page pointers are the same, it means that the new page pointer is the last node of the page pointer linked list of the data packet, the data corresponding to the new page pointer has been read, the page pointer is set to invalid, and a new descriptor is requested from the descriptor management module to send the next data packet; if the two page pointers are different, it means that the data packet has not been sent completely, and the current data packet continues to be sent.

[0081] This invention provides a high-efficiency multi-port parallel shared cache management system for switches, which meets the requirement of simultaneous data packet transmission and reception on n input / output ports of a switch. It efficiently manages m SRAM controllers in an SRAM array, dynamically allocating and reclaiming cache space for all input / output ports. Each port independently sends an access request to a specific SRAM controller based on its allocated cache space. Each SRAM controller independently decides which port to prioritize serving, thus achieving parallel access to the shared cache by multiple ports.

[0082] The beneficial effects of the embodiments of the present invention are:

[0083] (1) The packet receiving module of n input ports and the packet sending module of n output ports can be independently selected from m SRAM controllers for access. The m SRAM controllers can also independently select one packet sending module and one packet receiving module simultaneously for service. This method eliminates the drawback of previous shared cache designs that required time-division multiplexing of the read / write interface of a single SRAM to serve each port sequentially, thus solving the memory bottleneck of shared cache switches. With m SRAM controllers having m sets of read / write ports, the memory read / write bandwidth can be increased by m times when the SRAM bit width and frequency are the same.

[0084] (2) k priority virtual output queues are organized in the form of k linked lists, and these k linked lists share d descriptor nodes. This design eliminates the need to set a separate FIFO for each virtual output queue, and a virtual output queue can occupy all the linked list nodes. In traditional shared buffer switches, even if the SRAM used to store data packets is fully dynamically shared, the output queue of each port is implemented using a fixed-size FIFO, which limits the number of data packets stored in the SRAM to the size of the FIFO. If the FIFO of a port is full, no data packets destined for that port can be stored in the SRAM, resulting in low utilization of the shared buffer. If the FIFO of each port is designed to be quite large, enough to store descriptors that fill all the shared buffer data packets, it will waste resources, and a large number of FIFOs will be idle. This design adopts k linked lists sharing d descriptor nodes. When the virtual output queue of some output ports needs to store more descriptors, more descriptor nodes are requested; when not needed, these descriptor nodes are made available for other output ports. This allows the design to achieve 100% cache utilization in any situation while avoiding resource waste.

[0085] (3) The page pointer management module, descriptor management module, and SRAM controller all employ a dynamic non-blocking polling state machine. While serving one port, it immediately begins querying whether the next port needs service, without waiting for the previous port to finish. If a port needs service, it waits at that port, and begins serving the current port immediately after the previous port finishes service. Compared to previous polling state machines, the state machine in this invention is more efficient and can reduce invalid polling time.

Claims

1. A high-efficiency multi-port parallel shared cache management system for switches, characterized in that, It includes multiple independent data packet receiving modules corresponding to multiple input ports, a page pointer management module, a descriptor management module, an SRAM array with m SRAM controllers that can be independently polled and read / written, and multiple independent data packet sending modules corresponding to multiple output ports; The data packet receiving module receives and temporarily stores data packets, and simultaneously requests free page pointers from the page pointer management module. It also temporarily stores the received free page pointers as page pointers. When the size of the temporarily stored data packet exceeds the preset page size, it selects an SRAM controller from the SRAM array based on the temporarily stored free page pointers and sends a write request. It also sends a preset page size of data from the temporarily stored data packet to the SRAM array. After sending, it requests a new free page pointer from the page pointer management module again. After all pages of the temporarily stored data packet have been sent, it sends a descriptor composed of the information used to manage the data packets to the descriptor management module. The page pointer management module establishes a linked list of page pointers for each data packet based on the page pointer corresponding to each data packet. It manages multiple free page pointers corresponding to the base address of free pages in SRAM and uses dynamic non-blocking polling to provide polling services to the data packet receiving module and the data packet sending module. This satisfies the requests of the data packet receiving module and the data packet sending module for free page pointers or page pointers, and also reclaims page pointers to make them free page pointers. The descriptor management module receives descriptors from all data packet receiving modules, establishes a priority virtual output queue, and dynamically and non-blockingly polls the data packet sending modules to respond to their requests for descriptors. Each SRAM controller in the SRAM array dynamically and non-blockingly polls multiple data packet receiving modules and multiple data packet sending modules, and autonomously selects the corresponding data packet receiving module and data packet sending module for writing and reading according to the request. The data packet sending module requests a descriptor from the descriptor management module, selects the SRAM controller from the SRAM array based on the information in the descriptor, obtains data, sends the data packet to the output port, and sends the page pointer in the data packet to the page pointer management module.

2. The high-efficiency multi-port parallel shared cache management system for switches as described in claim 1, characterized in that, The data packet receiving module receives and temporarily stores the data packet according to the control signal of the input port.

3. The high-efficiency multi-port parallel shared cache management system for switches as described in claim 1, characterized in that, The descriptor includes: error indicator bit, CRC32 check value, home page pointer, number of pages, source port, data packet priority, and destination port information.

4. The high-efficiency multi-port parallel shared cache management system for switches as described in claim 1, characterized in that, When the data packet receiving module requests a free page pointer from the page pointer management module, it sends relevant information, including: "whether to request a free page pointer for the first page of the data packet" and "port number".

5. A high-efficiency multi-port parallel shared cache management system for switches as described in claim 1, characterized in that, The page pointer management module includes: The page pointer sending state machine responds to the request of the data packet receiving module, sends the free page pointer, and establishes the data packet page pointer linked list; The page pointer receiving state machine responds to the request of the data packet sending module, reclaims the page pointer, and requests the page pointer sending state machine to send the next page pointer linked by the page pointer as the free page pointer; A dynamic, non-blocking polling state machine is responsible for polling the state machines of the data packet receiving module and the data packet sending module. The free page pointer queue is initialized after reset, stores the free page pointers, issues free page pointers according to the request of the page pointer sending state machine, and reclaims the page pointers according to the request of the page pointer receiving state machine, making them free page pointers.

6. A high-efficiency multi-port parallel shared cache management system for switches as described in claim 5, characterized in that, The page pointer sending state machine is a slave state machine of the write dynamic non-blocking state machine.

7. A high-efficiency multi-port parallel shared cache management system for switches as described in claim 5, characterized in that, The dynamic non-blocking polling state machine includes: Write a dynamic non-blocking polling state machine to select the corresponding data packet receiving module based on the request from the data packet receiving module and whether the page pointer sending state machine is idle; The system reads the dynamic non-blocking polling state machine and selects the corresponding data packet sending module based on the request from the data packet sending module and whether the page pointer receiving state machine is idle.

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