Semiconductor structure manufacturing method and image sensor
By forming a buried layer in the back-illuminated image sensor manufacturing and using it to act as an etching blocking effect in the selective etching step, the problem of the large number of photocaps in the double-deep trench manufacturing process is solved, and the image sensor is reduced Manufacturing cost.
Patent Information
- Application Number
- CN202411129659.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-16
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-08-16
AI Technical Summary
The prior art requires two different types of grooves when manufacturing back-illuminated image sensors, resulting in the use of two photocoats in the double-deep groove manufacturing process, which is relatively expensive.
By forming a first initial trench and a second initial trench with an opening area greater than the first initial trench on the substrate surface, and depositing an isolation layer on the substrate surface, etching the isolation layer, ion implantation is performed, forming a buried layer, through The selective etching step removes the isolation layer, forms the first trench and the second trench, and uses the buried layer to act as an etching blocking effect in the second selective etching step, reducing the use of the photomask.
The manufacturing of the first and second trenches of different depths is achieved without a photocoat, which reduces the manufacturing cost of the image sensor.
Smart Images
Figure CN118645516B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and an image sensor. Background Art
[0002] Complementary Metal-Oxide-Semiconductor (CMOS) image sensors are widely used, including front side illumination (FSI) image sensors and back side illumination (BSI) image sensors. Back side illumination image sensors require two different types of grooves, including narrow and deep grooves for isolating adjacent photodiodes and wide and shallow grooves for arranging wires. Usually, two masks are required to make double-depth grooves, which is costly. Summary of the invention
[0003] In view of the above problems, the present application provides a method for manufacturing a semiconductor structure and an image sensor, aiming to reduce the number of masks used in the manufacturing process of two different types of grooves and reduce the manufacturing cost of the image sensor.
[0004] According to a first aspect of the present invention, there is provided a method for manufacturing a semiconductor structure, comprising:
[0005] Forming a first initial groove and a second initial groove having an opening area larger than that of the first initial groove on the surface of the substrate;
[0006] Depositing an isolation layer on the surface of the substrate until the first initial trench is filled and a gap is left in the center of the second initial trench;
[0007] Etching the isolation layer until the isolation layer in the second initial trench is etched away and the isolation layer remains on the bottom of the first initial trench;
[0008] performing ion implantation on the substrate to form a buried layer in the substrate below the second initial trench;
[0009] Removing the isolation layer remaining in the first initial trench by a first selective etching step;
[0010] The substrate in the first initial trench is etched through a second selective etching step to form a first trench, and the substrate on the buried layer in the second initial trench is removed to form a second trench.
[0011] Optionally, forming a first initial trench and a second initial trench having an opening area larger than that of the first initial trench on the surface of the substrate comprises:
[0012] forming a mask layer on the surface of the substrate;
[0013] Etching the mask layer through a prefabricated mask to form a patterned mask layer, wherein the prefabricated mask is formed with a first groove pattern and a second groove pattern having an area larger than the first groove pattern;
[0014] The substrate is etched using the patterned mask layer as a mask to form the first initial trenches corresponding to the first trench pattern and the second initial trenches corresponding to the second trench pattern.
[0015] Optionally, depositing an isolation layer on the surface of the substrate includes: depositing an isolation layer on the surface of the patterned mask layer;
[0016] Etching the isolation layer comprises: etching the isolation layer through a third selective etching step, and the patterned mask layer is retained during the execution of the third selective etching step.
[0017] Optionally, the third selective etching step is performed by isotropic etching.
[0018] Optionally, the material used for the isolation layer is oxide, and the ion implantation into the substrate includes: implanting oxygen ions into the substrate.
[0019] Optionally, oxygen ions are implanted into the substrate to form an oxygen-doped layer in the substrate below the second initial trench. The manufacturing method further includes: after removing the isolation layer remaining in the first initial trench through a first selective etching step, performing annealing to homogenize the oxygen ions doped in the oxygen-doped layer and then transform it into the buried layer.
[0020] Optionally, the first selective etching step is performed by isotropic etching.
[0021] Optionally, the second selective etching step is anisotropic etching.
[0022] Optionally, the material of the substrate is silicon, the ion implantation into the substrate is oxygen ion implantation, and the etching gas used in the second selective etching step includes hydrogen bromide or sulfur hexafluoride.
[0023] According to a second aspect of the present invention, there is provided an image sensor, comprising a first groove and a second groove, wherein an opening area of the second groove is larger than that of the first groove and a depth of the second groove is smaller than that of the first groove, and the first groove and the second groove are manufactured by any one of the manufacturing methods described in the first aspect.
[0024] The unexpected technical effects of this application are:
[0025] The manufacturing method of the semiconductor structure provided by the present application includes: forming a first initial groove and a second initial groove with an opening area larger than the first initial groove on the surface of the substrate; depositing an isolation layer on the surface of the substrate until the first initial groove is filled and a gap is left in the center of the second initial groove; etching the isolation layer until the isolation layer in the second initial groove is etched away and the isolation layer is left on the bottom of the first initial groove; ion implanting the substrate to form a buried layer in the substrate below the second initial groove; removing the isolation layer left in the first initial groove by a first selective etching step; etching the substrate in the first initial groove by a second selective etching step to form a first groove, and removing the substrate on the buried layer in the second initial groove to form a second groove. In the manufacturing method, the buried layer formed in the substrate below the second initial groove acts as an etching barrier in the second selective etching step, so that the depth of etching in the first initial groove in the second selective etching step can be greater than the depth of etching in the second initial groove, so that the depth of the formed first groove can be greater than the depth of the formed second groove. In the process of forming the first initial groove and the second initial groove to the first groove and the second groove of different depths, no photomask is used, so the number of photomasks used is reduced, thereby reducing the manufacturing cost of the image sensor.
[0026] Furthermore, forming a first initial groove and a second initial groove with an opening area larger than the first initial groove on the surface of the substrate includes: forming a mask layer on the surface of the substrate; etching the mask layer via a prefabricated mask to form a patterned mask layer, wherein the prefabricated mask is formed with a first groove pattern and a second groove pattern with an area larger than the first groove pattern; etching the substrate using the patterned mask layer as a mask to form a first initial groove corresponding to the first groove pattern and a second initial groove corresponding to the second groove pattern. Thus, the manufacture of the first initial groove and the second initial groove with different opening areas is achieved through one prefabricated mask, so that in the case where no mask is used in the above-mentioned process of forming the first initial groove and the second initial groove to the first groove and the second groove of different depths, the entire manufacturing process of different types of first grooves and second grooves only requires one prefabricated mask, thereby effectively controlling the manufacturing cost of the image sensor. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:
[0028] Figure 1 A schematic cross-sectional view of a conventional back-illuminated image sensor is shown;
[0029] Figure 2A flow chart showing a method for manufacturing a semiconductor structure in an embodiment of the present application;
[0030] Figure 3 A schematic cross-sectional view showing a surface of a substrate after a mask layer is formed in an embodiment of the present application;
[0031] Figure 4 A schematic cross-sectional view showing a substrate surface after a first initial groove and a second initial groove are formed in an embodiment of the present application;
[0032] Figure 5 A schematic cross-sectional view showing an isolation layer deposited on the surface of a substrate in an embodiment of the present application is shown;
[0033] Figure 6 A schematic cross-sectional view showing the third selective etching step after execution in the embodiment of the present application;
[0034] Figure 7 A schematic cross-sectional view showing ion implantation into a substrate in an embodiment of the present application is shown;
[0035] Figure 8 A schematic cross-sectional view showing the first selective etching step after execution in an embodiment of the present application;
[0036] Fig. 9 A schematic cross-sectional view showing an embodiment of the present application after annealing treatment is performed;
[0037] Fig.10 A schematic cross-sectional view showing the second selective etching step after execution in the embodiment of the present application;
[0038] Fig.11 A schematic cross-sectional view showing a high dielectric constant layer and an oxide dielectric layer deposited on the substrate surface in an embodiment of the present application;
[0039] Fig.12 A schematic cross-sectional view after a metal layer and a grid are formed in an embodiment of the present application is shown;
[0040] Fig.13 A schematic cross-sectional view of an image sensor in an embodiment of the present application is shown.
[0041] Explanation of the reference numerals: 100 - back-illuminated image sensor; 110 - base; 111 - interconnection layer; 112 - substrate; 120 - dielectric layer; 121 - high dielectric constant layer; 122 - oxide layer; 130 - metal layer; 131 - tungsten layer; 132 - aluminum layer; 140 - grid; 201 - substrate; 202 - mask layer; 202' - patterned mask layer; 203 - first initial trench; 204 - second initial trench; 205 - isolation layer; 206 - gap; 207 - oxygen-doped layer; 208 - buried layer; 209 - first trench; 210 - second trench; 211 - high dielectric constant layer; 212 - oxide layer; 213 - metal layer; 214 - grid; 215 - interconnection layer. DETAILED DESCRIPTION
[0042] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.
[0043] This application may be presented in a variety of forms, some examples of which are described below.
[0044] Figure 1 FIG. 4 shows an existing back-illuminated image sensor. Figure 1 As shown, the back-illuminated image sensor 100 includes a substrate 110, a dielectric layer 120, a metal layer 130 and a grid 140. The substrate 110 is divided into a pixel region I and a peripheral region II, wherein the pixel region I is a region where a plurality of photodiodes PD are arranged; the peripheral region II is a region arranged outside the pixel region I and used to form peripheral components of the back-illuminated image sensor 100, such as components used to realize logic functions.
[0045] Reference Figure 1The base 110 includes an interconnection layer 111 and a substrate 112. The interconnection layer 111 is formed on the front side of the substrate 112 and may include a multi-layer patterned conductive layer and a conductive plug isolated by a dielectric material, and the conductive layer and the conductive plug provide interconnections between various doping regions, circuits and input / outputs of the back-illuminated image sensor 100. The above-mentioned dielectric layer 120 is formed on the back side of the substrate 112. A first trench is formed on the back side of the portion of the substrate 112 corresponding to the pixel region I, and the first trench is filled with the dielectric layer 120 to form a deep trench isolation structure DTI for isolating adjacent photodiodes PD. The grid 140 is separated by the dielectric layer 120 and the deep trench isolation structure DTI corresponding to the pixel region I is formed on the back side of the substrate 112. A second groove is formed on the back side of the portion of the substrate 112 corresponding to the peripheral region II, and a metal layer 130 is then formed after a dielectric layer 120 is deposited on the inner wall of the second groove. Since the dielectric layer 120 in the second groove is still in a groove shape, the actual width of the wire played by the metal layer 130 can be increased, thereby reducing the wire resistance, wherein the dielectric layer 120 may include a high dielectric constant layer 121 and an oxide layer 122, the high dielectric constant layer 121 is deposited on the back side of the substrate 112, and the oxide layer 122 is formed on the back side of the high dielectric constant layer 121; the metal layer 130 may include a tungsten layer 131 and an aluminum layer 132, the tungsten layer 131 is deposited on the back side of the dielectric layer 120, and the aluminum layer 132 is formed on the side of the tungsten layer 131 away from the groove wall of the second groove.
[0046] The depth of the second groove is, for example, 0.3um-1.5um, and its opening area is reflected as the top width in the illustrated cross section, and the top width is, for example, 10um-200um. Compared with the second groove, the first groove has a greater depth and a smaller width. In the existing process, when two different types of grooves, such as the first groove and the second groove, are formed in the substrate 112, two patterning processes including photolithography and etching are required, so two masks are required, which is costly.
[0047] In view of this, an embodiment of the present application provides a method for manufacturing a semiconductor structure, aiming to reduce the number of masks used in the manufacturing process of two different types of grooves and reduce the manufacturing cost of image sensors. Figure 2 A flowchart showing a method for manufacturing a semiconductor structure according to an embodiment of the present application is shown. Figure 2 , the manufacturing method comprises:
[0048] Step S110 , forming a first initial trench and a second initial trench having an opening area larger than that of the first initial trench on the surface of the substrate.
[0049] Step S120 , depositing an isolation layer on the surface of the substrate until the first initial trench is filled and a gap remains in the center of the second initial trench.
[0050] Step S130 , etching the isolation layer until the isolation layer in the second initial trench is etched away and the isolation layer remains on the bottom of the first initial trench.
[0051] Step S140 , performing ion implantation on the substrate to form a buried layer in the substrate below the second initial trench.
[0052] Step S150, removing the isolation layer remaining in the first initial trench through a first selective etching step.
[0053] Step S160, etching the substrate in the first initial trench through a second selective etching step to form a first trench, and removing the substrate on the buried layer in the second initial trench to form a second trench.
[0054] It should be noted that the opening area of the above-mentioned second initial groove is larger than that of the first initial groove. Therefore, in the process of depositing the isolation layer on the surface of the substrate, the first initial groove and the second initial groove are respectively filled with the isolation layer deposited on the groove wall and the groove bottom to achieve the first initial groove being filled first. In this way, by controlling the deposition time of the isolation layer, the first initial groove can be filled while a gap is left in the center of the second initial groove.
[0055] It should be understood that depositing an isolation layer on the surface of the substrate will cause the isolation layer to be deposited on the substrate outside the notch of the first initial groove. When the first initial groove is filled, the isolation layer deposited on the substrate outside the notch of the first initial groove will be closed at the same time. Therefore, when the first initial groove is filled, the surface of the isolation layer at the notch of the first initial groove is above the plane where the notch of the first initial groove is located, and the thickness of the isolation layer on the plane where the notch of the first initial groove is located is roughly equal to the thickness of the isolation layer in the second initial groove. Then the isolation layer is etched. The gap left in the center of the second initial groove allows the isolation layer deposited in the second initial groove to be etched from the gap to the groove wall and the groove bottom at the same time. Since the first initial groove has been filled, the isolation layer can only be etched from the isolation layer surface above the groove opening to the groove bottom. In this way, the thickness required to etch the isolation layer in the first initial groove is greater than the thickness required to etch the isolation layer in the second initial groove. Therefore, the isolation layer in the second initial groove is etched first. By controlling the etching time, the isolation layer in the second initial groove can be etched away while the isolation layer remains on the bottom of the first initial groove.
[0056] The buried layer formed in the substrate below the second initial groove is a structure buried in the substrate, and thus the substrate is separated from the bottom of the second initial groove, so that the first selective etching step is to selectively etch the isolation layer without etching the substrate. After the isolation layer left in the first initial groove is removed by the first selective etching step, the second selective etching step is to selectively etch the substrate in the first initial groove and on the buried layer in the second initial groove without etching the buried layer, so that the buried layer acts as an etching barrier in the second selective etching step, so that the depth of the first groove formed can be greater than the depth of the second groove formed by etching in the first initial groove at a depth greater than the depth of the buried layer through the second selective etching step. Therefore, the formation process of the different depths of the first groove and the second groove no longer requires a mask, so that the number of masks used in the manufacturing process of the double-depth groove can be controlled, the manufacturing cost of the double-depth groove can be reduced, and the manufacturing cost of the image sensor with the double-depth groove can also be reduced accordingly.
[0057] Figures 3 to 10 Schematic diagram of each step of an exemplary method for manufacturing a semiconductor structure provided in an embodiment of the present application. Figures 3 to 10 The manufacturing method of the semiconductor structure provided in the embodiment of the present application is described in detail.
[0058] In step S110, forming a first initial trench and a second initial trench having an opening area larger than the first initial trench on the surface of the substrate may include: Figure 3 As shown in FIG. 1 , a mask layer 202 is formed on the surface of the substrate 201; and then the mask layer 202 is etched through a prefabricated mask to form a Figure 4 The patterned mask layer 202' is then used as a mask to etch the substrate 201 to form a Figure 4 A first initial trench 203 and a second initial trench 204 are shown.
[0059] Specifically, the prefabricated mask is formed with a first groove pattern for forming the first initial groove 203 and a second groove pattern for forming the second initial groove 204, and the area of the second groove pattern is larger than the first groove pattern, so the opening area of the correspondingly formed second initial groove 204 is larger than the first initial groove 203. Figure 4 The cross-sectional view shows that the top width of the second initial trench 204 is greater than that of the first initial trench 203. The mask layer 202 is, for example, a hard mask layer, on which photoresist is coated and the coated photoresist is exposed by a prefabricated mask to form a mask for etching the mask layer 202, and then the mask layer 202 is etched to form the patterned mask layer 202'.
[0060] It should be noted that Figure 4The first initial trench 203 and the second initial trench 204 are in an inverted trapezoidal shape in the cross-sectional view due to over-etching and other reasons. It should be understood that the first initial trench 203 and the second initial trench 204 formed above have the same depth because they are formed in the same patterning process including photolithography and etching based on a prefabricated mask. The above steps S120 to S160 performed thereafter are to perform re-etching of the first initial trench 203 and the second initial trench 204 to different depths to form the first trench and the second trench with increased depth. In view of this, the process of etching the substrate 201 in step S110 to form the first initial trench 203 and the second initial trench 204 is also called a shallow trench isolation (STI) etching process.
[0061] The formation process of the first initial groove 203 and the second initial groove 204 with different opening areas described above only requires one prefabricated mask. Therefore, when the formation process from the first initial groove 203 and the second initial groove 204 to the first groove and the second groove of different depths does not use a mask, the entire manufacturing process of different types of first grooves and second grooves only requires one prefabricated mask.
[0062] In step S120, depositing an isolation layer on the substrate surface may include: Figure 5 As shown, an isolation layer 205 is deposited on the surface of the patterned mask layer 202'. Figure 5 , the isolation layer 205 deposited as described above fills the first initial groove 203 and leaves a gap 206 in the center of the second initial groove 204, and the surface of the isolation layer 205 at the notch of the first initial groove 203 is above the plane where the notch of the first initial groove 203 is located, and the isolation layer 205 above the plane where the notch of the first initial groove 203 is located has approximately the same thickness as the isolation layer 205 in the second initial groove 204. The above-mentioned deposition of the isolation layer 205 can be carried out by a high-density plasma (HDP) chemical vapor deposition process or a high aspect ratio process (HARP), so as to ensure that the isolation layer 205 can be filled into the first initial groove 203 and the second initial groove 204 more evenly.
[0063] In step S130, etching the isolation layer may include: etching the isolation layer through a third selective etching step. Figure 5 The isolation layer 205 shown is etched. The third selective etching step may be performed by isotropic etching, so that Figure 6As shown, the isolation layer 205 in the second initial trench 204 is etched away, while the isolation layer 205 remains on the bottom of the first initial trench 203. The third selective line etching step is to selectively etch the isolation layer 205 without etching the patterned mask layer 202', that is, the patterned mask layer 202' is retained during the execution of the third selective etching step, so that the patterned mask layer 202' converted from the mask layer 202 can protect the substrate 201 on its bottom surface in the third selective etching step and subsequent steps.
[0064] In step S140, ion implantation is performed on the substrate, which may include: Figure 7 As shown, oxygen ion implantation is performed on the substrate 201. The material used for the isolation layer 205 can be an oxide, such as silicon dioxide (SiO2), so that the execution of step S140 does not cause the isolation layer 205 in the first initial trench 203 to change in material. The presence of the patterned mask layer 202' during the oxygen ion implantation process protects the substrate 201 at its bottom without changing its material. The patterned mask layer 202' is then removed, so the execution of step S140 does not cause any other effects except for forming a buried layer in the substrate 201 below the second initial trench 204 as described above.
[0065] In step S150, the isolation layer remaining in the first initial trench is removed by a first selective etching step, which may be an isotropic etching step. Figure 7 The remaining isolation layer 205 in the first initial trench 203 is removed, for example, by isotropic wet etching. Figure 8 shown.
[0066] Further, oxygen ion implantation into the substrate 201 is performed as follows Figure 7 As shown in FIG. 1 , an oxygen-doped layer 207 is formed in the substrate 201 below the second initial trench 204. The semiconductor structure manufacturing method provided in the present application may further include: performing an annealing process after step S150 is performed to homogenize the oxygen ions doped in the oxygen-doped layer 207 and transform them into Fig. 9 The buried layer 208 shown in the figure ensures that the buried layer 208 in the step S160 executed later can more reliably play the etching barrier role in the second selective etching step; and because the annealing treatment is performed after the step S150, and the isolation layer 205 remaining in the first initial trench 203 has been removed by the step S150, the annealing treatment will not change the material of the substrate 201 at the bottom of the first initial trench 203 due to the oxygen ions diffused into the isolation layer 205.
[0067] In step S160, the substrate in the first initial trench is etched to form a first trench by a second selective etching step, and the substrate on the buried layer in the second initial trench is removed to form a second trench. The second selective etching step may be anisotropic etching. Fig. 9 and Fig.10 As shown, the anisotropic etching is performed in a direction from the surface of the substrate 201 to the bottom surface, so that the substrate in the first initial trench 203 is etched to increase the depth of the first initial trench 203 to form a first trench 209; and the substrate 201 on the buried layer 208 in the second initial trench 204 is removed to increase the depth of the second initial trench 204 to form a second trench 210. The existence of the buried layer 208 blocks the increased depth value of the second initial trench 204, while the increased depth value of the first initial trench 203 is not limited in the substrate 201, so the depth of the formed first trench 209 can be greater than that of the formed second trench 210.
[0068] As described above, the second selective etching step is to selectively etch the substrate 201 located on the buried layer 208 in the first initial groove 203 and the second initial groove 204 without etching the buried layer 208. Therefore, when the substrate 201 is made of silicon (Si) and oxygen ions are injected into the substrate 201 in step S140, the etching gas that can be used in the second selective etching step includes hydrogen bromide (HBr) or sulfur hexafluoride (SF6), thereby achieving etching of the silicon material without etching silicon dioxide formed after the silicon material is oxidized.
[0069] The above-mentioned method for manufacturing a semiconductor structure realizes the manufacturing of the first trench 209 and the second trench 210 of different depths with fewer masks. When the first trench 209 and the second trench 210 are applied to an image sensor, after removing the patterned mask layer 202', Fig.11 As shown in FIG. 1 , a high dielectric constant layer 211 and an oxide layer 212 are sequentially deposited on the surface of the substrate 201, wherein the first trench 209 is filled by the deposition of the high dielectric constant layer 211 and the oxide layer 212, thereby forming a deep trench isolation structure DTI for isolating adjacent photodiodes PD. Fig.12 As shown, a grid 214 is formed on the deep trench isolation structure DTI with a high dielectric constant layer 211 and an oxide layer 212 therebetween; the second trench 210 is still in a groove shape after the high dielectric constant layer 211 and the oxide layer 212 are deposited. Fig.12 The metal layer 213 is deposited on the surface of the oxide layer 212, so that the actual width of the wire played by the metal layer 213 can be increased, thereby reducing the wire resistance. Fig.13As shown, the substrate 201 is formed on the surface of the interconnection layer 215. The interconnection layer 215 can be connected to the metal layer 213 through a connection channel formed between the interconnection layer 215 and the metal layer 213. A multi-layer patterned conductive layer and a conductive plug isolated by a dielectric material are arranged in the interconnection layer 215. The conductive layer and the conductive plug provide interconnection between various doping regions, circuits and input / outputs of the image sensor.
[0070] Corresponding to the manufacturing method of the semiconductor structure provided in the above embodiments, another embodiment of the present application further provides an image sensor, which includes a first groove and a second groove, the opening area of the second groove is larger than the first groove and the depth of the second groove is smaller than the first groove, and the first groove and the second groove are manufactured using any one of the manufacturing methods provided in the above embodiments. Fig.13 The image sensor provided by the embodiment of the present application has a relatively low manufacturing cost because the number of masks used to manufacture the first grooves and the second grooves of different depths can be controlled to one.
[0071] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A method for manufacturing a semiconductor structure, comprising: Forming a first initial groove and a second initial groove having an opening area larger than that of the first initial groove on the surface of the substrate; Depositing an isolation layer on the surface of the substrate until the first initial trench is filled and a gap is left in the center of the second initial trench; Etching the isolation layer until the isolation layer in the second initial trench is etched away and the isolation layer remains on the bottom of the first initial trench; Performing ion implantation on the substrate when an isolation layer is left on the bottom of the first initial trench and the isolation layer in the second initial trench is etched away, so as to form a buried layer in the substrate below the second initial trench; Removing the isolation layer remaining in the first initial trench by a first selective etching step; After the isolation layer remaining in the first initial trench is removed, the substrate in the first initial trench is etched through a second selective etching step to form a first trench, and the substrate on the buried layer in the second initial trench is removed to form a second trench having a depth less than that of the first trench.
2. The manufacturing method according to claim 1, wherein: Forming a first initial trench and a second initial trench having an opening area larger than that of the first initial trench on a surface of a substrate, comprising: forming a mask layer on the surface of the substrate; Etching the mask layer through a prefabricated mask to form a patterned mask layer, wherein the prefabricated mask is formed with a first groove pattern and a second groove pattern having an area larger than that of the first groove pattern; The substrate is etched using the patterned mask layer as a mask to form the first preliminary trenches corresponding to the first trench pattern and the second preliminary trenches corresponding to the second trench pattern.
3. The manufacturing method according to claim 2, wherein: Depositing an isolation layer on the surface of the substrate, comprising: depositing an isolation layer on the surface of the patterned mask layer; Etching the isolation layer comprises: etching the isolation layer through a third selective etching step, and the patterned mask layer is retained during the execution of the third selective etching step.
4. The manufacturing method according to claim 3, wherein: The third selective etching step is performed by isotropic etching.
5. The manufacturing method according to claim 3, wherein: The material used for the isolation layer is oxide, and ion implantation is performed on the substrate, including: implanting oxygen ions into the substrate.
6. The manufacturing method according to claim 5, wherein: Oxygen ions are implanted into the substrate to form an oxygen-doped layer in the substrate below the second initial trench. The manufacturing method also includes: after removing the isolation layer remaining in the first initial trench through a first selective etching step, annealing is performed to homogenize the oxygen ions doped in the oxygen-doped layer and then transform it into the buried layer.
7. The manufacturing method according to claim 3, wherein: The first selective etching step is performed by isotropic etching.
8. The manufacturing method according to claim 3, wherein: The second selective etching step is anisotropic etching.
9. The manufacturing method according to claim 8, wherein: The material of the substrate is silicon, the ion implantation into the substrate is oxygen ion implantation, and the etching gas used in the second selective etching step includes hydrogen bromide or sulfur hexafluoride.
10. An image sensor, comprising a first groove and a second groove, wherein the opening area of the second groove is larger than that of the first groove and the depth of the second groove is smaller than that of the first groove, and the first groove and the second groove are manufactured by the manufacturing method according to any one of claims 1 to 9.