A consistency verification method and related apparatus

Abstract

Consistency verification method and related device are disclosed, an initial operation request is generated through an EP module, the initial operation request is a PCIE signal, a to-be-executed operation request is obtained by performing format conversion on the initial operation request through an RC module, the to-be-executed operation request is an AXI4 signal, the to-be-executed operation request is sent to an RNI of a to-be-tested device, so as to generate an operation message through the RNI, and the operation message is sent to an HNF of the to-be-tested device, so as to operate a first target address in a host storage space of the to-be-tested device through the HNF to obtain an operation result. In this way, by utilizing the characteristics of the RNI external I / O device, the PCIE device can send an operation request to the to-be-tested device, and the data in the host storage space of the to-be-tested device is operated. After the host storage space is operated, the data of the first target address is obtained as first detection data, and then a comparison result is determined. The consistency of the to-be-tested device based on the CHI protocol is detected, and the test efficiency and accuracy are high.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a consistency verification method and related device. BACKGROUND

[0002] In modern computer systems, both central processing units (CPUs) and input / output (I / O) devices (such as disks, network interfaces, etc.) can directly access the host memory (RAM), which, however, brings some potential problems: 1) cache inconsistency, the CPU may cache some memory data, and if the I / O device modifies these data at the same time, the memory data in the cache will be different from that in the I / O device (simplified as IO) if the CPU cache is not updated; 2) inconsistency problem caused by multi-core processors, multiple CPU cores may access and modify memory data at the same time, which aggravates the difficulty of maintaining data consistency.

[0003] In computer systems, it is necessary to ensure the data consistency between I / O devices and CPUs (such as CPU cache), which is called I / O coherence (I / O Coherency). With the wide application of multi-core processors and complex I / O devices, I / O coherence becomes more and more important to avoid errors caused by data inconsistency.

[0004] Coherent Hub Interface (CHI) is a high-performance coherent interconnection protocol developed by ARM for multi-processor systems. The CHI protocol is used to connect multiple processor cores, caches and other system components to ensure data consistency and efficient transmission between different components. The device under test based on the CHI protocol has an IO coherent Requesting Node (RNI) for connecting external I / O devices, and a Home Node Full (HNF) for interacting with storage space.

[0005] At present, the I / O coherence detection method for the device under test based on the CHI protocol is still in a blank state. SUMMARY

[0006] To solve the above technical problems, the embodiments of the present application provide a consistency verification method and related device, which realize the consistency detection of the device under test based on the CHI protocol, and have high testing efficiency and accuracy.

[0007] The embodiments of the present application provide a consistency verification method, which comprises:

[0008] An initial operation request is generated by a root node EP module, the initial operation request comprising a first write request or a first read request, the first write request comprising to-be-written data, the initial operation request being a PCIE signal in a high-speed serial computer expansion bus standard (PCIE, Peripheral Component Interconnect Express);

[0009] The initial operation request is converted into a to-be-executed operation request by a root complex RC module, and the to-be-executed operation request is sent to an IO consistency request node RNI of the device under test, so as to generate an operation packet by the RNI and send the operation packet to a home node HNF of full consistency of the device under test, so as to operate a first target address in a host storage space of the device under test by the HNF to obtain an operation result; the to-be-executed operation request is an AXI4 signal, when the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address, and when the initial operation request is a read request, the operation result comprises first read data of the first target address;

[0010] Data of the first target address is obtained as first detection data;

[0011] If the initial operation request is a first write request, a first comparison result is obtained by comparing the first detection data and the to-be-written data; if the initial operation request is a first read request, a second comparison result is obtained by comparing the first detection data and the first read data.

[0012] Optionally, the RC module enables PCIE configuration through a configuration interface, and the EP module enables configuration through a management interface connected with the RC module, and the EP module is configured with a descriptor of direct memory access (DMA) and data transfer channel control logic, so as to realize DMA data transfer.

[0013] Optionally, the method further comprises:

[0014] A second read data is obtained by performing a read operation on a second target address in the host storage space according to a configured read descriptor through a direct memory access (DMA) module;

[0015] The second read data is sent to a media access control (MAC) module through the DMA module;

[0016] A second write request comprising the second read data is sent to the DMA module through the MAC module;

[0017] A write operation is performed on a third target address in the host storage space according to a configured write descriptor through the DMA module;

[0018] acquire data at the second target address as second detection data, and acquire data at the third target address as third detection data;

[0019] compare the second detection data with second read data to obtain a third comparison result, and compare the third detection data with the second read data to obtain a fourth comparison result.

[0020] Optionally, the MAC module is enabled by a configuration interface, and the DMA module is enabled by the configuration interface, and the DMA module is configured with a descriptor of the DMA and data transfer channel control logic to implement data transfer of the DMA.

[0021] Optionally, if the initial operation request is a write request, before the RNI node of the device under test is sent the operation request to be executed, the method further comprises:

[0022] performing a write operation on the first target address by a full request node RNF of the device under test;

[0023] Optionally, after the operation result is obtained by the HNF performing the operation on the first target address in the host storage space, the method further comprises:

[0024] performing a read operation on the first target address by the RNF to obtain third read data;

[0025] comparing the first detection data with the third read data to obtain a fifth comparison result.

[0026] Optionally, the RNI and the HNF communicate through a network on chip NOC, the RNF is connected to the NOC, and the NOC is further connected to a full coherent slave node SNF of the device under test.

[0027] If the initial operation request includes a first write request, the operation result is obtained by the HNF performing the operation on the first target address in the host storage space, including:

[0028] performing a write operation on the first target address in the host cache in the host storage space by the HNF to obtain a write completion signal;

[0029] Or, the operation message is sent by the HNF to the SNF, so that a write operation is performed on the first target address in the host memory in the host storage space by the SNF to obtain a write completion signal.

[0030] Optionally, the host storage space comprises a host memory or a host cache, the first target address comprises a first start address and a first field length, the number of the first target addresses is multiple, and address ranges corresponding to the multiple first target addresses cover a read-write test range in the host storage space.

[0031] The embodiment of the application provides a consistency verification device, comprising:

[0032] An operation request generation unit is configured to generate an initial operation request through a root node EP module, wherein the initial operation request comprises a first write request or a first read request, the first write request comprises to-be-written data, and the initial operation request is a high-speed serial computer expansion bus standard PCIE signal.

[0033] An operation request sending unit is configured to perform format conversion on the initial operation request through a root complex RC module to obtain a to-be-executed operation request, and send the to-be-executed operation request to an IO consistency request node RNI of a device under test, so as to generate an operation message through the RNI, and send the operation message to a full-consistency master node HNF of the device under test, so as to perform operation on a first target address in a host storage space of the device under test through the HNF to obtain an operation result; the to-be-executed operation request is an AXI4 signal, when the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address, and when the initial operation request is a read request, the operation result comprises first read data of the first target address.

[0034] A first detection data acquisition unit is configured to acquire data of the first target address as first detection data.

[0035] A first comparison unit is configured to compare the first detection data and the to-be-written data to obtain a first comparison result when the initial operation request is a first write request, and compare the first detection data and the first read data to obtain a second comparison result when the initial operation request is a first read request.

[0036] Optionally, the RC module is enabled for PCIE configuration through a configuration interface, and the EP module is enabled for configuration through a management interface connected with the RC module, and the EP module is configured with a descriptor of direct memory access DMA and data transfer channel control logic, so as to realize DMA data transfer.

[0037] Optionally, the device further comprises:

[0038] The first reading unit is configured to perform a reading operation on the second target address in the host storage space to obtain second reading data according to a configured reading descriptor through a direct memory access (DMA) module.

[0039] The reading data sending unit is configured to send the second reading data to a media access control (MAC) module through the DMA module.

[0040] The writing request sending unit is configured to send a second writing request including the second reading data to the DMA module through the MAC module.

[0041] The first writing unit is configured to perform a writing operation on a third target address in the host storage space according to a configured writing descriptor through the DMA module.

[0042] The second detection data obtaining unit is configured to obtain data of the second target address as second detection data and data of the third target address as third detection data.

[0043] The second comparison unit is configured to compare the second detection data with the second reading data to obtain a third comparison result and compare the third detection data with the second reading data to obtain a fourth comparison result.

[0044] Optionally, the MAC module is enabled through a configuration interface, and the DMA module is enabled through the configuration interface.

[0045] Optionally, if the initial operation request is a writing request, the device further comprises:

[0046] The second writing unit is configured to perform a writing operation on the first target address through a full request node (RNF) of the device under test before the RNI node of the device under test sends the operation request to be executed.

[0047] and / or,

[0048] The second reading unit is configured to perform a reading operation on the first target address through the RNF to obtain third reading data after the HNF performs an operation on the first target address in the host storage space to obtain an operation result.

[0049] The third comparison unit is configured to compare the first detection data with the third reading data to obtain a fifth comparison result.

[0050] Optionally, the RNI and the HNF communicate through a network on chip (NOC), the RNF is connected to the NOC, and the NOC is also connected to a full-coherent slave node (SNF) of the DUT;

[0051] If the initial operation request comprises a first write request, the HNF performs an operation on a first target address in a host storage space to obtain an operation result, including:

[0052] The HNF performs a write operation on the first target address in the host cache in the host storage space to obtain a write completion signal.

[0053] Or, the HNF sends the operation packet to the SNF, so that the SNF performs a write operation on the first target address in the host memory in the host storage space to obtain a write completion signal.

[0054] Optionally, the host storage space comprises a host memory or a host cache, the first target address comprises a first start address and a first field length, the number of the first target addresses is a plurality, and the address ranges corresponding to the plurality of first target addresses cover a read-write test range in the host storage space.

[0055] In a third aspect, an embodiment of the present application provides a consistency verification platform, comprising:

[0056] a root node (EP) module and a root complex (RC) module;

[0057] a verification module configured to execute the consistency verification method of the first aspect.

[0058] Optionally, the consistency verification platform further comprises:

[0059] a first configuration interface configured to complete PCIE configuration of the RC module to enable the RC module;

[0060] a management interface connected to the RC module and configured to complete configuration of the EP module to enable the EP module; the EP module is configured with a descriptor of direct memory access (DMA) and data transfer channel control logic to implement DMA data transfer.

[0061] Optionally, the consistency verification platform further comprises:

[0062] a direct memory access (DMA) module and a media access control (MAC) module.

[0063] Optionally, the consistency verification platform further comprises:

[0064] a second configuration interface configured to complete configuration of the MAC module to enable the MAC module.

[0065] a third configuration interface configured to complete configuration of the DMA module to enable the DMA module, the DMA module being configured with a descriptor of the DMA and data transfer channel control logic to enable the DMA data transfer.

[0066] In a fourth aspect, an embodiment of the present application discloses a computer device, which comprises a processor and a memory:

[0067] The memory is configured to store program code and transmit the program code to the processor.

[0068] The processor is configured to execute the consistency verification method according to the instructions in the program code.

[0069] In a fifth aspect, an embodiment of the present application discloses a computer readable storage medium configured to store a computer program, the computer program being configured to execute the consistency verification method according to the first aspect when executed by a processor.

[0070] The embodiments of the present application provide a consistency verification method and related device, an initial operation request is generated by a root node EP module, the initial operation request can include a first write request or a first read request, the first write request includes to-be-written data, the initial operation request is a PCIE signal, a to-be-executed operation request is obtained by performing format conversion on the initial operation request by a root complex RC module, the to-be-executed operation request is an AXI4 signal, the to-be-executed operation request is sent to an IO consistency request node RNI of a to-be-tested device, so as to generate an operation message by the RNI, and the operation message is sent to a full consistency master node HNF of the to-be-tested device, so as to perform operation on a first target address in a host storage space of the to-be-tested device by the HNF to obtain an operation result. When the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address, and when the initial operation request is a read request, the operation result includes first read data of the first target address. In this way, by using the characteristics of the RNI external I / O device, the EP module and the RC module, which are two PCIE devices, can send an operation request to the to-be-tested device, and operation on data in the host storage space of the to-be-tested device is realized.

[0071] After the operation on the host storage space, the data of the first target address can be acquired as first detection data, if the initial operation request is the first write request, the first comparison result is obtained by comparing the first detection data and the to-be-written data, which is used to reflect the IO consistency in the write process, if the initial operation request is the first read request, the second comparison result is obtained by comparing the first detection data and the first read data, which is used to reflect the IO consistency in the read process. That is, through the PCIE device, the IO consistency in the write process and the IO consistency in the read process can be automatically simulated and tested, the consistency detection of the to-be-tested device based on the CHI protocol is realized, and the test efficiency and accuracy are high. BRIEF DESCRIPTION OF DRAWINGS

[0072] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0073] Figure 1 A flow chart of a consistency verification method provided by the embodiment of the present application is provided.

[0074] Figure 2 A structural schematic diagram of a consistency verification platform provided by the embodiment of the present application is provided.

[0075] Figure 3 A flow chart of another consistency verification method provided by the embodiment of the present application is provided.

[0076] Figure 4 A structural block diagram of a consistency verification device provided by the embodiment of the present application is provided.

[0077] Figure 5 A structural block diagram of a computer device for consistency verification provided by the embodiment of the present application is provided. DETAILED DESCRIPTION

[0078] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0079] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the connotation of the present application, therefore the present application is not limited by the specific embodiments disclosed below.

[0080] With reference to the accompanying drawings, the specific implementation manners of the consistency verification method and the related device provided by the embodiments of the present application will be described in detail below through embodiments.

[0081] Reference Figure 1 As shown in the figure, the flowchart of the consistency verification method provided by the embodiments of the present application can include the following steps.

[0082] S101, an initial operation request is generated through an EP module, the initial operation request including a first write request or a first read request.

[0083] S102, the initial operation request is format-converted to obtain an operation request to be executed through an RC module, and the operation request to be executed is sent to an IO consistency request node RNI of a device under test.

[0084] In the embodiments of the present application, the device under test can be input and output simulated and tested through an EP module and an RC module, which are two PCIE devices. PCIE is a high-speed serial computer expansion bus standard, which is used to connect the mainboard of a computer and external hardware devices, such as a graphics card, a network card, a solid state disk, etc. PCIe is an upgraded version of traditional PCI, which provides higher bandwidth and lower latency. Reference Figure 2 As shown in the figure, the structure diagram of the consistency verification platform provided by the embodiments of the present application includes an EP module and an RC module.

[0085] Since ARM provides a high-performance PCIe IP core, which supports fast and reliable PCIe communication, by using the IP core of ARM, an efficient consistency verification platform can be constructed, and the EP module and the RC module can both be the IP core of ARM. Specifically, the IP (AXI Bridge for PCI Express Gen3 Subsystem v3.0) of ARM can be selected as the RC module of PCIE, and the IP (DMA / Bridge Subsystem for PCI Express v4.1) of ARM can be selected as the PCIE EP module connected to the outside of PC. The RC module is used to convert the PCIE data stream from the EP module into an AXI4 data stream and send it to the device under test, and convert the AXI4 data stream from the device under test into a PCIE data stream and send it to the EP module.

[0086] Reference Figure 2As shown, the device under test can include an IO consistency request node (RNI), a full consistency host node (HNF) and a host storage space. The RNI is connected with the RC module, and is configured to convert AXI4 data stream from the RC module into transaction packets of the CHI protocol, which can include read messages or write messages. The HNF is configured to interact with the host storage space based on the read messages or the write messages. The host storage space includes at least one of a host cache and a host memory. The RNI and the HNF can communicate through a network on chip (NOC), which is a communication method of a system on chip and has better performance than a traditional bus system.

[0087] The RC module is enabled for PCIE configuration through a configuration interface (referred to as a first configuration interface). The configuration interface can be an AXI Verification IP, and the PCIE-related configuration of the RC module is completed through an AXI LITE interface. For example, an AXI VIP of the AXI LITE interface with 32-bit address and data bit width (other options can also be selected in other scenarios) can be selected to configure the PCIE register of the RC module, the SUBBUS (identity information) is configured as 1, the slot function is configured, the PCIE bridge (bridge function) is enabled, the bridge enable is pulled high, the AXI-to-PCIE address conversion register is configured, the memory space (storage space) and the bus master (bus master unit) register are enabled, and the entire RC module is enabled. The slot function is used to realize hot plug and is an optional configuration item, which can not be configured in other scenarios.

[0088] The EP module is enabled for configuration through a master interface connected with the RC module. The master interface can be an AXI Verification IP (AXI VIP), and the related configuration of the EP module is completed through an AXI4 master interface. The EP module is configured with a descriptor and data carrying channel control logic of direct memory access (DMA) to realize DMA data carrying, complete writing and reading of a large amount of data, and prove the completeness of multi-core consistency after data matching. DMA refers to a technology that allows external devices to directly access system memory without CPU intervention in a computer system. DMA improves data transmission efficiency, reduces the burden of the CPU, and enables it to handle other tasks.

[0089] For example, the configuration of the descriptor of the DMA of the EP module can be completed by using AXI VIP as the master interface, the data carrying channel can include H2C and C2H channels, i.e. the control logic and the start address of the descriptor of the H2C / C2H are configured respectively, the H2C channel is enabled first to read the descriptor and complete the write from the EP module to the host storage space, and then the C2H channel is enabled to read the descriptor and complete the read from the host storage space to the EP module.

[0090] In addition, various error modes can be enabled for the configuration space of the EP module, including Correctable Error (correctable error), Non-Fatal Error (non-fatal error), Fatal Error (fatal error), Unsupported Requests Error (request not supported error), so that the PCIe device can send the corresponding ErrorMessages (error information) message. The Relaxed Order (relaxed order) mode of the PCIe device can also be enabled, so that the order of information transmission is relaxed, i.e. when the PCIe device transmits TLP (Transaction Layer Packet), the Attr field of the TLP can be set to Relaxed Ordering as needed. The size of the maximum Payload (payload) that the PCIe device can support, Max_Payload_Size, is set to 512 bytes. The I / O space (I / O space), memory space (memory space), and bus master register of the EP module are enabled, so that they can receive I / O transactions and memory (storage) transactions.

[0091] Meanwhile, the AXI LITE also needs to configure the BAR space of the EP module, for example, 32-bit ffffff is written to the BAR0, BAR1, BAR2, BAR3, BAR4, BAR5 and extended ROM BAR of the EP module respectively, the value of the BAR register is read in the form of masking, and the size of each BAR space is obtained according to the space position of the value f, and then the start addresses of the seven BAR spaces are assigned.

[0092] In the simulation of writing and reading to the DUT through the PCIE device, an initial operation request can be generated by the root node EP module, the initial operation request comprising a first write request or a first read request, the first write request comprising to-be-written data, used to instruct writing the to-be-written data to the host storage space of the DUT, and the first read request used to instruct reading data from the host storage space of the DUT. The first read request or the first write request can further comprise a first target address, used to instruct writing the to-be-written data to the first target address of the host storage space, or used to instruct reading data from the first target address of the host storage space.

[0093] Then, the initial operation request is converted into a to-be-executed operation request by the RC module, and the to-be-executed operation request is sent to the RNI of the DUT, so as to generate an operation message by the RNI, and send the operation message to the HNF of the DUT, so as to operate the first target address in the host storage space of the DUT by the HNF to obtain an operation result. The to-be-executed operation request is an AXI4 signal.

[0094] When the initial operation request comprises the first write request, the operation result is a write completion signal, that is, the simulation process is a write process. Specifically, the first write request is generated by the EP module, used to instruct writing the to-be-written data to the host storage space of the DUT, the first write request being a differential signal of PCIE, and then the RC module converts the first write request into a to-be-executed operation request (denoted as a to-be-operated write request), the to-be-executed write request being an AXI4 signal, the to-be-operated write request being sent to the RNI of the DUT, so as to generate an operation message (denoted as a write message, which is a message conforming to the CHI protocol) by the RNI, and send the write message to the HNF (for example, sending to the HNF through the NOC), and write the first target address by the HNF to obtain a write completion signal. The write message has configuration information, used to instruct whether it needs to satisfy the multi-core consistency, and through the snoop field corresponding to the writenosnp (not needing to satisfy the multi-core consistency) and writeunique (needing to satisfy the multi-core consistency) types, it can send different transactions for the multi-core consistency, so as to enrich the verification scene of the consistency. The write completion signal is sent from the HNF to the RNI, and then sent to the EP module through the RC module, and once DMA is completed, the EP module can send an MSI message to the RC module, and the RC module converts it into a line interrupt, and retains the interrupt type.

[0095] In the embodiments of the present application, a full consistency slave node (SNF) can be further included, which can be connected with the NOC. If the initial operation request comprises a first write request, the operation result obtained by operating the first target address in the host storage space through the HNF can be specifically a write completion signal obtained by performing a write operation on the first target address in the host cache in the host storage space through the HNF, or a write completion signal obtained by performing a write operation on the first target address in the host memory in the host storage space through the SNF by sending the operation packet to the SNF through the HNF. When performing the write operation on the host cache, the write operation can be performed on the l3 cache (the third level cache), that is, the HNF can write the data to be written into the l3 cache, or the HNF can forward the data to be written to the SNF so that the SNF writes the data to be written into the host memory.

[0096] In the embodiments of the present application, a full request node (RNF) can be further included, which can comprise a CPU core and the like, and the RNF can be connected to the NOC. The RC module can send a line interrupt to the RNF, so that the RNF can process the DMA carried data (that is, the data of the first target address) and complete the write operation of the EP module to the host storage space at a time.

[0097] When the initial operation request is a first read request, the operation result comprises first read data, that is, the simulation process is a read process. Specifically, the EP module generates a first read request for indicating to read the data of the host storage space of the device under test, the first read request is a differential signal of PCIE, and then the RC module performs format conversion on the first read request to obtain a to-be-executed operation request (denoted as a to-be-operated read request), the to-be-operuted read request is an AXI4 signal, the to-be-operated read request is sent to the RNI of the device under test, so that the RNI generates an operation packet (denoted as a read packet, which is a packet conforming to the CHI protocol) and sends the read packet to the HNF (for example, the read packet is sent to the HNF through the NOC), the HNF reads the first target address to obtain the first read data, and the first read data can be included in a read completion message. The read packet has configuration information for indicating whether it needs to satisfy the multi-core consistency, and the snoop field corresponds to readnosnp (not needing to satisfy the multi-core consistency) and readonce (needing to satisfy the multi-core consistency) types, so that different transactions for the multi-core consistency can be sent, thereby enriching the verification scene of the consistency. The first read data is sent from the HNF to the RNI, and then sent to the EP module through the RC module. After that, the EP module can send an MSI interrupt message to the RC module, and the RNF receives the interrupt to represent that the read operation from the host storage space to the EP module is completed at a time.

[0098] The HNF can read the first target address to obtain first read data. Specifically, the HNF can determine whether there is data meeting the requirement (i.e., data corresponding to the first target address) in the l3 cache according to the storage state of the l3 cache. If there is, the HNF reads the first target address in the l3 cache to obtain the first read data. If there is not, the HNF can query the storage state of the l2 cache (the second level cache) according to the snoop filter, and determine whether there is data meeting the requirement in the l2 cache. If there is, the HNF reads the first target address in the l2 cache to obtain the first read data. If there is not, the HNF reads the first target address in the host memory to obtain the first read data.

[0099] The first target address includes a first start address and a first field length, and the number of the first target addresses is multiple. The address ranges corresponding to the multiple first target addresses cover the read-write test range in the host storage space. In a specific implementation, in order to meet the simulation test requirements of cache consistency, a complete test case needs to be formulated. For the read and write requests of the external I / O device, the SAM table is first set, and the address range is divided so as to perfectly cover the read-write test range in the host storage space, for example, perfectly cover the read-write test range of the L3 cache. Each address offset of a cache line needs to be tested, so that all data transfer sizes of a cache line can be tested.

[0100] Through S101 and S102, the characteristics of the RNI external I / O device can be utilized, and the operation request can be sent to the device under test through the EP module and the RC module, so as to implement the operation on the data in the host storage space of the device under test.

[0101] In S103, the data of the first target address is obtained as first detection data.

[0102] In S104, if the initial operation request is the first write request, the first detection data and the data to be written are compared to obtain a first comparison result. If the initial operation request is the first read request, the first detection data and the first read data are compared to obtain a second comparison result.

[0103] After the write process or the read process is simulated by the PCIE device, the data of the first target address can be acquired as the first detection data, and the data of the first target address can be data written in the write process or data read in the read process. The data written or read by the PCIE device can be verified by taking the data as the first detection data. The first detection data can be acquired from the HNF after the HNF performs the data write operation, or can be acquired from the SNF after the SNF performs the data write operation, or can be obtained by reading the first target address through other modules.

[0104] After the first detection data is acquired, if the initial operation request is the first write request, a first comparison result can be obtained by comparing the first detection data and the to-be-written data, and the first comparison result is used to reflect IO consistency in the write process. If the initial operation request is the first read request, a second comparison result is obtained by comparing the first detection data and the first read data, and the second comparison result is used to reflect IO consistency in the read process of the PCIE device. That is, IO consistency in the write process and IO consistency in the read process can be automatically simulated and tested by the PCIE device, and consistency detection of the to-be-tested device based on the CHI protocol can be realized by the PCIE device, which has high testing efficiency and accuracy.

[0105] In the embodiments of the present application, the RNF module can also be added to the consistency verification platform, so that the IO consistency of the to-be-tested device can be more completely tested by combining the main memory transaction sent by the RNF and the device transaction sent by the PCIE device.

[0106] Specifically, before the write process is simulated, the RNF of the to-be-tested device can also perform a write operation on the first target address. In this way, the to-be-written data written in the simulated write process will cover the data written by the RNF, and the effectiveness of the PCIE device in rewriting the data of the first target address can be detected through the operations of S101-S104, and then the IO consistency of the to-be-tested device can be reflected.

[0107] Specifically, after the write process is simulated, the RNF can also perform a read operation on the first target address to obtain third read data, and a fifth comparison result is obtained by comparing the first detection data and the third read data, which is used to indicate the consistency of the RNF in reading the data of the first target address.

[0108] In the embodiments of the present application, the consistency verification platform can also include a direct memory access (DMA) module and a medium access control (MAC) module, which are described with reference to Figure 2As shown, both are treated as network cards to perform consistency verification on the device under test, that is, the device under test can be verified for consistency by at least one of the PCIE device and the network card. MAC refers to a layer of protocol responsible for managing and controlling data transmission in a computer network. The MAC layer is part of the data link layer, mainly responsible for communication management between multiple devices in a local area network or metropolitan area network.

[0109] Since ARM also provides a high-performance DMA IP core and an Ethernet MAC IP core, the process of receiving data by the network end can be simulated using the DMA IP core and the MAC IP core. The DMA module selects the IP (AXI DMA) of ARM, which is used to carry data between the network port and the host storage space, can convert the AXI stream data stream obtained from the MAC module into an AXI4 data stream, and convert the AXI4 data stream into an AXI stream data stream and send it to the MAC module. The MAC module selects the IP (Tri-Mode Ethernet MAC v9.0) of ARM, which is the MAC layer IP core of the Ethernet (ethernet), can be connected to the physical (Physical, PHY) layer of the external port, and can loop back the differential signal. In this way, by using the IP core of ARM, an efficient consistency verification platform can be constructed to verify the IO consistency of the multi-core processor.

[0110] The MAC module enables configuration through a configuration interface (referred to as a second configuration interface) to achieve configuration. The configuration interface can select AXI Verification IP, thereby realizing register configuration excitation of the MAC module. For example, the AXI VIP of the AXI LITE interface with 32-bit address and data bit width can be selected as the register configuration excitation of the MAC module. When configuring the MAC module, in order to achieve flow control, the MAC source address of the pause frame is set, the receiver is started and reset, the frame filter is configured, and the correct MAC address is ensured to be received.

[0111] The DMA module completes configuration implementation enabling through a configuration interface (denoted as a third configuration interface). The configuration interface can select AXI Verification IP, thereby realizing register configuration excitation of the DMA module. For example, AXI VIP of an AXI LITE interface with 32-bit address and data bit width can be selected as register configuration excitation of the DMA module. The DMA module is configured with descriptor and data carrying channel control logic of the DMA, so as to realize DMA data carrying. For example, a Current Descriptor Pointer can be configured to specify an address of a current descriptor, a Tail Descriptor Pointer can be configured to specify an address of a last descriptor, and the data carrying channel can include S2MM and MM2S channels, that is, an S2MM DMA Control Register is configured to enable transmission of a stream to memory (S2MM, MAC module to host storage space) of the DMA, and an interrupt threshold is set, and an MM2S DMA Control Register is configured to enable transmission of memory to stream (MM2S, host storage space to MAC module) of the DMA, and an interrupt threshold is set.

[0112] When writing and reading simulation of the device under test is performed through the network card, S201 can be performed to realize writing simulation, S202-S204 can be performed to realize reading simulation, and S205-S206 can be performed to realize consistency detection. For details, refer to Figure 3

[0113] S201, reading operation is performed on a second target address in the host storage space according to a configured reading descriptor through the DMA module, to obtain second reading data.

[0114] Specifically, the reading descriptor can be MM2SDescriptor data, which records a load address. The load address is taken as the second target address, and the second reading data can be read from the host storage space, for example, a host memory.

[0115] ​The process of obtaining the second read data by performing a read operation on the second target address by the DMA module can specifically be that the DMA module generates a second read request for instructing to read data in the host storage space of the device under test, the second read request can be an AXI4 signal, the second read request is sent to the RNI of the device under test, so that the RNI generates a read message which is a message conforming to the CHI protocol, and sends the read message to the HNF (for example, sends to the HNF through the NOC), and the HNF performs a read operation on the second target address to obtain the second read data, which can be included in a read completion message. The data read process of the RNI and the HNF can refer to the description of the foregoing data read process through the PCIE device, and will not be described here.

[0116] S202, sending the second read data to the MAC module by the DMA module.

[0117] S203, sending a second write request including the second read data to the DMA module by the MAC module.

[0118] S204, performing a write operation on a third target address in the host storage space by the DMA module according to the configured write descriptor.

[0119] Specifically, after obtaining the second read data, the DMA module can send the second read data in the form of AXI stream data stream to the MAC module. The MAC module performs data loopback, and takes the second read data as new data to be written. The second write request is used to instruct to write the second read data to the host storage space (i.e., the third target address) of the device under test, and the second write request is an AXI stream data stream. After the MAC module sends the second write request to the DMA module, the DMA module converts the AXI stream data stream into an AXI4 data stream. The write descriptor can be a Descriptor data of the S2MM, which can record a load address. The load address is taken as the third target address, and the second read data can be written into the host storage space such as a host memory, to complete the whole IO transmission.

[0120] The process of performing a write operation on the third target address by the DMA module can specifically be that the DMA module sends the second write request after format conversion to the RNI of the device under test, so that the RNI generates a write message which is a message conforming to the CHI protocol, and sends the write message to the HNF (for example, sends to the HNF through the NOC), and the HNF performs a write operation on the third target address. The data write process of the RNI and the HNF can refer to the description of the foregoing data write process through the PCIE device, and will not be described here.

[0121] S205, acquire data of the second target address as second detection data, and acquire data of the third target address as third detection data.

[0122] S206, compare the second detection data with second read data to obtain a third comparison result, and compare the third detection data with the second read data to obtain a fourth comparison result.

[0123] After the simulation of the write process and the read process by the network card, the data of the second target address can be acquired as the second detection data, and the data of the third target address can be acquired as the third detection data. The second detection data is compared with the second read data to obtain the third comparison result, which is used to reflect the IO consistency in the write process of the network card. The third detection data is compared with the second read data to obtain the fourth comparison result, which is used to reflect the IO consistency in the read process of the network card. The consistency detection of the device under test based on the CHI protocol by the network card is realized, and the test efficiency and accuracy are high.

[0124] The second target address includes a second start address and a second field length, the number of the second target addresses is multiple, and the address ranges corresponding to the multiple second target addresses cover the read-write test range in the host storage space. The third target address includes a third start address and a third field length, the number of the third target addresses is multiple, and the address ranges corresponding to the multiple third target addresses cover the read-write test range in the host storage space.

[0125] In the embodiments of the application, the consistency verification can also be performed by the RNF module in combination with the network card. Specifically, after S202, the RNF can perform a read operation on the second target address to obtain fourth read data, and the second detection data is compared with the fourth read data to obtain a sixth comparison result, which is used to indicate the consistency of the read operation of the RNF on the data of the second target address. The RNF can also perform a read operation on the third target address to obtain fifth read data, and the second detection data is compared with the fifth read data to obtain a seventh comparison result, which is used to indicate the consistency of the read operation of the RNF on the data of the third target address.

[0126] Specifically, before S203, the RNF of the device under test can also perform a write operation on the third target address. In this way, the second read data written in the simulation write process will cover the data written by the RNF, and the operations of S202-S206 can detect the effectiveness of the rewriting of the data of the third target address by the PCIE device, and thus the IO consistency of the device under test is reflected.

[0127] In the embodiments of the present application, more test case requirements can be proposed for the consistency verification platform, a large number of smoke tests and random tests are increased, and the test reliability is improved. The first target address, the second target address and the third target address can be the same address or different addresses, so that the data is updated through multiple write operations at different times, and the data is obtained through multiple read operations at different times, and the test reliability can be improved.

[0128] The calling of the modules in the consistency verification platform in the above steps can be automatically realized through a script, that is, the script can be used for automatic testing. The multi-core system and the complex I / O operation result in a very complex test scene. A large number of repetitive complete tests are required. The present project selects a combination test method, including UVM unit-level testing, vivado system-level testing and FPGA board-level testing. The board-level testing depends on specific hardware platforms for testing, which may increase the cost and complexity. The embodiments of the present application describe the simulation testing in the FPGA board-level testing, which combines hardware simulation and software simulation, fully utilizes the advantages of FPGA and software simulator, and reduces the hardware dependency. At the same time, the automatic tool and the script are used to execute the hardware testing to verify the function, performance and reliability. The test efficiency, coverage and accuracy are improved.

[0129] The embodiments of the present application provide a consistency verification method. An initial operation request is generated through a root node EP module. The initial operation request can include a first write request or a first read request. The first write request includes to-be-written data. The initial operation request is a PCIE signal of a high-speed serial computer expansion bus standard. A to-be-executed operation request is obtained by performing format conversion on the initial operation request through a root complex RC module. The to-be-executed operation request is an AXI4 signal. The to-be-executed operation request is sent to an IO consistency request node RNI of a to-be-tested device, so as to generate an operation message through the RNI, and send the operation message to a full consistency master node HNF of the to-be-tested device, so as to perform operation on a first target address in a host storage space of the to-be-tested device through the HNF to obtain an operation result. When the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address. When the initial operation request is a read request, the operation result includes first read data of the first target address. In this way, by using the characteristics of the RNI external I / O device, the EP module and the RC module, which are two PCIE devices, can send operation requests to the to-be-tested device, and the operation on the data in the host storage space of the to-be-tested device is realized.

[0130] After the operation on the host storage space, data of the first target address can be acquired as first detection data, if the initial operation request is the first write request, a first comparison result is obtained by comparing the first detection data and the to-be-written data, which is used to reflect the IO consistency in the write process, if the initial operation request is the first read request, a second comparison result is obtained by comparing the first detection data and the first read data, which is used to reflect the IO consistency in the read process. That is, through the PCIE device, the IO consistency in the write process and the IO consistency in the read process can be automatically simulated and tested, the consistency detection of the to-be-tested device based on the CHI protocol is realized, and high testing efficiency and accuracy are achieved.

[0131] Based on the above consistency verification method, the embodiment of the application further provides a consistency verification device, as shown in Figure 4 The structure block diagram of the consistency verification device provided by the embodiment of the application can include:

[0132] The operation request generation unit 110 is configured to generate an initial operation request through a root node EP module, the initial operation request includes a first write request or a first read request, the first write request includes to-be-written data, and the initial operation request is a PCIE signal of a high-speed serial computer expansion bus standard.

[0133] The operation request sending unit 120 is configured to perform format conversion on the initial operation request through a root complex RC module to obtain a to-be-executed operation request, and send the to-be-executed operation request to an IO consistency request node RNI of a to-be-tested device, so as to generate an operation message through the RNI, and send the operation message to a full consistency master node HNF of the to-be-tested device, so as to perform operation on a first target address in a host storage space of the to-be-tested device through the HNF to obtain an operation result; the to-be-executed operation request is an AXI4 signal, when the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address, and when the initial operation request is a read request, the operation result includes first read data of the first target address.

[0134] The first detection data acquisition unit 130 is configured to acquire data of the first target address as first detection data.

[0135] The first comparison unit 140 is configured to, if the initial operation request is the first write request, compare the first detection data and the to-be-written data to obtain a first comparison result, and if the initial operation request is the first read request, compare the first detection data and the first read data to obtain a second comparison result.

[0136] Optionally, the RC module is enabled for PCIE configuration through a configuration interface, and the EP module is enabled for configuration through a management interface connected with the RC module, and the EP module is configured with a descriptor of direct memory access (DMA) and data transfer channel control logic to realize DMA data transfer.

[0137] Optionally, the apparatus further comprises:

[0138] a first reading unit configured to perform a reading operation on the second target address in the host storage space according to a configured reading descriptor through a direct memory access (DMA) module to obtain second reading data;

[0139] a reading data sending unit configured to send the second reading data to a media access control (MAC) module through the DMA module;

[0140] a write request sending unit configured to send a second write request including the second reading data to the DMA module through the MAC module;

[0141] a first writing unit configured to perform a writing operation on a third target address in the host storage space according to a configured writing descriptor through the DMA module;

[0142] a second detection data obtaining unit configured to obtain data of the second target address as second detection data and data of the third target address as third detection data;

[0143] a second comparing unit configured to compare the second detection data with the second reading data to obtain a third comparison result and compare the third detection data with the second reading data to obtain a fourth comparison result.

[0144] Optionally, the MAC module is enabled for configuration through a configuration interface, and the DMA module is enabled for configuration through the configuration interface, and the DMA module is configured with a descriptor of DMA and data transfer channel control logic to realize DMA data transfer.

[0145] Optionally, if the initial operation request is a write request, the apparatus further comprises:

[0146] a second writing unit configured to perform a writing operation on the first target address through a full request node (RNF) of the device under test before sending the operation request to be executed to the RNI node of the device under test;

[0147] and / or,

[0148] a second reading unit, configured to perform a reading operation on the first target address in the host storage space through the RNF to obtain third reading data after the operation result is obtained by performing the operation on the first target address in the host storage space through the HNF;

[0149] a third comparison unit, configured to compare the first detection data and the third reading data to obtain a fifth comparison result.

[0150] Optionally, the RNI and the HNF communicate through a network on chip (NOC), the RNF is connected to the NOC, and the NOC is also connected to a full-coherent slave node (SNF) of the DUT.

[0151] If the initial operation request includes a first write request, the operation result is obtained by performing the operation on the first target address in the host storage space through the HNF, including:

[0152] the write completion signal is obtained by performing the write operation on the first target address in the host cache in the host storage space through the HNF;

[0153] or, the write completion signal is obtained by performing the write operation on the first target address in the host memory in the host storage space through the SNF by sending the operation packet to the SNF through the HNF.

[0154] Optionally, the host storage space includes a host memory or a host cache, the first target address includes a first start address and a first field length, the number of the first target addresses is a plurality, and the address ranges corresponding to the plurality of first target addresses cover a read-write test range in the host storage space.

[0155] In addition, the embodiment of the application further provides a consistency verification platform, as shown in Figure 2 , including:

[0156] a root node EP module and a root complex RC module;

[0157] a verification module configured to execute the consistency verification method of the first aspect.

[0158] Optionally, the consistency verification platform further includes:

[0159] a first configuration interface configured to complete PCIE configuration of the RC module to enable the RC module;

[0160] a management interface connected to the RC module, configured to complete configuration of the EP module to enable the EP module; the EP module is configured with a descriptor of direct memory access (DMA) and data transfer channel control logic to implement DMA data transfer.

[0161] Optionally, the consistency verification platform further comprises:

[0162] a direct memory access (DMA) module and a media access control (MAC) module.

[0163] Optionally, the consistency verification platform further comprises:

[0164] a second configuration interface for completing configuration of the MAC module to enable the MAC module;

[0165] a third configuration interface for completing configuration of the DMA module to enable the DMA module, the DMA module being configured with a descriptor of the DMA and data transfer channel control logic to implement DMA data transfer.

[0166] Referring to Figure 5 , Figure 5 A structural block diagram of a computer device for consistency verification is provided in the embodiments of the present application. The computer device comprises a processor 710 and a memory 720:

[0167] The memory 720 is configured to store program code and transmit the program code to the processor 710.

[0168] The processor 710 is configured to execute the consistency verification method according to the instructions in the program code.

[0169] The embodiments of the present application also disclose a computer readable storage medium for storing a computer program, the computer program being configured to execute the consistency verification method according to any of the implementation manners of the above embodiments when executed by a processor.

[0170] From the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on such an understanding, the technical solutions of the present application can be embodied in the form of a software product. The computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in the various embodiments or some parts of the embodiments.

[0171] It should be noted that the various embodiments described in the specification are intended to be exemplary only and that the scope of the application is not intended to be limited to the embodiments described in the specification. Rather, the scope of the application is intended to cover all modifications and variations of the exemplary methods and techniques described herein as would be apparent to those of ordinary skill in the art. The embodiments disclosed in the specification and / or claims are intended to be merely exemplary and are subject to change. It is intended that only those changes and modifications that are particular to a particular embodiment be excluded. It is intended that the following claims be construed to include all such changes and modifications as fall within the true spirit and scope of the application.

[0172] It should also be noted that the various embodiments described in the specification are intended to be exemplary only and that the scope of the application is not intended to be limited to the embodiments described in the specification. Rather, the scope of the application is intended to cover all modifications and variations of the exemplary methods and techniques described herein as would be apparent to those of ordinary skill in the art. The embodiments disclosed in the specification and / or claims are intended to be merely exemplary and are subject to change. It is intended that only those changes and modifications that are particular to a particular embodiment be excluded. It is intended that the following claims be construed to include all such changes and modifications as fall within the true spirit and scope of the application.

[0173] The above description is only preferred embodiments of the present application, and the present application is not limited to the above embodiments. Any person skilled in the art, without departing from the scope of the present application, can make many possible changes and modifications to the above disclosed methods and technical contents, or modify equivalent embodiments. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the scope of the present application, are still within the scope of protection of the present application.

Claims

1. A method of consistency verification, characterized by, The method comprises: generating an initial operation request by a root node EP module, the initial operation request comprising a first write request or a first read request, the first write request comprising to-be-written data, the initial operation request being a PCIE signal; format-converting the initial operation request by a root complex RC module to obtain a to-be-executed operation request, and sending the to-be-executed operation request to an IO consistency request node RNI of the device under test, so as to generate an operation message by the RNI, and send the operation message to a home node full consistency HNF of the device under test, so as to operate a first target address in a host storage space of the device under test by the HNF to obtain an operation result; the to-be-executed operation request being an AXI4 signal, when the initial operation request is a write request, the operation result being a write completion signal of writing the to-be-written data into the first target address, when the initial operation request is a read request, the operation result comprising first read data of the first target address; obtaining data of the first target address as first detection data; if the initial operation request is a first write request, comparing the first detection data and the to-be-written data to obtain a first comparison result; if the initial operation request is a first read request, comparing the first detection data and the first read data to obtain a second comparison result.

2. The method of claim 1, wherein, The RC module enables PCIE configuration through a configuration interface, the EP module enables configuration through a management interface connected with the RC module, and the EP module is configured with a descriptor of direct memory access (DMA) and data transfer channel control logic to realize DMA data transfer.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: reading a second target address in the host storage space according to a configured read descriptor by a direct memory access (DMA) module to obtain second read data; sending the second read data to a medium access control (MAC) module by the DMA module; sending a second write request comprising the second read data to the DMA module by the MAC module; writing a third target address in the host storage space according to a configured write descriptor by the DMA module; obtaining data of the second target address as second detection data, and obtaining data of the third target address as third detection data; comparing the second detection data and the second read data to obtain a third comparison result, and comparing the third detection data and the second read data to obtain a fourth comparison result.

4. The method of claim 3, wherein, The MAC module enables configuration through a configuration interface, the DMA module enables configuration through a configuration interface, and the DMA module is configured with a descriptor of DMA and data transfer channel control logic to realize DMA data transfer.

5. The method according to claim 1 or 2, characterized in that, If the initial operation request is a write request, before the to-be-executed operation request is sent to the RNI node of the device under test, the method further comprises: writing the first target address by a home request node RNF of the device under test; And / or, after the operation result is obtained by operating the first target address in the host storage space through the HNF, the method further comprises: reading operation is performed on the first target address through the RNF to obtain third read data; comparing the first detection data and the third read data to obtain a fifth comparison result.

6. The method of claim 5, wherein, The RNI and the HNF communicate through a network on chip (NOC), the RNF is connected to the NOC, and the NOC is also connected to a full consistency slave node (SNF) of the device under test; If the initial operation request includes a first write request, an operation result is obtained by operating a first target address in the host storage space through the HNF, comprising: write operation is performed on the first target address in the host cache in the host storage space through the HNF to obtain a write completion signal; Or, the operation message is sent to the SNF through the HNF, so that the write operation is performed on the first target address in the host memory in the host storage space through the SNF to obtain a write completion signal.

7. The method according to claim 1 or 2, characterized in that, The host storage space includes a host memory or a host cache, the first target address includes a first start address and a first field length, the number of the first target address is multiple, and the address range corresponding to multiple first target addresses covers the read-write test range in the host storage space.

8. A consistency verification apparatus characterized by comprising: Comprising: An operation request generation unit is configured to generate an initial operation request through a root node (EP) module, the initial operation request includes a first write request or a first read request, the first write request includes to-be-written data, and the initial operation request is a high-speed serial computer expansion bus standard (PCIE) signal; An operation request sending unit is configured to convert the initial operation request into a to-be-executed operation request through a root complex (RC) module, and send the to-be-executed operation request to an IO consistency request node (RNI) of the device under test, so that the RNI generates an operation message, and sends the operation message to a full consistency master node (HNF) of the device under test, so that the HNF operates a first target address in a host storage space of the device under test to obtain an operation result; the to-be-executed operation request is an AXI4 signal, when the initial operation request is a write request, the operation result is a write completion signal of writing the to-be-written data into the first target address, and when the initial operation request is a read request, the operation result includes first read data of the first target address; A first detection data acquisition unit is configured to acquire data of the first target address as first detection data; A first comparison unit is configured to compare the first detection data and the to-be-written data to obtain a first comparison result if the initial operation request is a first write request, and compare the first detection data and the first read data to obtain a second comparison result if the initial operation request is a first read request.

9. The apparatus of claim 8, wherein, The device further comprises: The first reading unit is configured to perform a reading operation on the second target address in the host storage space to obtain second reading data according to a configured reading descriptor through a direct memory access (DMA) module. The reading data sending unit is configured to send the second reading data to a media access control (MAC) module through the DMA module. The write request sending unit is configured to send a second write request including the second reading data to the DMA module through the MAC module. The first writing unit is configured to perform a writing operation on a third target address in the host storage space according to a configured writing descriptor through the DMA module. The second detection data obtaining unit is configured to obtain data of the second target address as second detection data and obtain data of the third target address as third detection data. The second comparison unit is configured to compare the second detection data with the second reading data to obtain a third comparison result and compare the third detection data with the second reading data to obtain a fourth comparison result.

10. The apparatus of claim 8 or 9, wherein, If the initial operation request is a write request, the apparatus further includes: The second writing unit is configured to perform a writing operation on the first target address through a full request node (RNF) of the device under test before the RNI node of the device under test sends the operation request to be executed. And / or, The second reading unit is configured to perform a reading operation on the first target address through the RNF to obtain third reading data after the HNF performs an operation on the first target address in the host storage space. The third comparison unit is configured to compare the first detection data with the third reading data to obtain a fifth comparison result.

11. A conformity verification platform, characterized by, The apparatus includes: A root node (EP) module and a root complex (RC) module. The verification module is configured to perform the consistency verification method in any one of claims 1-7.

12. The conformance verification platform of claim 11, wherein, The apparatus further includes: A direct memory access (DMA) module and a media access control (MAC) module.

13. A computer device, comprising: The computer device includes a processor and a memory: The memory is configured to store program code and transmit the program code to the processor. The processor is configured to execute the consistency verification method in any one of claims 1-7 according to instructions in the program code.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium is configured to store a computer program, which, when executed by a processor, is configured to execute the consistency verification method in any one of claims 1-7. The computer readable storage medium is configured to store a computer program, which, when executed by a processor, is configured to execute the consistency verification method in any one of claims 1-7.

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