Semiconductor device manufacturing method, semiconductor device and testing method
By forming and removing the peel layer on the interconnected structure surface of the semiconductor device, the raised problems caused by machine heat are solved, the test stability and electrical performance are improved, and the wafer yield loss is reduced.
Patent Information
- Application Number
- CN202411110156.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-14
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2044-08-14
AI Technical Summary
During the WAT process of semiconductor devices, due to thermal instability of the machine, the surface of the interconnect structure forms protrusions, causing electrical test results to drift, reduce wafer yield, and even cause wafer scrapping.
The stripping layer is formed on the surface of the interconnect structure, which wraps and covers the protrusions. The interconnection structure surface is planarized by removing the stripping layer and element detection is performed during the removal to prevent overetching, dry etching and annealing are used to use Steps to repair possible damage.
Effectively avoid test results drift caused by the convexity of the interconnected structure surface, reduce the loss of wafer yield, improve the electrical performance of the device, and ensure complete wrapping and removal of the peeling layer through the use of borosilicate glass layer , prevent overetching.
Smart Images
Figure CN118658835B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method for preparing a semiconductor device, a semiconductor device and a testing method. Background Art
[0002] The semiconductor manufacturing process usually includes the front-end process, the back-end process and the WAT (Wafer Acceptance Test) process. WAT is used to test the electrical properties of the device, which is performed after the back-end process is completed. WAT is tested by directly contacting the probe of the probe card with the interconnection structure of the wafer to ensure that the wafer can operate normally during subsequent manufacturing and use.
[0003] However, due to the influence of thermal instability of the machine, protrusions usually form on the surface of the interconnect structure, which will cause the electrical test results to drift, thereby causing wafer degradation. In severe cases, the wafer may even be directly scrapped, resulting in a loss of wafer yield. Summary of the invention
[0004] In view of the above problems, the purpose of the present application is to provide a method for preparing a semiconductor device, a semiconductor device and a testing method, so as to trim the surface of the interconnect structure, thereby improving the yield and electrical performance of the semiconductor device.
[0005] According to one aspect of the present invention, there is provided a method for preparing a semiconductor device, comprising: forming an interconnect structure and a passivation layer covering the interconnect structure on a semiconductor layer; forming a window exposing the interconnect structure, wherein the surface exposed by the interconnect structure has a protrusion; forming a stripping layer, wherein the stripping layer at least covers the surface of the interconnect structure exposed by the window and wraps the protrusion on the surface of the interconnect structure; and removing the stripping layer and the protrusion wrapped by the stripping layer, so that the interconnect structure exposed by the window has a flat surface.
[0006] Optionally, the peeling layer is a doped layer.
[0007] Optionally, the peeling layer is a borophosphosilicate glass layer.
[0008] Optionally, a thickness of the release layer is greater than a height of protrusions on the surface of the interconnect structure.
[0009] Optionally, the lift-off layer has a thickness less than 15000 angstroms.
[0010] Optionally, during the process of removing the stripping layer, element detection is simultaneously performed on the surface exposed by the window, wherein when it is detected that the surface exposed by the window contains boron element and / or phosphorus element, the stripping layer continues to be removed; when it is detected that the surface exposed by the window contains no boron element and / or phosphorus element, the stripping layer removal is stopped.
[0011] Optionally, the stripping layer is removed by dry etching, and a mixed gas containing fluorine and chlorine is used as the etching gas.
[0012] Optionally, after forming the peeling layer, an annealing step is also included.
[0013] According to another aspect of the present invention, a semiconductor device is provided. The semiconductor device is formed according to the above-mentioned manufacturing method.
[0014] According to another aspect of the present invention, a method for testing a semiconductor device is provided, comprising: forming a semiconductor device using the above-mentioned preparation method, wherein an interconnect structure exposed by a window in the semiconductor device has a flat surface; and contacting the interconnect structure through the window with a probe for testing.
[0015] The unexpected technical effects of this application are:
[0016] According to the semiconductor device manufacturing method, semiconductor device and testing method of the embodiment of the present invention, a peeling layer is formed on the surface of the interconnection structure, so that the peeling layer wraps the protrusions on the surface of the interconnection structure, and then the protrusions on the surface of the interconnection structure are removed while removing the peeling layer, so as to flatten the surface of the interconnection structure. In the test process of the semiconductor device, the drift of the test results caused by the protrusions on the surface of the interconnection structure is avoided, and the loss of wafer yield is reduced. At the same time, the flattening of the surface of the interconnection structure improves the electrical performance of the device.
[0017] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, the stripping layer is a borosilicate glass layer. The borosilicate glass at high temperature has fluidity, so that the stripping layer can completely wrap the protrusions on the surface of the interconnection structure, so that the protrusions are removed together with the stripping layer.
[0018] According to the semiconductor device manufacturing method, semiconductor device and testing method of the embodiments of the present invention, the thickness of the peeling layer is greater than the height of the protrusions on the surface of the interconnect structure, so that the peeling layer can completely cover the height of the protrusions on the surface of the interconnect structure.
[0019] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, element detection is performed on the surface of the interconnect structure while removing the stripping layer to prevent over-etching and further prevent the loss of interconnect structure size.
[0020] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, after the stripping layer is formed, an annealing step is also included to repair the damage that may be caused by the stripping layer formation process, and further prevent the damage caused by the stripping layer formation from affecting subsequent steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:
[0022] Figure 1 A schematic cross-sectional view of a semiconductor device is shown;
[0023] Figure 2 A method for preparing a semiconductor device according to an embodiment of the present invention is shown;
[0024] Figures 3a to 3e The cross-sectional views at various stages of the semiconductor device manufacturing process according to the embodiment of the present invention are shown, wherein:
[0025] Figure 3a A schematic structural diagram of a semiconductor device after an interconnection layer and a passivation layer are sequentially formed on a semiconductor layer is shown;
[0026] Figure 3b A schematic structural diagram of a semiconductor device after a window is formed is shown;
[0027] Figure 3c A schematic diagram showing the structure of a semiconductor device after a peeling layer is formed;
[0028] Figure 3d A schematic structural diagram of a semiconductor device with a portion of a peeling layer and a portion of a protrusion removed is shown;
[0029] Figure 3e A schematic diagram of the structure of a semiconductor device with the peeling layer and the protrusions completely removed is shown;
[0030] Figure 4 A schematic diagram of performing electrical testing on a semiconductor device in a specific embodiment is shown;
[0031] Figure 5 A method for testing a semiconductor device according to an embodiment of the present invention is shown;
[0032] Figure 6a A schematic structural diagram of a semiconductor device after a window is formed is shown;
[0033] Figure 6b A schematic diagram showing the structure of a semiconductor device after a peeling layer is formed;
[0034] Figure 6c A schematic structural diagram of a semiconductor device with a portion of a peeling layer and a portion of a protrusion removed is shown;
[0035] Figure 6dA schematic diagram of the structure of a semiconductor device with the peeling layer and the protrusions completely removed is shown;
[0036] Figure 6e A schematic diagram showing a probe contacting an interconnect structure through a window for testing.
[0037] Figure 7a A schematic diagram showing the force on the surface of the interconnection structure when the probe contacts the surface of the interconnection structure when the surface of the interconnection structure is smooth;
[0038] Figure 7b The schematic diagram shows the force on the surface of the interconnect structure when the probe contacts the surface of the interconnect structure when the surface of the interconnect structure has protrusions. DETAILED DESCRIPTION
[0039] The present application will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown.
[0040] This application may be presented in a variety of forms, some examples of which are described below.
[0041] Figure 1 1 shows a schematic cross-sectional view of a semiconductor device. The semiconductor device 100 is, for example, a MOSFET (ie, a metal oxide semiconductor field effect transistor), but is not limited thereto. In a preferred embodiment, the semiconductor device is, for example, an N-type MOSFET. Figure 1 As shown, the semiconductor device 100 includes a semiconductor layer 110 , an interconnection layer 120 located on the semiconductor layer 110 , and a passivation layer 130 covering the interconnection layer 120 .
[0042] The semiconductor layer 110 includes a semiconductor substrate 111, a source region 112 and a drain region 113 located in the semiconductor substrate 111, and a gate stack located above the semiconductor substrate 111. The semiconductor substrate 111 may be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor substrate 111 is P-type doped; for a P-type MOSFET, the semiconductor substrate 111 is N-type doped. The source region 112 and the drain region 113 are doped regions in the semiconductor substrate 111. For example, for an N-type MOSFET, the source region 112 and the drain region 113 are N-type doped; for a P-type MOSFET, the source region 112 and the drain region 113 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 114 and a gate conductor 115, wherein the gate dielectric layer 114 is sandwiched between the semiconductor substrate 111 and the gate conductor 115. The gate dielectric layer 114 is composed of, for example, silicon oxide, and the gate conductor 115 is composed of, for example, doped polysilicon.
[0043] The interconnection layer 120 includes an interlayer dielectric layer 121 located above the semiconductor layer 110, and an interconnection structure 122 located inside the interlayer dielectric layer 121. The interlayer dielectric layer 121 is composed of, for example, silicon oxide, and is used to isolate the active region of the semiconductor device 100 from the interconnection structure 122. The interconnection structure 122 includes one or more layers of wiring 1221 and a connection channel 1222, wherein the connection channel 1222 connects the wiring 1221 with the gate stack, the source region 112 and the drain region 113, or connects the wiring 1221 of the adjacent layer. The connection channel 1222 and the wiring 1221 may be composed of metal, such as copper, aluminum, etc.
[0044] The passivation layer 130 covers the interconnection layer 120 and is used to protect the interconnection layer 120. The passivation layer 130 has a window 131 to expose at least part of the surface of the interconnection structure 122 through the window 131. The passivation layer 130 is, for example, a silicon oxide (SiO2) layer, a silicon nitride (SiN) layer, or a composite layer of silicon oxide and silicon nitride (SiN). In one embodiment, the passivation layer 130 is, for example, a silicon nitride (SiN) layer.
[0045] Figure 2 A method for preparing a semiconductor device according to an embodiment of the present invention is shown. Figures 3a to 3e The cross-sectional views of various stages in the process of preparing a semiconductor device according to an embodiment of the present invention are shown. Figure 2 as well as Figures 3a to 3e A method for testing a semiconductor device according to an embodiment of the present invention is described.
[0046] like Figure 2 as well as Figure 3a As shown, in step S100 , an interconnection layer 120 and a passivation layer 130 covering the interconnection layer 120 are formed on the semiconductor layer 110 .
[0047] The semiconductor layer 110 includes a semiconductor substrate 111, a source region 112 and a drain region 113 located in the semiconductor substrate 111, and a gate stack located above the semiconductor substrate 111. The semiconductor substrate 111 may be composed of any one of a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. For example, for an N-type MOSFET, the semiconductor substrate 111 is P-type doped; for a P-type MOSFET, the semiconductor substrate 111 is N-type doped. The source region 112 and the drain region 113 are doped regions in the semiconductor substrate 111. For example, for an N-type MOSFET, the source region 112 and the drain region 113 are N-type doped; for a P-type MOSFET, the source region 112 and the drain region 113 are P-type doped. The gate stack of the semiconductor device 100 includes a gate dielectric layer 114 and a gate conductor 115, wherein the gate dielectric layer 114 is sandwiched between the semiconductor substrate 111 and the gate conductor 115. The gate dielectric layer 114 is composed of, for example, silicon oxide, and the gate conductor 115 is composed of, for example, doped polysilicon.
[0048] The interconnection layer 120 includes an interlayer dielectric layer 121 located above the semiconductor layer 110, and an interconnection structure 122 located inside the interlayer dielectric layer 121. The interlayer dielectric layer 121 is composed of, for example, silicon oxide, and is used to isolate the active region of the semiconductor device 100 from the wiring structure. The interconnection structure 122 includes one or more layers of wiring 1221 and a connection channel 1222, wherein the connection channel 1222 connects the wiring 1221 with the gate stack, the source region 112 and the drain region 113, or connects the wiring 1221 of the adjacent layer. The connection channel 1222 and the wiring 1221 can be composed of metal, such as copper, aluminum, etc.
[0049] The passivation layer 130 covers the interconnection layer 120 to protect the interconnection layer 120 .
[0050] like Figure 2 as well as Figure 3b As shown, in step S110 , a window 131 exposing the interconnect structure 122 is formed, wherein the exposed surface of the interconnect structure 122 has a protrusion 123 .
[0051] In this step, for example, a photolithography and etching process is used to form a window 131 in the passivation layer 130 , and the window 131 exposes the top of the interconnection structure 122 .
[0052] The material of the top of the interconnect structure 122 is usually aluminum (AL), and the material of the interlayer dielectric layer 121 is usually silicon oxide (SiO2). The thermal expansion coefficient of aluminum (AL) is 23.2E-6 / °C, and the thermal expansion coefficient of silicon oxide (SiO2) is 0.55E-6 / °C. Since the expansion coefficient of aluminum (AL) is greater than that of silicon oxide (SiO2), during the formation of the window 131, affected by the thermal instability of the machine, the deformation of the top of the interconnect structure 122 is greater than the deformation of the interlayer dielectric layer 121, and then the protrusion 123 is formed on the surface of the interconnect structure 122 exposed by the window 131. In one embodiment, for example, at a high temperature of 400°C, the interlayer dielectric layer 121 (SiO2) is almost not deformed, and the deformation of the interconnect structure 122 (AL) is greater than the deformation of the interlayer dielectric layer 121 (SiO2). Due to the compression of the interlayer dielectric layer 121 (SiO2), the surface lattice of the interconnect structure 122 exposed by the window 131 is raised.
[0053] See also Figure 2 as well as Figure 3c In step S120 , a peeling layer 140 is formed. The peeling layer 140 at least covers the surface of the interconnection structure 122 exposed by the window 131 and wraps the protrusions 123 on the surface of the interconnection structure 122 .
[0054] In this step, for example, a deposition process is used to form a peeling layer 140 on the surface of the passivation layer 130, the sidewalls of the window 131, and the surface of the interconnection structure 122 exposed through the window 131. In this embodiment, the peeling layer 140 conformally covers the surface of the passivation layer 130, the sidewalls of the window 131, and the surface of the interconnection structure 122 exposed through the window 131, and wraps the protrusion 123 on the surface of the interconnection structure 122.
[0055] The stripping layer 140 is a doped layer, preferably a doped layer of phosphorus and / or boron. In one embodiment, the stripping layer 140 is, for example, a borophospho-silicate glass (BPSG) layer. The thickness of the stripping layer 140 is greater than the height of the protrusion 123, so that the stripping layer 140 completely covers the protrusion 123. Further, the thickness of the stripping layer 140 is less than 15,000 angstroms to prevent the stripping layer 140 from being too thick, which increases the difficulty of etching during the removal of the stripping layer 140. In one embodiment, the thickness of the stripping layer 140 is, for example, 5,000 angstroms. Borophospho-silicate glass has a certain fluidity at high temperature, and the stripping layer 140 formed can completely wrap the protrusion 123 on the surface of the interconnect structure 122.
[0056] See also Figure 2 In step S130, after the peeling layer 140 is formed, the device is annealed.
[0057] In order to prevent the process of forming the peeling layer 140 from causing damage to the device, the present application adds an annealing process to repair the damage that may be caused by the process of forming the peeling layer 140, and further prevent the damage caused by the formation of the peeling layer 140 from affecting subsequent steps. In this step, for example, annealing is performed on the entire device in a nitrogen (N) environment. In one embodiment, the annealing time is, for example, 15 minutes.
[0058] See also Figure 2 , Figure 3d as well as Figure 3e In step S140 , the peeling layer 140 is removed, and the protrusions 123 wrapped by the peeling layer 140 are removed at the same time, so as to planarize the surface of the exposed interconnect structure 122 .
[0059] In this step, dry etching is used, for example, to remove the lift-off layer 140. In one embodiment, for example, a mixed gas containing fluorine and chlorine is used as the etching gas.
[0060] Furthermore, during the process of removing the stripping layer 140 by etching, the surface exposed by the window 131 is detected to prevent over-etching. In one embodiment, for example, the detection device 20 is used to detect the surface exposed by the window 131. Wherein, the stripping layer 140 contains boron (B) and / or phosphorus (P). When it is detected that the surface exposed by the window 131 contains boron (B) and / or phosphorus (P), it indicates that the surface of the interconnect structure 122 exposed by the window 131 is still covered with the stripping layer 140, and etching is continued to remove the remaining stripping layer 140, such as Figure 3d When no boron element (B) and / or phosphorus element (P) is detected on the surface of the interconnect structure 122 exposed by the window 131, it indicates that the stripping layer 140 on the surface of the interconnect structure 122 exposed by the window 131 has been completely removed, and the removal of the stripping layer 140 is stopped. Figure 3e As shown, since the stripping layer 140 (borosilicate stripping layer) completely wraps the protrusion 123, the protrusion 123 is also etched away at the same time as the stripping layer 140 is completely etched away, and since the detection process is added, over-etching is prevented, and the etching process is further prevented from affecting the size of the interconnect structure 122.
[0061] Through the above steps, the semiconductor device 100 obtains a flat and smooth surface of the interconnection structure 122 at the window 131, thereby improving the electrical performance of the device.
[0062] The manufacturing process of the semiconductor device 100 includes a front-end process and a back-end process, wherein the front-end process includes thin film deposition, ion implantation, and patterning, which are mainly used to form the source region 112, the drain region 113, and the gate stack of the semiconductor device 100; the back-end process includes thin film deposition and patterning, which are mainly used to form the interconnection structure of the semiconductor device 100, including the connection channel 1222 and the wiring 1221 of the semiconductor device 100. The semiconductor device 100 also includes a WAT (Wafer Acceptance Test) process, which is performed after the back-end process is completed and is used for electrical testing of the device to ensure that the chip can operate normally during subsequent manufacturing and use.
[0063] Figure 4 FIG. 1 shows a schematic diagram of performing an electrical test on a semiconductor device in a specific embodiment; Figure 4 As shown, the test process, for example, applies a low level voltage to the interconnection structure 122 connected to the source region 112, and applies a high level voltage to the interconnection structure 122 connected to the drain region 113 and the interconnection structure 122 connected to the gate, so as to test the electrical performance of the semiconductor device. During the test, the probe 30 needs to directly contact the surface of the interconnection structure 122.
[0064] Figure 5 A method for testing a semiconductor device according to an embodiment of the present invention is shown. Figures 6a to 6e 1 shows cross-sectional views of various stages in a semiconductor device testing process according to an embodiment of the present invention. For the sake of clarity, Figures 6a to 6e Only part of the device structure is shown. Figure 2 as well as Figures 6a to 6e A method for testing a semiconductor device according to an embodiment of the present invention is described.
[0065] See also Figure 5 as well as Figure 6a In step S210 , a window 131 exposing the interconnect structure 122 is formed, wherein the exposed surface of the interconnect structure 122 has a protrusion 123 .
[0066] In this step, for example, a window 131 is formed in the passivation layer 130 by using a photolithography and etching process, and the window 131 exposes the top of the interconnection structure 122, so that the probe can contact the top of the interconnection structure 122 through the window 131 during the subsequent test. In the process of forming the window 131, the deformation of the top of the interconnection structure 122 is greater than the deformation of the interlayer dielectric layer 121 due to the thermal instability of the machine, and then the protrusion 123 is formed on the surface of the interconnection structure 122 exposed by the window 131.
[0067] In the subsequent WAT process, the probe 30 contacts the top surface of the interconnect structure 122. Ideally, the exposed surface of the interconnect structure 122 is flat and smooth. When the probe 30 contacts the exposed surface of the interconnect structure 122, the exposed surface of the interconnect structure 122 is subjected to uniform force. Figure 7a When the probe 30 contacts the exposed surface of the interconnection structure 122 with the protrusion 123, the protrusion 123 will cause the top surface of the interconnection structure 122 to be subjected to uneven force, and the needle insertion effect of the probe 30 will be deteriorated. Figure 7b shown.
[0068] The uneven force on the surface of the interconnect structure 122 caused by the protrusions 123 will cause the electrical test results to drift, which will lead to wafer degradation, and in severe cases, even direct wafer scrapping. When reaching the WAT process, the wafer has completed all the processes of the front-end process and the back-end process. If the measurement results drift due to the protrusions 123 on the surface of the interconnect structure 122, it will cause a loss of wafer yield.
[0069] See also Figure 5 as well as Figure 6b In step S220 , a peeling layer 140 is formed. The peeling layer 140 at least covers the surface of the interconnection structure 122 exposed by the window 131 and wraps the protrusions 123 on the surface of the interconnection structure 122 .
[0070] In this step, for example, a deposition process is used to form a peeling layer 140 on the surface of the passivation layer 130, the sidewalls of the window 131, and the surface of the interconnection structure 122 exposed through the window 131. In this embodiment, the peeling layer 140 conformally covers the surface of the passivation layer 130, the sidewalls of the window 131, and the surface of the interconnection structure 122 exposed through the window 131, and wraps the protrusion 123 on the surface of the interconnection structure 122.
[0071] The stripping layer 140 is a doped layer, preferably a phosphorus and / or boron doped layer. In one embodiment, the stripping layer 140 is, for example, a borophospho-silicate glass (BPSG) layer. The thickness of the stripping layer 140 is greater than the height of the protrusion 123, so that the stripping layer 140 completely covers the protrusion 123. Further, the thickness of the stripping layer 140 is less than 15,000 angstroms to prevent the stripping layer 140 from being too thick, which increases the difficulty of etching during the removal of the stripping layer 140. In one embodiment, the thickness of the stripping layer 140 is, for example, 5,000 angstroms. Borophospho-silicate glass has a certain fluidity at high temperature, and the stripping layer 140 formed can completely wrap the protrusion 123 on the surface of the interconnect structure 122.
[0072] See also Figure 5 In step S230, after the peeling layer 140 is formed, the device is annealed.
[0073] In this step, the entire device is annealed in a nitrogen (N) environment, for example. In one embodiment, the annealing time is, for example, 15 minutes.
[0074] In order to prevent the process of forming the peeling layer 140 from causing damage to the device, the present application adds an annealing process to repair the damage that may be caused by the process of forming the peeling layer 140, and further prevent the damage caused by the formation of the peeling layer 140 from affecting subsequent steps.
[0075] See also Figure 5 , Figure 6c as well as Figure 6d In step S240 , the peeling layer 140 is removed, and at the same time, the protrusion 123 wrapped by the peeling layer 140 is removed.
[0076] In this step, dry etching is used, for example, to remove the lift-off layer 140. In one embodiment, for example, a mixed gas containing fluorine and chlorine is used as the etching gas.
[0077] Furthermore, during the process of removing the stripping layer 140 by etching, the surface exposed by the window 131 is detected to prevent over-etching. In one embodiment, for example, the detection device 20 is used to detect the surface exposed by the window 131. Wherein, the stripping layer 140 contains boron (B) and / or phosphorus (P). When the surface exposed by the window 131 is detected to contain boron (B) and / or phosphorus (P), it indicates that the surface exposed by the window 131 is still covered with the stripping layer 140. Etching is continued, such as Figure 3c When no boron element (B) and / or phosphorus element (P) is detected on the surface exposed by the window 131, the etching is stopped. Figure 3d As shown, since the stripping layer 140 (borosilicate stripping layer) completely wraps the protrusion 123, the protrusion 123 is also etched away at the same time as the stripping layer 140 is completely etched away, and since the detection process is added, over-etching is prevented, and the etching process is further prevented from affecting the size of the interconnect structure 122.
[0078] See also Figure 5 as well as Figure 6e In step S250 , the probe contacts the interconnection structure 122 through the window 131 to perform a test. At this time, the exposed surface of the interconnection structure 122 is smooth, and the measurement process will not be affected by the protrusion 123 .
[0079] The unexpected technical effects of this application are:
[0080] According to the semiconductor device manufacturing method, semiconductor device and testing method of the embodiment of the present invention, a peeling layer is formed on the surface of the interconnection structure, so that the peeling layer wraps the protrusions on the surface of the interconnection structure, and then the protrusions on the surface of the interconnection structure are removed while removing the peeling layer, so as to flatten the surface of the interconnection structure. In the test process of the semiconductor device, the drift of the test results caused by the protrusions on the surface of the interconnection structure is avoided, and the loss of wafer yield is reduced. At the same time, the flattening of the surface of the interconnection structure improves the electrical performance of the device.
[0081] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, the stripping layer is a borosilicate glass layer. The borosilicate glass at high temperature has fluidity, so that the stripping layer can completely wrap the protrusions on the surface of the interconnection structure, so that the protrusions are removed together with the stripping layer.
[0082] According to the semiconductor device manufacturing method, semiconductor device and testing method of the embodiments of the present invention, the thickness of the peeling layer is greater than the height of the protrusions on the surface of the interconnect structure, so that the peeling layer can completely cover the height of the protrusions on the surface of the interconnect structure.
[0083] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, element detection is performed on the surface of the interconnect structure while removing the stripping layer to prevent over-etching and further prevent the loss of interconnect structure size.
[0084] According to the semiconductor device preparation method, semiconductor device and testing method of the embodiments of the present invention, after the stripping layer is formed, an annealing step is also included to repair the damage that may be caused by the stripping layer formation process, and further prevent the damage caused by the stripping layer formation from affecting subsequent steps.
[0085] The embodiments of the present application are described above, and these embodiments do not describe all the details in detail, nor do they limit the application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A method for preparing a semiconductor device, comprising: forming an interconnect structure and a passivation layer covering the interconnect structure on the semiconductor layer; forming a window exposing the interconnection structure, wherein the exposed surface of the interconnection structure has a protrusion; forming a peeling layer, wherein the thickness of the peeling layer is greater than the height of the protrusions on the surface of the interconnection structure, the peeling layer at least covers the surface of the interconnection structure exposed by the window and wraps the protrusions on the surface of the interconnection structure, and the peeling layer is a borophosphosilicate glass layer; as well as The peeling layer is removed by dry etching, and the protrusions wrapped by the peeling layer are removed at the same time.
2. The preparation method according to claim 1, wherein The thickness of the release layer is less than 15,000 angstroms.
3. The preparation method according to claim 1, wherein During the process of removing the peeling layer, the surface exposed by the window is simultaneously subjected to element detection, wherein: When it is detected that the surface exposed by the window has the boron element and / or the phosphorus element, continue to remove the peeling layer; When it is detected that there is no boron element and / or phosphorus element on the surface exposed by the window, the removal of the peeling layer is stopped.
4. The preparation method according to claim 1, wherein A mixed gas containing fluorine and chlorine is used as the etching gas.
5. The preparation method according to claim 1, wherein After forming the peeling layer, an annealing step is further included. 6 . A semiconductor device, wherein the semiconductor device is formed according to the preparation method according to claim 1 .
7. A method for testing a semiconductor device, comprising: A semiconductor device is formed according to the preparation method according to any one of claims 1 to 5, wherein the interconnect structure exposed by the window has a flat surface; as well as A probe contacts the interconnection structure through the window to perform a test.