IQ signal mismatch correction method and device, storage medium and electronic equipment

Abstract

The embodiment of the application discloses an IQ signal mismatch correction method and device, a storage medium and an electronic device, and relates to the field of signal processing. The embodiment of the application directly corrects the phase of the analog IQ signal through iteration and correction, and the algorithm complexity is low, so that the phase calibration can be completed in a short time, and the response speed of the system is improved. It does not depend on a specific hardware platform or chip manufacturing process, and therefore has strong applicability. Whether it is different types of chips or different application scenarios, as long as there is a phase deviation problem of I / Q two-way signals, the technical solution can be used for calibration.

Description

Technical Field

[0001] This application relates to the field of signal processing, and in particular to a method, apparatus, storage medium, and electronic device for mismatch correction of IQ signals. Background Technology

[0002] Due to issues such as mismatches in chip manufacturing processes, even if the design meets the requirement of a 90° phase difference between the I and Q signals, the actual chip may still exhibit a phase deviation greater than or less than 90°. Therefore, phase correction of the I and Q signals is necessary. See also Figure 1 As shown, the existing method for correcting IQ signals involves digital correction using sampled data from a subsequent ADC. This is achieved by calculating the phase and amplitude mismatch of the IQ signals using the ADC data, and then compensating for IQ through numerical compensation. However, this method suffers from several drawbacks: long correction time and high algorithm complexity in the digital calibration device, resulting in a large device size. Summary of the Invention

[0003] This application provides a method, apparatus, storage medium, and electronic device for mismatch correction of IQ signals, which can solve the problems of high complexity, low efficiency, and large hardware size in existing digital calibration technologies. The technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a mismatch correction method for IQ signals, the method comprising:

[0005] Perform n iterations: The delay chain circuit is instructed to delay the specified channel according to the current control word; after the delay, the phase difference between the I-channel signal and the Q-channel signal is measured, and the phase difference is converted into a phase difference voltage. The phase difference voltage is compared with the reference voltage. If the phase difference voltage is less than the reference voltage, the intermediate control word between the current control word and the maximum control word is calculated, and the calculated intermediate control word is used as the next control word; if the phase difference voltage is greater than the reference voltage, the intermediate control word between the current control word and the minimum control word is calculated, and the calculated intermediate control word is used as the next control word; the delay chain circuit is instructed to delay the specified channel according to the next control word; n represents the length of the control word.

[0006] After the n th iteration, the latest control word is obtained, and the delay chain circuit is instructed to delay the specified channel according to the latest control word; after the delay processing, the phase difference between the I channel signal and the Q channel signal is measured, and the phase difference is converted into a phase difference voltage; the size of the phase difference voltage and the reference voltage is compared, the number of first comparison results and the number of second comparison results are counted within a preset time window, if the number of first comparison results is greater than the number of second comparison results, the latest control word plus 1 is taken as the target control word; if the number of second comparison results is greater than the number of first comparison results, the latest control word minus 1 is taken as the target control word; the first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage.

[0007] In a second aspect, the embodiments of the present application provide an IQ signal mismatch correction device, the device comprising:

[0008] The iteration unit is configured to perform n iterations: instructing the delay chain circuit to delay the specified channel according to the current control word; after the delay processing, measuring the phase difference between the I channel signal and the Q channel signal, converting the phase difference into a phase difference voltage, and comparing the size of the phase difference voltage and the reference voltage; if the phase difference voltage is less than the reference voltage, calculating the intermediate control word between the current control word and the maximum control word, and taking the calculated intermediate control word as the next control word; if the phase difference voltage is greater than the reference voltage, calculating the intermediate control word between the current control word and the minimum control word, and taking the calculated intermediate control word as the next control word; instructing the delay chain circuit to delay the specified channel according to the next control word.

[0009] The correction unit is configured to, after the n th iteration, obtain the latest control word, and instruct the delay chain circuit to delay the specified channel according to the latest control word; after the delay processing, measure the phase difference between the I channel signal and the Q channel signal, and convert the phase difference into a phase difference voltage; compare the size of the phase difference voltage and the reference voltage, count the number of first comparison results and the number of second comparison results within a preset time window, if the number of first comparison results is greater than the number of second comparison results, take the latest control word plus 1 as the target control word; if the number of second comparison results is greater than the number of first comparison results, take the latest control word minus 1 as the target control word; the first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage.

[0010] In a third aspect, the embodiments of the present application provide a computer storage medium, the computer storage medium stores a plurality of instructions, the instructions are suitable for being loaded and executed by a processor to perform the method steps described above.

[0011] In a fourth aspect, an electronic device is provided, which can include a processor and a memory; wherein the memory stores a computer program, and the computer program is adapted to be loaded by the processor and execute the method steps described above.

[0012] The technical solutions provided by some embodiments of the present application have at least the following beneficial effects:

[0013] The control word is adjusted in real time through iteration, and the delay of the delay chain circuit is dynamically changed according to the phase difference of the current I / Q two-way signal, so as to realize accurate control of the phase difference. The real-time and dynamic adjustment capability enables the technical solution to respond to system changes more quickly and ensure that the system always works in the best state. The adjustment of the phase difference mainly depends on the delay chain circuit and the control logic, and does not depend on the sampling data of the ADC. Therefore, compared with the IQ calibration through numerical compensation, the technical solution has lower dependence on hardware and reduces the error introduced due to insufficient performance or precision of the ADC. Through iteration and adjustment of the control word, the technical solution can gradually approach the ideal phase difference and realize high-precision phase calibration. After iteration ends, the accuracy of the final control word can be further confirmed by counting the number of comparison results in a preset time window. This statistical method can reduce the influence of single measurement error and improve the stability of the system. At the same time, due to the low algorithm complexity, the phase calibration can be completed in a short time, and the response speed of the system is improved. The technical solution does not depend on a specific hardware platform or chip manufacturing process, and therefore has strong applicability. Whether it is different types of chips or different application scenarios, as long as there is a phase deviation problem of I / Q two-way signals, the technical solution can be used for calibration. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.

[0015] Figure 1 is a schematic diagram of digital correction of IQ signals by ADC in the prior art;

[0016] Figure 2 is a flowchart of an IQ signal mismatch correction method provided by an embodiment of the present application;

[0017] Figure 3 is a structural diagram of an IQ signal mismatch correction device provided by the present application;

[0018] Figure 4 is a structural schematic diagram of an electronic device provided by the present application. DETAILED DESCRIPTION

[0019] For the purpose, technical solutions and advantages of the present application to be clearer, the following will be further described in detail with reference to the drawings.

[0020] It should be noted that the IQ signal mismatch correction method provided by the present application is generally executed by an IQ signal mismatch correction device, and accordingly, the IQ signal mismatch correction device is generally arranged in an electronic device.

[0021] Please refer to Figure 1 , a flowchart of an IQ signal mismatch correction method provided by the present application is shown. As shown in Figure 2 , the method of the present application can include the following steps:

[0022] S201, performing n iterations: instructing the delay chain circuit to perform delay processing on the specified channel according to the current control word; measuring the phase difference between the I path signal and the Q path signal after the delay processing, converting the phase difference into a phase difference voltage, and comparing the size between the phase difference voltage and the reference voltage; if the phase difference voltage is less than the reference voltage, calculating the intermediate control word between the current control word and the maximum control word, and taking the calculated intermediate control word as the next control word; if the phase difference voltage is greater than the reference voltage, calculating the intermediate control word between the current control word and the minimum control word, and taking the calculated intermediate control word as the next control word; instructing the delay chain circuit to perform delay processing on the specified channel according to the next control word.

[0023] Among them, the I channel is used to transmit the I path signal, the Q channel is used to transmit the Q path signal, the delay chain circuit is arranged in the specified channel, the specified channel is the I channel or the Q channel, and the following will be described by taking the delay chain circuit arranged in the Q channel as an example.

[0024] 1, initialization: setting the iteration number n, n represents the length of the control word of the delay chain circuit. Set the reference voltage V_ref, the maximum control word CW_max, the minimum control word CW_min, and the initial control word CW_current, for example: the length of the control word arranged by the delay chain circuit is 6, so the minimum control word CW_min=0, the maximum control word CW_max=63, that is, the delay chain circuit is arranged with 64 positions of delay amount.

[0025] 2, start iteration: for each iteration i (where i is from 1 to n).

[0026] 3, delay processing: instructing the delay chain circuit to perform delay processing on the Q channel according to the current control word CW_current.

[0027] 4. Phase difference measurement: After the Q-channel delay processing, measure the phase difference between the I and Q signals, and convert the measured phase difference into a phase difference voltage V_phase_diff.

[0028] 5. Compare phase difference voltage to reference voltage: Compare the phase difference voltage V_phase_diff to a reference voltage V_ref.

[0029] 6. Adjust control word: If V_phase_diff is less than V_ref, perform the following operations:

[0030] Calculate an intermediate control word CW_mid between the current control word CW_current and the maximum control word CW_max. Set CW_mid as the next control word CW_next.

[0031] If V_phase_diff is greater than V_ref, perform the following operations:

[0032] Calculate an intermediate control word CW_mid between the current control word CW_current and the minimum control word CW_min.

[0033] Set CW_mid as the next control word CW_next.

[0034] 7. Update current control word: Set the next control word CW_next as the current control word CW_current for use in the next iteration.

[0035] 8. Iteration completion check: Check if the number of iterations n has been reached. If not, return to step 3 for the next iteration. If so, end the iteration process.

[0036] 9. End correction: The final control word CW_current used is the one obtained after n iterations of correction, which is used for subsequent delay processing of the Q channel.

[0037] For example, assuming n = 6, the minimum control word is 0, and the maximum control word is 63, the following is a specific example of the execution steps to illustrate the above mismatch correction process:

[0038] Initialization: Set the number of iterations n = 6. Set the reference voltage V_ref (the specific value is determined by the system). Set the maximum control word CW_max = 63. Set the minimum control word CW_min = 0. Set the initial control word CW_current (for example, starting from the middle value, CW_current = 32).

[0039] Start iteration: for each iteration i (from 1 to 6): 1st iteration (i = 1): use the current control word CW_current = 32 to instruct the delay chain circuit to delay the Q channel. Measure the phase difference between the I and Q signals and convert to a phase difference voltage V_phase_diff. Compare V_phase_diff and V_ref. Assume V_phase_diff is less than V_ref, calculate an intermediate control word CW_mid = (32 + 63) / 2 = 47.5 (since the control word must be an integer, here it can be rounded to 48). Set CW_mid = 48 as the next control word CW_next.

[0040] Update current control word: set CW_next = 48 as CW_current for the next iteration.

[0041] Continue iteration: repeat steps 3 and 4, adjusting the control word according to the comparison of V_phase_diff and V_ref for each iteration until all 6 iterations are completed.

[0042] Iteration process example:

[0043] 2nd iteration can result in CW_current = 55 (if V_phase_diff is still less than V_ref).

[0044] 3rd iteration can result in CW_current = 59 (continuing to reduce the phase difference).

[0045] 4th iteration can find that V_phase_diff is greater than V_ref, so CW_current will adjust towards CW_min, for example, resulting in CW_current = 52.

[0046] Subsequent iterations will continue to adjust until a control word that is close to a match is found.

[0047] End of correction: after 6 iterations, the mismatch correction device obtains a control word CW_current that is closer to the optimal match. This control word will be used for subsequent Q channel delay processing.

[0048] In some embodiments of the present application, calculating an intermediate control word between the current control word and the maximum control word includes:

[0049] Taking the average of the current control word and the maximum control word, and rounding, rounding up or rounding down the average to obtain the intermediate control word;

[0050] Calculating an intermediate control word between the current control word and the minimum control word includes:

[0051] The intermediate control word is obtained by averaging the current control word and the minimum control word, and then rounding the average value up or down. The resulting intermediate control word is an integer.

[0052] In one or more possible embodiments, the number of stops in the delay chain circuit is related to the clock frequency and the calibration accuracy, and can be calculated using the following formula:

[0053] delay_t = α / 4f, delay_num = (1 / 4f - T) / delay_t, where f is the clock frequency of the I / Q channels, α is the required calibration accuracy (which can be 1 / 1000 or 1 / 10000), T is the basic delay difference of the I / Q channels (which should be less than 1 / 4f), delay_t is the delay amount for each position, and delay_num is the number of positions in the delay chain.

[0054] S202. After the nth iteration, obtain the latest control word and instruct the delay chain circuit to perform delay processing on the specified channel according to the latest control word. After the delay processing, measure the phase difference between the I-channel signal and the Q-channel signal, and convert the phase difference into a phase difference voltage. Compare the phase difference voltage with the reference voltage, and count the number of the first comparison result and the second comparison result within a preset time window. If the number of the first comparison result is greater than the number of the second comparison result, increment the latest control word by 1 to obtain the target control word. If the number of the second comparison result is greater than the number of the first comparison result, decrement the latest control word by 1 to obtain the target control word.

[0055] The first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage. After n iterations of S201, the latest control word CW_latest is obtained. Using CW_latest as the control word, the delay chain circuit is instructed to perform delay processing on the specified channel again. After delay processing, the phase difference between the I-channel signal and the Q-channel signal is measured and converted into a phase difference voltage V_final_phase_diff.

[0056] In a preset time window T_window, the magnitude between the phase difference voltage and the reference voltage is repeatedly compared multiple times. In each comparison, if V_final_phase_diff is less than V_ref, it is recorded as a first comparison result; if V_final_phase_diff is greater than V_ref, it is recorded as a second comparison result. The number of the first comparison results and the second comparison results are counted, and are recorded as Count_Less and Count_Greater respectively. Count_Less and Count_Greater are compared: if Count_Less is greater than Count_Greater, it means that in most cases, the phase difference voltage is too small, so CW_latest is added 1 as the target control word CW_target. If Count_Greater is greater than Count_Less, it means that in most cases, the phase difference voltage is too large, so CW_latest is subtracted 1 as the target control word CW_target. The determined target control word CW_target is output, or it is applied to the delay chain circuit to achieve accurate delay adjustment on the specified channel.

[0057] After the above steps, the mismatch correction device finds a target control word CW_target, which can keep the phase difference voltage near the reference voltage for a long time, so as to achieve accurate correction of the phase difference between the I and Q signals.

[0058] In some embodiments of the present application, the magnitude between the phase difference voltage and the reference voltage is compared by a comparator. If the phase difference voltage is less than the reference voltage, the comparator outputs low level 0; if the phase difference voltage is greater than the reference voltage, the comparator outputs high level 1, i.e. the first comparison result is the comparator output low level, and the second comparison result is the comparator output high level.

[0059] Implementing the embodiments of the present application can bring the following beneficial effects:

[0060] The control word is adjusted in real time through iteration, and the delay of the delay chain circuit is dynamically changed according to the phase difference of the current I / Q two-way signal, so as to realize accurate control of the phase difference. The real-time and dynamic adjustment capability enables the technical solution to respond to system changes more quickly and ensure that the system always works in the best state. The adjustment of the phase difference mainly depends on the delay chain circuit and the control logic, and does not need to depend on the sampling data of the ADC. Therefore, compared with the IQ calibration realized by numerical compensation, the technical solution has lower dependence on hardware and reduces the error introduced due to insufficient performance or precision of the ADC. Through iteration and adjustment of the control word, the technical solution can gradually approach the ideal phase difference and realize high-precision phase calibration. After iteration, the accuracy of the final control word can be further confirmed by counting the number of comparison results in a preset time window. The statistical method can reduce the influence of single measurement error and improve the stability of the system. At the same time, due to the low algorithm complexity, the phase calibration can be completed in a short time, and the response speed of the system is improved. The technical solution does not depend on a specific hardware platform or chip manufacturing process, and therefore has strong applicability. Whether it is different types of chips or different application scenarios, as long as there is a phase deviation problem of I / Q two-way signals, the technical solution can be used for calibration.

[0061] The following is an apparatus embodiment of the present application, which can be used to execute the method embodiments of the present application. For details not disclosed in the apparatus embodiments of the present application, please refer to the method embodiments of the present application.

[0062] Please refer to Figure 3 which shows a structure diagram of an IQ signal mismatch correction apparatus provided by an example embodiment of the present application, hereinafter referred to as apparatus 3. The apparatus 3 can be realized by software, hardware or a combination of both to become all or part of an electronic device. The apparatus 3 comprises an iteration unit 301 and a correction unit 302.

[0063] The iteration unit 301 is configured to perform n iterations: instructing the delay chain circuit to perform delay processing on the specified channel according to the current control word; measuring the phase difference between the I and Q signals after the delay processing, converting the phase difference into a phase difference voltage, and comparing the size between the phase difference voltage and the reference voltage; if the phase difference voltage is less than the reference voltage, calculating an intermediate control word between the current control word and the maximum control word, and taking the calculated intermediate control word as the next control word; if the phase difference voltage is greater than the reference voltage, calculating an intermediate control word between the current control word and the minimum control word, and taking the calculated intermediate control word as the next control word; and instructing the delay chain circuit to perform delay processing on the specified channel according to the next control word;

[0064] The correction unit 302 is configured to obtain the latest control word after the nth iteration, and to instruct the delay chain circuit to delay the specified channel according to the latest control word. After the delay processing, the phase difference between the I channel signal and the Q channel signal is measured, and the phase difference is converted into a phase difference voltage. The phase difference voltage and the reference voltage are compared, and the number of first comparison results and the number of second comparison results are counted within a preset time window. If the number of first comparison results is greater than the number of second comparison results, the latest control word is incremented by 1 to obtain the target control word. If the number of second comparison results is greater than the number of first comparison results, the latest control word is decremented by 1 to obtain the target control word. The first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage.

[0065] In one or more possible embodiments, the intermediate control word between the current control word and the maximum control word is calculated by:

[0066] taking the average of the current control word and the maximum control word, and rounding, rounding up or rounding down the average to obtain the intermediate control word.

[0067] In one or more possible embodiments, the intermediate control word between the current control word and the minimum control word is calculated by:

[0068] taking the average of the current control word and the minimum control word, and rounding, rounding up or rounding down the average to obtain the intermediate control word.

[0069] In one or more possible embodiments, the initialized control word configured in the delay chain circuit is determined according to the intermediate control word calculated from 0 and the maximum control word.

[0070] In one or more possible embodiments, the comparator is used to compare the size of the phase difference voltage and the reference voltage. When the output of the comparator is low, it indicates that the phase difference voltage is less than the reference voltage. When the output of the comparator is high, it indicates that the phase difference voltage is greater than the reference voltage.

[0071] In one or more possible embodiments, the number of gears of the delay chain circuit is related to the clock frequency and the correction accuracy. The number of gears of the delay chain circuit is calculated according to the following formula:

[0072] delay_t = a / 4f, delay_num = (1 / 4f-T) / delay_t, f is the clock frequency of the I / Q channel, a is the required calibration accuracy, which can be 1 / 1000, 1 / 10000, T is the basic delay difference of the I / Q channel, which should be less than 1 / 4f; delay_t is the delay amount of each gear, and delay_num is the number of gears of the delay chain.

[0073] It should be noted that the device 3 provided by the above embodiment is only used as an example to illustrate the division of the above functional modules when performing the IQ signal mismatch correction method. In actual application, the above functional distribution can be completed by different functional modules according to the needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the above functions. In addition, the IQ signal mismatch correction device and the IQ signal mismatch correction method provided by the above embodiment belong to the same concept, and the implementation process is detailed in the method embodiment. Here, it is not repeated.

[0074] The serial numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0075] The embodiments of the present application also provide a computer storage medium, which can store a plurality of instructions, the instructions being suitable for being loaded and executed by a processor to implement the method steps of the embodiments of the method as shown in the above Figure 2 The specific implementation process can refer to the specific description of the embodiments of the method as shown in the above Figure 2 Here, it is not repeated.

[0076] The present application also provides a computer program product, which stores at least one instruction, the at least one instruction is loaded and executed by the processor to implement the IQ signal mismatch correction method as described in each of the above embodiments.

[0077] Please refer to Figure 4 , the present application provides a structural schematic diagram of an electronic device. As shown in Figure 4 , the electronic device 400 can include at least one processor 401, at least one network interface 404, a user interface 403, a memory 405, and at least one communication bus 402.

[0078] The communication bus 402 is used to realize the connection and communication between the components.

[0079] The user interface 403 can include a display screen (Display), a camera (Camera), and an optional user interface 403, which can also include a standard wired interface and a wireless interface.

[0080] The network interface 404 can optionally include a standard wired interface and a wireless interface (such as a WI-FI interface).

[0081] The processor 401 can include one or more processing cores. The processor 401 connects various parts within the entire electronic device 400 by various interfaces and lines, performs various functions of the electronic device 400 and processes data by running or executing instructions, programs, code sets or instruction sets stored in the memory 405, and calling data stored in the memory 405. Optionally, the processor 401 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The processor 401 can integrate a combination of one or several of a central processing unit (CPU), a graphics processing unit (GPU), and a modem. Among them, the CPU mainly processes an operating system, a user interface, and an application program; the GPU is responsible for rendering and drawing the content to be displayed on the display screen; and the modem is used for processing wireless communication. It can be understood that the above-mentioned modem can also not be integrated into the processor 401, but can be realized by a separate chip.

[0082] The memory 405 can include a random access memory (RAM) and can also include a read-only memory (ROM). Optionally, the memory 405 includes a non-transitory computer-readable storage medium. The memory 405 can be used to store instructions, programs, codes, code sets or instruction sets. The memory 405 can include a program storage area and a data storage area, wherein the program storage area can store instructions for implementing an operating system, instructions for at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the above-mentioned various method embodiments, etc.; the data storage area can store data involved in the above-mentioned various method embodiments, etc. The memory 405 can also be at least one storage device located away from the aforementioned processor 401. As shown, the memory 405 as a computer storage medium can include an operating system, a network communication module, a user interface module, and an application program. Figure 4 As shown, the memory 405 as a computer storage medium can include an operating system, a network communication module, a user interface module, and an application program.

[0083] In Figure 4In the electronic device 400 shown, the user interface 403 is mainly used to provide an interface for the user to input, and obtain data input by the user; and the processor 401 can be used to call an application stored in the memory 405, and specifically execute the method as shown in Figure 2 The method shown, the specific process can refer to Figure 2 The specific process can refer to

[0084] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by a computer program instructing related hardware. The program can be stored in a computer readable storage medium, and when the program is executed, the program can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory, a random access memory, etc.

[0085] The above only describes the preferred embodiments of the present application, and of course cannot limit the scope of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope of the present application.

Claims

1. A method of mismatch correction of an IQ signal, characterized by, The method comprises the following steps: performing n iterations: instructing the delay chain circuit to delay the specified channel according to the current control word; measuring the phase difference between the I and Q signals after the delay processing, converting the phase difference into a phase difference voltage, and comparing the size between the phase difference voltage and a reference voltage; if the phase difference voltage is less than the reference voltage, calculating an intermediate control word between the current control word and the maximum control word, and taking the calculated intermediate control word as the next control word; if the phase difference voltage is greater than the reference voltage, calculating an intermediate control word between the current control word and the minimum control word, and taking the calculated intermediate control word as the next control word; instructing the delay chain circuit to delay the specified channel according to the next control word; n represents the length of the control word; after performing the n iterations, obtaining the latest control word and instructing the delay chain circuit to delay the specified channel according to the latest control word, measuring the phase difference between the I and Q signals after the delay processing, converting the phase difference into a phase difference voltage, comparing the size between the phase difference voltage and a reference voltage, counting the number of first comparison results and second comparison results within a preset time window, and if the number of first comparison results is greater than the number of second comparison results, taking the latest control word plus 1 as the target control word; if the number of second comparison results is greater than the number of first comparison results, taking the latest control word minus 1 as the target control word; the first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage.

2. The method of claim 1, wherein, The calculation of the intermediate control word between the current control word and the maximum control word comprises: taking the average of the current control word and the maximum control word, and rounding, rounding up or rounding down the average to obtain the intermediate control word. The calculation of the intermediate control word between the current control word and the minimum control word comprises: taking the average of the current control word and the minimum control word, and rounding, rounding up or rounding down the average to obtain the intermediate control word.

3. The method according to claim 1 or 2, characterized in that, The initialized control word configured in the delay chain circuit is determined according to the intermediate control word calculated from 0 and the maximum control word.

4. The method of claim 3, wherein, The comparator compares the size between the phase difference voltage and the reference voltage, and when the output of the comparator is low, it indicates that the phase difference voltage is less than the reference voltage; when the output of the comparator is high, it indicates that the phase difference voltage is greater than the reference voltage.

5. The method according to claim 1 or 2 or 4, characterized in that, The number of gears of the delay chain circuit is related to the clock frequency and the correction accuracy, and the number of gears of the delay chain circuit is calculated according to the following formula: delay_t = a / 4f, delay_num = (1 / 4f-T) / delay_t, f is the clock frequency of the I / Q channel, a is the required calibration accuracy, which can be 1 / 1000, 1 / 10000, T is the basic delay difference of the I / Q channel, which should be less than 1 / 4f; delay_t is the delay amount of each gear, and delay_num is the number of gears of the delay chain.

6. A mismatch correction apparatus of an IQ signal, characterized by comprising: The method comprises the following steps: an iteration unit, configured to perform n times of iterations: instructing the delay chain circuit to delay the specified channel according to a current control word; measuring a phase difference between the I signal and the Q signal after the delay processing, converting the phase difference into a phase difference voltage, and comparing a size between the phase difference voltage and a reference voltage; if the phase difference voltage is less than the reference voltage, calculating an intermediate control word between the current control word and a maximum control word, and taking the calculated intermediate control word as a next control word; if the phase difference voltage is greater than the reference voltage, calculating an intermediate control word between the current control word and a minimum control word, and taking the calculated intermediate control word as the next control word; instructing the delay chain circuit to delay the specified channel according to the next control word; an amendment unit, configured to perform the n times of iterations, acquire a latest control word, and instruct the delay chain circuit to delay the specified channel according to the latest control word; measure a phase difference between the I signal and the Q signal after the delay processing, convert the phase difference into a phase difference voltage, and compare a size between the phase difference voltage and the reference voltage; count a number of first comparison results and a number of second comparison results within a preset time window, take the latest control word plus 1 as a target control word if the number of the first comparison results is greater than the number of the second comparison results; take the latest control word minus 1 as the target control word if the number of the second comparison results is greater than the number of the first comparison results; the first comparison result indicates that the phase difference voltage is less than the reference voltage, and the second comparison result indicates that the phase difference voltage is greater than the reference voltage.

7. A computer storage medium, characterized in that The computer storage medium stores a plurality of instructions, which are suitable for being loaded and executed by a processor, and implement the method steps in any one of claims 1-5.

8. An electronic device, comprising: comprise: a processor and a memory; wherein the memory stores a computer program, and the computer program is suitable for being loaded and executed by the processor, and implement the method steps in any one of claims 1-5.

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