A calibration method and circuit applied to a pipelined successive approximation ADC

Abstract

The application discloses a kind of applied to the calibration method and circuit of pipeline successive approximation type ADC, by input signal and residual signal injection Dither signal, and using Dither_2 signal corresponding to the estimated value Dd2 of digital domain and the gain estimation value of residual signal VR' after injection is calibrated, gain value after calibration is obtained;Using gain value after calibration, digital code D1 and digital code D2 are spliced, to realize the calibration of interstage gain error, output the output signal to be mismatched calibration;The corresponding Dither signal is subtracted in digital domain to the output signal to be mismatched calibration, to find demarcation point, the maximum value of the interval before each demarcation point and the minimum value of the interval after each demarcation point are used to represent the weight mismatch information of the corresponding capacitor of demarcation point;To obtain corresponding error amount by using LMS algorithm to constantly iterate, realize the mismatch calibration of the output signal to be mismatched calibration, to improve the quantization accuracy and linearity of ADC.

Description

Technical Field

[0001] The present invention belongs to the technical field of mixed signal integrated circuits, and in particular relates to a calibration method and circuit applied to a pipeline successive approximation ADC. Background Art

[0002] Traditional pipelined analog-to-digital converters (Pipelined ADCs) operate through a multi-stage cascade and pipelined approach, offering high precision and high sampling rates. However, the presence of multiple inter-stage residual amplifiers consumes significant power. Traditional successive approximation register ADCs (SAR ADCs) offer a simple structure, a high degree of digitization, and low power consumption. The pipelined SAR ADC combines these two advantages, offering high sampling rates, high precision, and low power consumption. This approach offers a compromise between power consumption and speed, and has become a research hotspot in recent years.

[0003] During the design of PSAR ADCs, capacitor mismatches can lead to uncertainty in the weights between binary capacitors, significantly degrading ADC performance. Furthermore, in deep submicron processes, the gain of the residual amplifier is severely limited, making it impossible to accurately amplify the signal in a closed-loop configuration. To improve the ADC's quantization accuracy and linearity, these mismatches must be calibrated. Summary of the Invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a calibration method and circuit for a pipelined successive approximation ADC. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] In a first aspect, the present invention provides a calibration method for a pipelined successive approximation register ADC, the method comprising:

[0006] For input signal V in Sampling and injecting Dither_1 signal to obtain the injected input signal V i ' n , using the first stage SAR ADC to input the injected signal V i ' n Quantization is performed to obtain an M-bit digital code D1 and a residual signal VR; wherein the Dither_1 signal is a signal with randomly changing polarity and constant magnitude; after the Dither_1 signal is injected, the transfer curve of the first-stage SAR ADC changes;

[0007] The Dither_2 signal is injected into the residual signal VR to obtain an injected residual signal VR', and the injected residual signal VR' is amplified and quantized by the second SAR ADC to obtain an N-bit digital code D2;

[0008] According to the estimated value Dd2 of the Dither_2 signal corresponding to the digital domain and the injected residual signal VR', a preset gain estimation value G e is calibrated to obtain a calibrated gain value G e ;

[0009] According to the calibrated gain value G e , the digital code D1 and the digital code D2 are spliced to obtain an output signal Dout' to be mismatch calibrated;

[0010] The estimated value Dd1 of the Dither_1 signal corresponding to the digital domain is obtained by using the LMS algorithm, the estimated value Dd1 is subtracted from the output signal Dout' to be mismatch calibrated in the digital domain to obtain a changed transfer curve, M positions jumping from 0 to 1 in the changed transfer curve are found as demarcation points, the weight mismatch information of the capacitor corresponding to each demarcation point is obtained according to the maximum value output in the previous LSB interval and the minimum value output in the next LSB interval of each demarcation point, the iteration error of the capacitor corresponding to each demarcation point is obtained according to all the weight mismatch information, all the iteration errors are processed by using the LMS algorithm to obtain M error amounts, the digital code of each demarcation point in the output signal Dout' to be mismatch calibrated is subtracted by the error amount corresponding to the digital code to obtain an output signal Dout after mismatch calibration.

[0011] In an embodiment of the present application, the clock signal for controlling the injection of the Dither_1 signal is synchronized with the enable clock signal for controlling the first quantization of the comparator in the first SAR ADC.

[0012] In an embodiment of the present application, the process of calibrating the preset gain estimation value G e according to the estimated value Dd2 of the Dither_2 signal corresponding to the digital domain and the injected residual signal VR' to obtain a calibrated gain value G e , includes:

[0013] The product of the estimated value Dd2 and the preset gain estimation value G e is subtracted from the residual signal VR' to obtain a first signal VR'';

[0014] multiplying the first signal VR" with the estimated value Dd2 to obtain a first result, multiplying the first result with a first iteration step size μ1 to obtain a second signal VR"';

[0015] processing the second signal VR"'by using an accumulator to obtain a first gain estimation value Ge", replacing a preset current gain estimation value G e ' with the first gain estimation value Ge", using LMS algorithm to continuously perform iteration processing until the first gain estimation value Ge" converges to a stable value as the calibrated gain value G e output.

[0016] In an embodiment of the present application, the output signal Dout' to be mismatch calibrated and the mismatch calibrated output signal Dout are M+N-1 bits.

[0017] In an embodiment of the present application, the process of changing the transfer curve includes:

[0018] When the Dither_1 signal is injected, the transfer curve is translated left and right along the horizontal axis;

[0019] When the estimated value Dd1 is subtracted in the digital domain, the transfer curve is translated up and down along the vertical axis; when the voltage value Vd corresponding to the Dither_1 signal is greater than 0, the transfer curve is translated obliquely downward; when the voltage value Vd corresponding to the Dither_1 signal is less than 0, the transfer curve is translated obliquely upward.

[0020] In an embodiment of the present application, the process of obtaining the weight mismatch information of the capacitance corresponding to each demarcation point according to the maximum value output by the previous LSB interval and the minimum value output by the next LSB interval of each demarcation point includes:

[0021] For each demarcation point, the maximum value Max{Dout_cal|D1(m)=0, Vd>0} of the output of the previous LSB interval of the demarcation point m, the minimum value Min{Dout_cal|D1(m)=1, Vd>0} of the output of the next LSB interval of the demarcation point m, the maximum value Max{Dout_cal|D1(m)=0, Vd<0} of the output of the previous LSB interval of the demarcation point m when the voltage value Vd corresponding to the Dither_1 signal is less than 0, and the minimum value Min{Dout_cal|D1(m)=1, Vd<0} of the output of the next LSB interval of the demarcation point m are counted; the counting result of the demarcation point m is taken as the weight mismatch information of the capacitor corresponding to the demarcation point m; wherein m=1, 2, …, M-1, M, D1(m)=0 represents that the demarcation point m corresponds to the code value 0 in the digital code D1, and D1(m)=1 represents that the demarcation point m corresponds to the code value 1 in the digital code D1.

[0022] In an embodiment of the present application, the process of obtaining the iteration error corresponding to each bit capacitor according to all the weight mismatch information comprises:

[0023] For each weight mismatch information, when the weight mismatch information corresponds to the upward jump of the demarcation point in the changed transfer curve, Max{Dout_cal|D1(m)=0, Vd>0} - Min{Dout_cal|D1(m)=1, Vd<0} is selected as the iteration error of the capacitor corresponding to the weight mismatch information.

[0024] When the weight mismatch information corresponds to the downward jump of the demarcation point in the changed transfer curve, Max{Dout_cal|D1(m)=0, Vd<0} - Min{Dout_cal|D1(m)=1, Vd>0} is selected as the iteration error of the capacitor corresponding to the weight mismatch information.

[0025] In a second aspect, the present application provides a calibration circuit applied to a pipeline successive approximation ADC, comprising:

[0026] a sampling module, configured to sample an input signal V in ;

[0027] a perturbation injection module, configured to inject a Dither_1 signal into the sampled input signal V in to obtain an injected input signal V i ′ n ; wherein the Dither_1 signal is a signal with random polarity change and constant size; after the Dither_1 signal is injected, the transfer curve of the first-stage SAR ADC changes;

[0028] a first-stage SAR ADC configured to quantize the V i n to obtain a digital code D1 and a residual signal VR;

[0029] The disturbance injection module is further configured to inject a Dither_2 signal into the residual signal VR to obtain an injected residual signal VR';

[0030] An amplification module is configured to amplify the injected residual signal VR';

[0031] A second-stage SAR ADC is configured to quantize the amplified injected residual signal VR' to obtain an N-bit digital code D2;

[0032] A gain error calibration module is configured to calibrate a preset gain estimation value G e ′ according to the Dither_2 signal and the injected residual signal VR' to obtain a calibrated gain value G e ;

[0033] A data splicing module is configured to splice the digital code D1 and the digital code D2 according to the calibrated gain value G e to obtain an output signal Dout' to be mismatch calibrated;

[0034] A mismatch calibration module is configured to obtain an estimation value Dd1 of the Dither_1 signal corresponding to a digital domain by using an LMS algorithm, to obtain a re-changed transfer curve by subtracting the estimation value Dd1 from the Dout' in the digital domain, to find M positions jumping from 0 to 1 in the re-changed transfer curve as demarcation points, to obtain weight mismatch information of a capacitor corresponding to each demarcation point according to a maximum value output by a previous LSB interval of each demarcation point and a minimum value output by a subsequent LSB interval of each demarcation point, to obtain an iterative error of the capacitor corresponding to each demarcation point according to all the weight mismatch information, and to obtain M error amounts by processing all the iterative errors by using the LMS algorithm, to subtract an error amount corresponding to a digital code of each demarcation point in the output signal Dout' from the digital code to obtain an output signal Dout after mismatch calibration.

[0035] Advantages of the present application:

[0036] In the scheme provided by the present application, the estimation value Dd2 of the Dither_2 signal corresponding to a digital domain and the injected residual signal VR' are used to calibrate a preset gain estimation value G e ′, and the calibrated gain value G e ​The digital codes D1 and D2 are spliced ​​together to achieve calibration of the inter-stage gain error. The maximum value of the output of the LSB interval before each dividing point and the minimum value of the output of the LSB interval after each dividing point are used to represent the weight mismatch information of the capacitor corresponding to the dividing point. The LMS algorithm is then used to continuously iterate to obtain the corresponding error amount, thereby achieving mismatch calibration of the output signal Dout′ to be calibrated, thereby improving the quantization accuracy and linearity of the ADC. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 A principle block diagram of a pipelined successive approximation ADC according to a calibration method for a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0038] Figure 2 A schematic diagram of the steps of a calibration method for a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0039] Figure 3 A timing diagram of a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0040] Figure 4 A flowchart of a gain error calibration method for a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of a transfer curve corresponding to M=2 in a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0042] Figure 6 A flowchart of a capacitance mismatch calibration method for a pipelined successive approximation ADC provided by an embodiment of the present invention;

[0043] Figure 7 A schematic diagram of the structure of a pipelined successive approximation ADC provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0045] Example 1

[0046] A principle block diagram of a pipeline successive approximation ADC applied to a calibration method of the pipeline successive approximation ADC is provided in the embodiments of the present application, please refer to Figure 1 From the figure, the Dither signal is injected into the input signal and the residual signal respectively, so as to perform subsequent inter-stage gain error calibration and capacitor mismatch calibration, and the specific calibration steps are introduced below.

[0047] The embodiments of the present application provide a calibration method applied to a pipeline successive approximation ADC, as shown in Figure 2 , which can include:

[0048] S1, sampling the input signal V in and injecting the Dither_1 signal to obtain the injected input signal V i ′ n , quantizing the injected input signal V i ′ n by using the first SAR ADC to obtain the M-bit digital code D1 and the residual signal VR; wherein the Dither_1 signal is a signal with random polarity change and constant size; after injecting the Dither_1 signal, the transfer curve of the first SAR ADC changes.

[0049] For S1, it can include:

[0050] S11, sampling the input signal V in and injecting the Dither_1 signal to obtain the injected input signal V i ′ n .

[0051] After sampling the input signal V in by using the sampling switch Φ_s, the Dither_1 signal is injected into the sampled signal by using the switch Φ_d1 to obtain the injected input signal V i ′ n . The Dither_1 signal is a disturbance signal with random polarity change and constant size; after injecting the Dither_1 signal, the transfer curve of the first SAR ADC changes correspondingly, so as to be used for subsequent calibration. The transfer curve of the first SAR ADC represents the relationship between the analog input voltage of the SAR ADC and the digital output code. The specific change mode of the transfer curve is described below.

[0052] Optionally, since there is usually a one-bit redundant connection bit between the two SAR ADCs, the Dither_1 signal can be 1 / 2LSB. 1 / 2LSB represents half of the least significant bit in the first SAR ADC, representing the minimum voltage change that the first SAR ADC can distinguish.

[0053] S12, quantizing the injected input signal V i n to obtain an M-bit digital code D1 and a residual signal VR.

[0054] M represents the bit number of the first-stage SAR ADC, the digital code D1 represents the quantization result of the first-stage SAR ADC, and the residual signal represents the difference between the original analog input signal and the digital output signal generated after conversion by the first-stage SAR ADC.

[0055] Specifically, the clock signal for controlling the injection of the Dither_1 signal is synchronized with the enable clock signal for controlling the first quantization of the comparator in the first-stage SAR ADC.

[0056] It can be understood that the clock signal for controlling the injection of the Dither_1 signal controls the injection of the Dither_1 signal into the sampled signal by controlling the switch Φ_d1.

[0057] S2, injecting a Dither_2 signal into the residual signal VR to obtain an injected residual signal VR', and after the injected residual signal VR' is amplified, quantizing the amplified signal by the second-stage SAR ADC to obtain an N-bit digital code D2.

[0058] For S2, the residual signal VR' is amplified by the operational amplifier AMP in Figure 1 and is transmitted to the second-stage SAR ADC. N represents the bit number of the second-stage SAR ADC.

[0059] Since the residual signal in the pipeline successive approximation ADC is usually the residual signal obtained after the last inversion of the internal DAC output, the clock for controlling the injection of the Dither_2 signal into the residual signal needs to be strictly controlled after the last inversion of the DAC in the first-stage SAR ADC. The DAC in the first-stage SAR ADC is a key component that converts the digital output generated by the successive approximation algorithm into an analog voltage.

[0060] It can be understood that the clock signal for controlling the injection of the Dither_2 signal controls the injection of the Dither_2 signal into the sampled signal by controlling the switch Φ_d2. A timing diagram of a pipeline successive approximation ADC provided by an embodiment of the present application is shown in Figure 3 . As can be seen from Figure 3 , the signal for controlling the switch Φ_d1 is synchronized with the enable clock signal for controlling the first quantization of the comparator in the first-stage SAR ADC; and the signal for controlling the switch Φ_d2 is after the last inversion of the DAC in the first-stage SAR ADC. ​

[0061] It can be understood that, in order to calibrate the inter-stage gain error and the DAC capacitor mismatch, first, the Dither_1 signal and the Dither_2 signal are respectively injected into the input signal and the residual signal in the analog domain, and then they are subtracted in the digital backend, and the subsequent calibration method is used for calibration, so as to obtain the calibrated output signal Dout.

[0062] S3, according to the estimated value Dd2 of the Dither_2 signal corresponding to the digital domain and the injected residual signal VR', the preset gain estimate value G e is calibrated to obtain the calibrated gain value G e .

[0063] For S3, it can include:

[0064] S31, the residual signal VR' is used to subtract the product of the estimated value Dd2 and the preset gain estimate value G e to obtain a first signal VR''.

[0065] The Dither_2 signal is a disturbance signal, the estimated value Dd2 is the estimated value of the Dither_2 signal in the digital domain, and the preset gain estimate value G e is a known quantity when S3A is executed for the first time.

[0066] S32, the first signal VR'' is multiplied by the estimated value Dd2 to obtain a first result, and the first result is multiplied by a first iteration step size μ1 to obtain a second signal VR'''.

[0067] S33, the second signal VR''' is processed by using an accumulator to obtain a first gain estimate value Ge'', and the first gain estimate value Ge'' replaces the current preset gain estimate value G e , and the LMS algorithm is used for continuous iteration processing until the first gain estimate value Ge'' converges to a stable value, which is used as the calibrated gain value G e output.

[0068] The first gain estimate value Ge'' obtained by the LMS algorithm replaces the current preset gain estimate value G e , and after the replacement, S3A-S3C are executed again, and the first gain estimate value Ge'' obtained by S33 is iterated until it converges to a stable value with very small difference before and after, which is used as the calibrated gain value G e , so as to calibrate the preset gain estimate value G e . Calibrating the gain error is a prerequisite for the subsequent DAC mismatch calibration method, and the two can be performed at the same time, so as to obtain a high-precision and high-linearity calibration result.

[0069] S4, calibrating the gain value G e The digital code D1 and the digital code D2 are spliced to obtain an output signal Dout' to be mismatch calibrated.

[0070] S4, calibrating the gain value G e The splicing position corresponding to the digital code D1 and the digital code D2 is determined, so that the digital code D1 and the digital code D2 are spliced according to the splicing position to obtain an output signal Dout' to be mismatch calibrated.

[0071] Optionally, since there is usually a one-bit redundant connection bit between the two-stage SAR ADCs, the output signal Dout' to be mismatch calibrated and the output signal Dout after mismatch calibration can be M+N-1 bits.

[0072] Through S2-S3, the Dither_2 signal is injected into the residual signal, and the estimated value Dd2 corresponding to the Dither_2 signal in the digital domain and the residual signal VR' after injection are used to calibrate the preset gain estimation value G e to obtain a calibrated gain value G e ; the calibrated gain value G e is used to splice the digital code D1 and the digital code D2, so as to realize calibration of the inter-stage gain error.

[0073] S5, the estimated value Dd1 corresponding to the Dither_1 signal in the digital domain is obtained by using the LMS algorithm, the output signal Dout' to be mismatch calibrated is subtracted from the estimated value Dd1 in the digital domain to obtain a changed transfer curve again, M positions jumping from 0 to 1 in the changed transfer curve again are found as demarcation points, the weight mismatch information of the capacitor corresponding to each demarcation point is obtained according to the maximum value output in the previous LSB interval of each demarcation point and the minimum value output in the next LSB interval, the iteration error of the capacitor corresponding to each demarcation point is obtained according to all the weight mismatch information, all the iteration errors are processed by using the LMS algorithm to obtain M error amounts, the digital code of each demarcation point in the output signal Dout' to be mismatch calibrated is subtracted from the error amount corresponding to the digital code to obtain an output signal Dout after mismatch calibration.

[0074] For S5, it can include:

[0075] S51, the estimated value Dd1 corresponding to the Dither_1 signal in the digital domain is obtained by using the LMS algorithm, and the output signal Dout' to be mismatch calibrated is subtracted from the estimated value Dd1 in the digital domain to obtain a changed transfer curve again.

[0076] Specifically, the input signal V inWhen the sampling and the Dither_1 signal are injected, the transfer curve of the pipeline successive approximation ADC changes correspondingly; when the output signal Dout' to be mismatched and calibrated is subtracted by the estimated value Dd1 in the digital domain, the transfer curve of the pipeline successive approximation ADC also changes correspondingly.

[0077] The process of the change of the transfer curve can include:

[0078] When the Dither_1 signal is injected, the transfer curve is shifted left and right along the horizontal axis;

[0079] When the size of the Dither_1 signal is positive, the transfer curve is shifted left along the horizontal axis; when the size of the Dither_1 signal is negative, the transfer curve is shifted right along the horizontal axis.

[0080] When the estimated value Dd1 is subtracted in the digital domain, the transfer curve is shifted up and down along the vertical axis; when the voltage value Vd corresponding to the Dither_1 signal is greater than 0, the transfer curve is shifted obliquely downward; when the voltage value Vd corresponding to the Dither_1 signal is less than 0, the transfer curve is shifted obliquely upward. Therefore, in the final transfer curve, the shift of the transfer curve occurs in the slope direction.

[0081] In order to ensure the accuracy of the data, the LMS algorithm is used to process the Dither_1 signal to obtain the estimated value Dd1 corresponding to the digital domain.

[0082] In order to facilitate understanding, taking M=2 as an example, the pipeline successive approximation ADC with the mismatch of the capacitor weight is described in detail. The transfer curve of the pipeline successive approximation ADC corresponding to M=2 is shown by the solid line in Figure 5 When the voltage value Vd corresponding to the Dither_1 signal is greater than 0, the transfer curve changed again is shown by the left dashed line of the solid line in Figure 5 When the voltage value Vd corresponding to the Dither_1 signal is less than 0, the transfer curve changed again is shown by the right dashed line of the solid line in Figure 5 In Figure 5 the two different dashed lines in form a shadow area, and the area of the shadow area can represent the mismatch information of the capacitor corresponding to the demarcation point. The flow chart of the capacitor mismatch calibration provided by the embodiment of the present application is shown in Figure 6 The related steps will be described in detail below in combination with Figure 5 and Figure 6 .

[0083] S52, find M positions jumping from 0 to 1 in the transfer curve changed again as demarcation points, and obtain the weight mismatch information of the capacitor corresponding to each demarcation point according to the maximum value output in the previous LSB interval and the minimum value output in the next LSB interval of each demarcation point.

[0084] Specifically, when the SAR ADC has a mismatch in the capacitor weight, a jump up or down will occur at the demarcation point in the transfer curve of the SAR ADC. Taking M=2 as an example, in the transfer curve of the pipeline successive approximation ADC corresponding to M=2, it can be seen that a jump down occurs at the demarcation point corresponding to from 00 to 01, a jump up occurs at the demarcation point corresponding to from 01 to 10, and a jump down occurs at the demarcation point corresponding to from 10 to 11.

[0085] Due to the binary quantization mode of the SAR ADC, the transfer curve change caused by the mismatch in the capacitor weight has a symmetric characteristic. When the same bit output jumps from 0 to 1, the jumps occurring at different positions of the transfer curve are the same. Therefore, only the positions of M jumps from 0 to 1 need to be selected as the demarcation points, and the middle section is usually selected as the interval to ensure accuracy.

[0086] Specifically, according to the maximum value output by the previous LSB interval of each demarcation point and the minimum value output by the next LSB interval of each demarcation point, the process of obtaining the weight mismatch information of the capacitor corresponding to each demarcation point can include:

[0087] For each demarcation point, the maximum value Max{Dout_cal|D1(m)=0, Vd>0} output by the previous LSB interval of the demarcation point m and the minimum value Min{Dout_cal|D1(m)=1, Vd>0} output by the next LSB interval of the demarcation point m are counted when the voltage value Vd corresponding to the Dither_1 signal is greater than 0, and the maximum value Max{Dout_cal|D1(m)=0, Vd<0} output by the previous LSB interval of the demarcation point m and the minimum value Min{Dout_cal|D1(m)=1, Vd<0} output by the next LSB interval of the demarcation point m are counted when the voltage value Vd corresponding to the Dither_1 signal is less than 0; the counting result of the demarcation point m is taken as the weight mismatch information of the capacitor corresponding to the demarcation point m; wherein m=1, 2, …, M-1, M, D1(m)=0 represents that the demarcation point m corresponds to a code value of 0 in the digital code D1, and D1(m)=1 represents that the demarcation point m corresponds to a code value of 1 in the digital code D1. LSB represents the least significant bit, and the LSB interval represents the interval corresponding to the least significant bit, which refers to the voltage range in the analog input voltage range corresponding to the smallest change in the ADC output code.

[0088] The same input signal can obtain different digital code outputs after superimposing different Dither disturbances. In Figure 5 , it can be seen that the transfer curves corresponding to Vd>0 and Vd<0 represented by different dashed lines have corresponding horizontal windows near the demarcation points, and the horizontal windows correspond to Figure 5The area of the shadow region can represent the mismatch information of the capacitance corresponding to the demarcation point. The maximum value output in the previous LSB interval and the minimum value output in the next LSB interval are used to represent the area of the shadow region corresponding to the demarcation point, so that the mismatch information of the capacitance corresponding to the demarcation point is obtained. Taking the case of M=2 as an example, the maximum value of the 01 segment and the minimum value of the 10 segment are found; the maximum value of the 10 segment and the minimum value of the 11 segment; the maximum value of the 01 segment and the minimum value of the 10 segment represent the weight mismatch information of the high-order capacitance in the pipeline successive approximation type ADC of M=2, and the maximum value of the 10 segment and the minimum value of the 11 segment represent the weight mismatch information of the low-order capacitance in the pipeline successive approximation type ADC of M=2. By using the maximum value output in the previous LSB interval and the minimum value output in the next LSB interval, the area of the shadow region corresponding to the demarcation point is obtained, so that the weight mismatch information of the capacitance in the pipeline successive approximation type ADC is specifically represented, so as to facilitate subsequent mismatch calibration.

[0089] S53, according to all the weight mismatch information, the iteration error of the capacitance corresponding to each demarcation point is obtained, all the iteration errors are processed by using the LMS algorithm, M error amounts are obtained, the digital code of each demarcation point corresponding bit in the output signal Dout' to be mismatch calibrated is subtracted by the error amount corresponding to the digital code, and the output signal Dout after mismatch calibration is obtained.

[0090] Specifically, the process of obtaining the iteration error of each bit capacitance according to all the weight mismatch information can include:

[0091] For each weight mismatch information, when the weight mismatch information corresponds to the upward jump of the demarcation point in the changed transfer curve again, Max{Dout_cal|D1(m)=0, Vd>0}-Min{Dout_cal|D1(m)=1, Vd<0} is selected as the iteration error of the capacitance corresponding to the weight mismatch information; when the transfer curve jumps upward, the iteration error is less than 0.

[0092] When the weight mismatch information corresponds to the downward jump of the demarcation point in the changed transfer curve again, Max{Dout_cal|D1(m)=0, Vd<0}-Min{Dout_cal|D1(m)=1, Vd>0} is selected as the iteration error of the capacitance corresponding to the weight mismatch information. When the transfer curve jumps downward, the iteration error is greater than 0.

[0093] After all the iteration errors are processed by using the LMS algorithm to obtain M error amounts, the digital code of each demarcation point corresponding bit in the output signal Dout' to be mismatch calibrated is subtracted by the error amount corresponding to the digital code, and the output signal Dout after mismatch calibration is obtained.

[0094] The corresponding error amount is obtained by processing all iteration errors by using the LMS algorithm; and the output signal Dout' to be mismatched calibrated is calibrated by using the corresponding error amount, so that the output signal Dout after mismatch calibration is obtained.

[0095] The embodiment of the application uses the maximum value of the output of the LSB interval before the demarcation point and the minimum value of the output of the LSB interval after the demarcation point to represent the area of the shadow area corresponding to the demarcation point, so that the weight mismatch information of the capacitor corresponding to the demarcation point is obtained; the LMS algorithm is used to process all the weight mismatch information, so that M error amounts are obtained, so that the calibration of the output signal Dout' to be mismatched calibrated is completed, and the output signal Dout after mismatch calibration is output.

[0096] The mismatch calibration method applied to the pipeline successive approximation type ADC provided by the embodiment of the application mainly includes inter-stage gain error calibration and DAC capacitor mismatch calibration. e The Dither_2 signal corresponding to the estimation value Dd2 in the digital domain is used to calibrate the preset gain estimation value G e ; the calibrated gain value G e is used to splice the digital code D1 and the digital code D2, so that the calibration of the inter-stage gain error is realized, and the output signal Dout' to be mismatched calibrated is output; the corresponding Dither signal is subtracted from the output signal Dout' to be mismatched calibrated in the digital domain, so that the demarcation point is found, the maximum value of the output of the LSB interval before each demarcation point and the minimum value of the output of the LSB interval after the demarcation point are used to represent the weight mismatch information of the capacitor corresponding to the demarcation point; and the LMS algorithm is used to continuously iterate to obtain the corresponding error amount, so that the mismatch calibration of the output signal Dout' to be mismatched calibrated is realized, and the quantization precision and the linearity of the ADC are improved.

[0097] Embodiment 2

[0098] The embodiment of the application provides a calibration circuit applied to a pipeline successive approximation type ADC, as shown in Figure 7 , which can include:

[0099] A sampling module is configured to sample an input signal V in .

[0100] A disturbance injection module is configured to inject a Dither_1 signal into the sampled input signal V in to obtain an injected input signal V i '. n; wherein the Dither_1 signal is a signal with random polarity and constant magnitude; after the Dither_1 signal is injected, the transfer curve of the first-stage SAR ADC changes;

[0101] a first-stage SAR ADC, configured to quantize V i ′ n to obtain a digital code D1 and a residual signal VR;

[0102] a disturbance injection module, configured to inject a Dither_2 signal into the residual signal VR to obtain an injected residual signal VR';

[0103] an amplification module, configured to amplify the injected residual signal VR';

[0104] a second-stage SAR ADC, configured to quantize the amplified injected residual signal VR' to obtain an N-bit digital code D2;

[0105] a gain error calibration module, configured to calibrate a preset gain estimation value G e ′ according to the Dither_2 signal and the residual signal VR' to obtain a calibrated gain value G e ;

[0106] a data splicing module, configured to splice the digital code D1 and the digital code D2 according to the calibrated gain value G e to obtain an output signal Dout' to be mismatch calibrated;

[0107] a mismatch calibration module, configured to obtain an estimation value Dd1 of the Dither_1 signal in the digital domain by using an LMS algorithm, to obtain a re-changed transfer curve by subtracting the estimation value Dd1 from the output signal Dout' in the digital domain, to find M positions jumping from 0 to 1 in the re-changed transfer curve as demarcation points, to obtain weight mismatch information of a capacitor corresponding to each demarcation point according to a maximum value output in a previous LSB interval of each demarcation point and a minimum value output in a next LSB interval, to obtain an iterative error of the capacitor corresponding to each demarcation point according to all the weight mismatch information, and to obtain M error amounts by processing all the iterative errors by using the LMS algorithm, to subtract an error amount corresponding to a digital code of each demarcation point in the output signal Dout' from the digital code to obtain a mismatch calibrated output signal Dout.

[0108] The working process of the sampling module corresponds to S11 in Embodiment 1, the working process of the disturbance injection module corresponds to S11 and S2 in Embodiment 1, the working process of the first-stage SAR ADC corresponds to S12 in Embodiment 1, the working process of the amplification module corresponds to S2 in Embodiment 1, the working process of the second-stage SAR ADC corresponds to S2 in Embodiment 1, the working process of the gain error calibration module corresponds to S3 in Embodiment 1, the working process of the data splicing module corresponds to S4 in Embodiment 1, the working process of the mismatch calibration module corresponds to S5 in Embodiment 1, and the specific processing process of each module can be referred to Embodiment 1, which will not be described here.

[0109] In the scheme provided in the embodiment of the application, the disturbance injection module is used to inject a Dither_1 signal to an input signal and inject a Dither_2 signal to a residual signal; the gain error calibration module is used to obtain a calibrated gain value from a preset gain estimation value; the data splicing module is used to splice the digital code D1 and the digital code D2 by using the calibrated gain value, so as to realize the calibration of the inter-stage gain error; and the mismatch calibration module is used to calibrate the DAC capacitor mismatch, so as to output an output signal Dout after mismatch calibration, thereby improving the quantization precision and linearity of the ADC.

[0110] It should be noted that, in the description of the application, the terms "first" and "second" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0111] Each embodiment in the specification is described in a related manner, and the same and similar parts between each embodiment can be referred to each other, and each embodiment mainly explains the difference from other embodiments. Especially, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the related parts can be referred to the part of the method embodiment.

[0112] The above only describes the preferred embodiments of the application, and is not used to limit the protection scope of the application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the application shall be included in the protection scope of the application.

Claims

1. A calibration method for a pipelined successive approximation ADC, characterized in that: include: For input signal V in Sampling and injecting Dither_1 signal to obtain the injected input signal , using the first stage SAR ADC to process the injected input signal Quantization is performed to obtain an M-bit digital code D1 and a residual signal VR; wherein the Dither_1 signal is a signal with randomly changing polarity and constant magnitude; after the Dither_1 signal is injected, the transfer curve of the first-stage SAR ADC changes; Inject Dither_2 signal into the residual signal VR to obtain the injected residual signal , the residual signal after injection After being amplified, it is quantized by the second-stage SAR ADC to obtain an N-bit digital code D2; the Dither_2 signal is a disturbance signal; According to the estimated value Dd2 of the Dither_2 signal corresponding to the digital domain and the residual signal after injection Estimated gain for the preset Perform gain error calibration to obtain the calibrated gain value G e ; According to the calibrated gain value G e The digital code D1 and the digital code D2 are spliced ​​to obtain the output signal to be mismatched ; The LMS algorithm is used to obtain the estimated value Dd1 of the Dither_1 signal corresponding to the digital domain, and the output signal to be mismatched is used in the digital domain to obtain the estimated value Dd1 of the Dither_1 signal corresponding to the digital domain. Subtract the estimated value Dd1 to obtain a changed transfer curve, find M positions that jump from 0 to 1 in the changed transfer curve as demarcation points, and obtain the weight mismatch information of the capacitor corresponding to each demarcation point according to the maximum value output of the previous LSB interval and the minimum value output of the next LSB interval at each demarcation point; obtain the iterative error of the capacitor corresponding to each demarcation point according to all the weight mismatch information, process all the iterative errors using the LMS algorithm to obtain M error amounts, and convert the output signal to be mismatched into The digital code corresponding to each dividing point in the digits is subtracted from the error amount corresponding to the digital code to obtain the output signal Dout after mismatch calibration.

2. The calibration method for a pipelined successive approximation ADC according to claim 1, wherein: The clock signal used to control the injection of the Dither_1 signal is synchronized with the enable clock signal used to control the comparator in the first-stage SAR ADC to perform the first quantization.

3. The calibration method for a pipelined successive approximation ADC according to claim 1, wherein: According to the estimated value Dd2 of the Dither_2 signal corresponding to the digital domain and the residual signal Estimated gain for the preset Perform calibration to obtain the calibrated gain value G e The process includes: Using the residual signal Subtract the estimated value Dd2 from the preset gain estimated value The product of ; The first signal After multiplying the estimated value Dd2, a first result is obtained, and the first result is multiplied by the first iteration step length Multiply and get the second signal ; The second signal is processed by an accumulator Processing is performed to obtain the first gain estimate , the first gain estimate Replace the current preset gain estimate , the LMS algorithm is used to iterate continuously until the first gain estimate is obtained Converges to a stable value as the calibrated gain value G e Output.

4. The calibration method for a pipelined successive approximation ADC according to claim 1, wherein: The output signal to be mismatch calibrated The output signal Dout after the mismatch correction is M+N-1 bits.

5. The calibration method for a pipelined successive approximation ADC according to claim 1, wherein: The process of changing the transfer curve includes: When the Dither_1 signal is injected, the transfer curve shifts left and right along the horizontal axis; When the estimated value Dd1 is subtracted in the digital domain, the transfer curve shifts up and down along the vertical axis; when the voltage value Vd corresponding to the Dither_1 signal is greater than 0, the transfer curve shifts obliquely downward; when the voltage value Vd corresponding to the Dither_1 signal is less than 0, the transfer curve shifts obliquely upward.

6. The calibration method for a pipelined successive approximation ADC according to claim 1, wherein: The process of obtaining the weight mismatch information of the capacitor corresponding to each dividing point according to the maximum value outputted in the previous LSB interval and the minimum value outputted in the next LSB interval of each dividing point includes: For each dividing point, count the maximum value of the LSB interval output before the dividing point m when the voltage value Vd corresponding to the Dither_1 signal is greater than 0 , the minimum value of the LSB interval output after the dividing point m , when the voltage value Vd corresponding to the Dither_1 signal is less than 0, the maximum value outputted by the LSB interval before the dividing point m is counted , the minimum value of the LSB interval output after the dividing point m ; The statistical result of the demarcation point m is used as the weight mismatch information of the capacitor corresponding to the demarcation point m; wherein, , Indicates that the demarcation point m corresponds to the code value of 0 in the digital code D1, Indicates that the demarcation point m corresponds to the code value of 1 in the digital code D1.

7. The calibration method for a pipelined successive approximation ADC according to claim 6, wherein: The process of obtaining the iterative error corresponding to each capacitor according to all weight mismatch information includes: For each weight mismatch information, when the weight mismatch information corresponds to the upward jump of the demarcation point in the transfer curve that is changed again, select As the iterative error of the capacitance corresponding to the weight mismatch information; When the weight mismatch information corresponds to the downward jump of the demarcation point in the transfer curve that changes again, select The iterative error of the capacitance corresponding to the weight mismatch information.

8. A calibration circuit for a pipelined successive approximation ADC, characterized in that: include: Sampling module, used to sample the input signal V in Take samples; The disturbance injection module is used to inject the disturbance into the sampled input signal V in Inject the Dither_1 signal to get the injected input signal ; Wherein, the Dither_1 signal is a signal with randomly changing polarity and constant magnitude; after the Dither_1 signal is injected, the transfer curve of the first-stage SAR ADC changes; The first stage SAR ADC is used to Quantization is performed to obtain a digital code D1 and a residual signal VR; The disturbance injection module is also used to inject the Dither_2 signal into the residual signal VR to obtain the injected residual signal ; The Dither_2 signal is a disturbance signal; Amplification module for the residual signal to zoom in; The second stage SAR ADC is used to amplify the residual signal Quantization is performed to obtain an N-bit digital code D2; Gain error calibration module, used for adjusting the gain error according to the Dither_2 signal and the residual signal Estimated gain for the preset Perform calibration to obtain the calibrated gain value G e ; The data splicing module is used to obtain the calibrated gain value G e The digital code D1 and the digital code D2 are spliced ​​to obtain the output signal to be mismatched ; The mismatch calibration module is used to obtain the estimated value Dd1 of the Dither_1 signal corresponding to the digital domain using the LMS algorithm, and to obtain the estimated value Dd1 of the Dither_1 signal corresponding to the digital domain using the Subtract the estimated value Dd1 to obtain a changed transfer curve, find M positions that jump from 0 to 1 in the changed transfer curve as the dividing points, and obtain the weight mismatch information of the capacitor corresponding to each dividing point according to the maximum value output of the previous LSB interval and the minimum value output of the next LSB interval at each dividing point; obtain the iterative error of the capacitor corresponding to each dividing point according to all the weight mismatch information, process all the iterative errors using the LMS algorithm to obtain M error amounts, and convert the output signal The digital code corresponding to each dividing point in the digits is subtracted from the error amount corresponding to the digital code to obtain the output signal Dout after mismatch calibration.

Images