eMMC timing adjustment method, system, computer equipment and storage medium

Abstract

The present invention discloses an eMMC timing adjustment method, system, computer equipment and storage medium. The method includes: obtaining multiple first initial phase-shifted clocks according to a first input clock, and obtaining multiple second initial phase-shifted clocks according to a second input clock; inputting multiple first initial phase-shifted clocks and second initial phase-shifted clocks into a first clock selector and a second clock selector respectively, and obtaining first phase-shifted clocks and second phase-shifted clocks respectively; sending a preset command to an eMMC device, and when the transmission command and transmission data returned by the eMMC device meet the preset conditions, traversing the first phase-shifted clock and the second phase-shifted clock, obtaining multiple correct phase-shifted clocks, and determining the optimal phase-shifted clock. In this application, only data input and command input are adjusted, and the timing adjustment is simpler without affecting the data transmission accuracy, while reducing the wiring requirements of the PCB board.

Description

Technical Field

[0001] The present invention relates to the field of eMMC research and development test technology, and in particular to an eMMC timing adjustment method, system, computer equipment and storage medium. Background Art

[0002] The maximum clock frequency of eMMC (Embedded Multi Media Card) in hs200 and hs400 modes is up to 200MHz. When switching to hs200 and hs400 modes, the host can perform a sampling tuning sequence to compensate for timing variations caused by different silicon processes, PCB (printed circuit board) loads, voltages, temperatures, and other factors. The frequency used and the implementation of the tuning process will depend on the host and system implementation to find the best sampling point for the data line.

[0003] Most of the existing tuning processes use eMMC master and eMMC device to communicate data, traversing all clocks to confirm the best timing solution; however, the existing methods have disadvantages such as complex tuning process or low adjustment accuracy, especially the hs400 mode, which has a high frequency and adopts DDR (Double Data Rate, double-rate synchronous dynamic random access memory) sampling method. Therefore, it is very important to balance the complexity of the tuning program and the clock accuracy. Summary of the invention

[0004] In view of this, the purpose of the present invention is to overcome the deficiencies in the prior art and to provide an eMMC timing adjustment method, system, computer device and storage medium.

[0005] The present invention provides the following technical solutions:

[0006] In a first aspect, an eMMC timing adjustment method is provided in an embodiment of the present disclosure, which is applied to an eMMC timing adjustment system, wherein the eMMC timing adjustment system includes a master control, a timing adjustment device, and an eMMC device, wherein the master control includes a first delay module, a second delay module, a first clock selector, and a second clock selector, and the timing adjustment device includes a logic control module, a sending module, a receiving module, and a comparison module. The method includes:

[0007] Obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks;

[0008] Inputting a plurality of the first initial phase-shifted clocks into the first clock selector to obtain a first phase-shifted clock, and inputting a plurality of the second initial phase-shifted clocks into the second clock selector to obtain a second phase-shifted clock;

[0009] Control the sending module to send a preset command to the eMMC device, and when the receiving module receives the transmission command and transmission data returned by the eMMC device, control the comparing module to determine whether the transmission command and the transmission data meet a preset condition;

[0010] When the transmission command and the transmission data meet the preset condition, the logic control module is controlled to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks, and an optimal phase-shifted clock algorithm is used to determine the best phase-shifted clock from each of the correct phase-shifted clocks.

[0011] Preferably, the master control comprises a clock source selector and a clock divider module, and the acquiring of the first input clock and dividing the first input clock to obtain the target operating frequency include:

[0012] Selecting a first input clock from a plurality of clock sources provided by the master control through the clock source selector, and obtaining a preset frequency division coefficient;

[0013] The clock divider module is controlled to divide the first input clock according to the preset division coefficient to obtain the target operating frequency.

[0014] Preferably, the master control further includes a third clock selector, and the obtaining of the second input clock includes:

[0015] Determine the current communication mode;

[0016] If the current communication mode is the HS200 mode, selecting the target operating frequency as the second input clock through the third clock selector;

[0017] If the current communication mode is the HS400 mode, the Data Strobe clock sent by the eMMC device is obtained, and the Data Strobe clock is selected as the second input clock by the third clock selector.

[0018] Preferably, the receiving module includes a command receiving submodule and a data receiving submodule, and the controlling the sending module to send a preset command to the eMMC device, when the receiving module receives the transmission command and transmission data returned by the eMMC device, controlling the comparison module to determine whether the transmission command and the transmission data meet a preset condition, includes:

[0019] When the master sends a start clock adjustment command to the logic control module, the logic control module controls the sending module to send a preset command to the eMMC device, the logic control module controls the command receiving submodule to receive the transmission command returned by the eMMC device, and the logic control module controls the data receiving submodule to receive the transmission data returned by the eMMC device;

[0020] The logic control module controls the comparison module to determine whether the transmission command and the transmission data conform to a preset template;

[0021] When the transmission command and the transmission data conform to the preset template, it is determined that the transmission command and the transmission data satisfy the preset condition.

[0022] Preferably, the preset command is a CMD21 command.

[0023] Preferably, traversing the first phase-shifted clock and the second phase-shifted clock to obtain a plurality of correct phase-shifted clocks, and using an optimal phase-shifted clock algorithm to determine an optimal phase-shifted clock from each of the correct phase-shifted clocks, comprises:

[0024] Projecting the first phase-shifted clock and the second phase-shifted clock onto a two-dimensional plane;

[0025] Control the logic control module to determine a plurality of correct phase-offset clocks among the first phase-offset clock and the second phase-offset clock on the two-dimensional plane, and search for a plurality of candidate phase-offset clocks that meet preset conditions among the correct phase-offset clocks;

[0026] The logic control module is controlled to determine the first phase-shifted clock and the second phase-shifted clock corresponding to the candidate phase-shifted clock closest to the center position of the two-dimensional plane as the optimal phase-shifted clock.

[0027] Preferably, the searching for a plurality of candidate phase-offset clocks that meet preset conditions among the correct phase-offset clocks comprises:

[0028] Determine whether the two-dimensional plane includes an area where four adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes an area where four adjacent clocks are all the correct phase-shifted clocks, determine the area where the four adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock;

[0029] If the two-dimensional plane does not include a region where four adjacent clocks are all the correct phase-shifted clocks, determine whether the two-dimensional plane includes a region where three adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes a region where three adjacent clocks are all the correct phase-shifted clocks, determine the region where the three adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock;

[0030] If the two-dimensional plane does not include an area where three adjacent clocks are all the correct phase-shifted clocks, then determining whether the two-dimensional plane includes an area where two adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes an area where two adjacent clocks are all the correct phase-shifted clocks, determining the area where the two adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock;

[0031] If the two-dimensional plane does not include two adjacent areas where both are the correct phase-shifted clocks, it is determined whether the two-dimensional plane includes an area where the intersection position is the correct phase-shifted clock; if the two-dimensional plane includes an area where the intersection position is the correct phase-shifted clock, the area where the intersection position is the correct phase-shifted clock is determined as the candidate phase-shifted clock.

[0032] In a second aspect, an eMMC timing adjustment system is provided in an embodiment of the present disclosure, wherein the eMMC timing adjustment system includes a timing adjustment device, an eMMC device and a main control, wherein the main control includes a first delay module, a second delay module, a first clock selector and a second clock selector; the timing adjustment device includes a logic control module, a sending module, a receiving module and a comparing module;

[0033] The master control is used to obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks;

[0034] The master control is further configured to input a plurality of the first initial phase-shifted clocks into the first clock selector to obtain a first phase-shifted clock, and input a plurality of the second initial phase-shifted clocks into the second clock selector to obtain a second phase-shifted clock;

[0035] The timing adjustment device is used to control the sending module to send a preset command to the eMMC device, control the receiving module to receive the transmission command and transmission data returned by the eMMC device, and control the comparison module to determine whether the transmission command and the transmission data meet a preset condition;

[0036] The timing adjustment device is further used to control the logic control module to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks when the transmission command and the transmission data meet the preset condition, and use the optimal phase-shifted clock algorithm to determine the best phase-shifted clock from each of the correct phase-shifted clocks;

[0037] The timing adjustment device is also used to receive a preset command sent by the master control, and return the transmission command and the transmission data.

[0038] In a third aspect, a computer device is provided in an embodiment of the present disclosure, the computer device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the steps of the eMMC timing adjustment method described in the first aspect when executing the computer program.

[0039] In a fourth aspect, a computer-readable storage medium is provided in an embodiment of the present disclosure, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the eMMC timing adjustment method described in the first aspect are implemented.

[0040] Beneficial effects of this application:

[0041] The eMMC timing adjustment method provided in the embodiment of the present application is applied to the eMMC timing adjustment system, wherein the eMMC timing adjustment system comprises a main control, a timing adjustment device and an eMMC device, wherein the main control comprises a first delay module, a second delay module, a first clock selector and a second clock selector; the timing adjustment device comprises a logic control module, a sending module, a receiving module and a comparing module, and the method comprises: obtaining a first input clock, dividing the first input clock to obtain a target operating frequency, inputting the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtaining a second input clock, inputting the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks; dividing the plurality of first initial phase The first phase-shifted clock is input into the first clock selector to obtain the first phase-shifted clock, and the multiple second initial phase-shifted clocks are input into the second clock selector to obtain the second phase-shifted clock; the sending module is controlled to send a preset command to the eMMC device, and when the receiving module receives the transmission command and transmission data returned by the eMMC device, the comparison module is controlled to determine whether the transmission command and the transmission data meet the preset conditions; when the transmission command and the transmission data meet the preset conditions, the logic control module is controlled to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks, and the optimal phase-shifted clock algorithm is used to determine the best phase-shifted clock from each correct phase-shifted clock. In this application, only data input and command input are adjusted, and the timing adjustment is simpler without affecting the data transmission accuracy, while reducing the wiring requirements of the PCB board.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and understandable, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work. In each of the drawings, similar components are numbered similarly.

[0044] Figure 1 A flow chart of an eMMC timing adjustment method provided in an embodiment of the present application is shown;

[0045] Figure 2 A schematic diagram of the structure of an eMMC timing adjustment system provided in an embodiment of the present application is shown;

[0046] Figure 3 A schematic diagram showing the format of a preset command provided in an embodiment of the present application is shown;

[0047] Figure 4 A schematic diagram of the format of a preset template provided in an embodiment of the present application is shown;

[0048] Figure 5 One of the optimal phase offset clock selection schemes provided by an embodiment of the present application is shown;

[0049] Figure 6 A second optimal phase offset clock selection scheme provided in an embodiment of the present application is shown;

[0050] Figure 7 The third optimal phase offset clock selection scheme provided by the embodiment of the present application is shown;

[0051] Figure 8 A fourth optimal phase offset clock selection scheme provided in an embodiment of the present application is shown;

[0052] Fig. 9 A schematic diagram of the structure of another eMMC timing adjustment system provided in an embodiment of the present application is shown;

[0053] Fig.10 A schematic diagram of the structure of a computer device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0054] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0055] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0056] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0057] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the template are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0059] Example 1

[0060] like Figure 1 As shown, it is a flowchart of an eMMC timing adjustment method in an embodiment of the present application. The eMMC timing adjustment method provided in the embodiment of the present application is applied to an eMMC timing adjustment system, wherein the eMMC timing adjustment system includes a timing adjustment device, an eMMC device and a main control, wherein the main control includes a first delay module, a second delay module, a first clock selector and a second clock selector; the timing adjustment device includes a logic control module sending module, a receiving module and a comparison module, the eMMC device is a storage device, and is applicable to any device that complies with the eMMC protocol, the main control is connected to the timing adjustment device, and the timing adjustment device is connected to the eMMC device, and the specific method includes the following steps:

[0061] Step S110, obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks.

[0062] Specifically, the master controller provides multiple clock sources, which may be 1500MHz, 1200MHz, 1000MHz, 933MHz, 800MHz, 400MHz, etc. Different external master controllers may provide different clock source frequencies, which may be implemented according to specific needs, and this embodiment does not limit this.

[0063] like Figure 2 As shown, the clock source selector selects the first input clock from the multiple clock sources provided by the master control and obtains the preset division coefficient. Then the clock divider module divides the first input clock according to the preset division coefficient to achieve the target operating frequency of data transmission. For example, the first input clock selected by the clock source selector is 800MHz, and the preset division coefficient is 4. Then the target operating frequency obtained by the clock divider module is 800÷4=200MHz.

[0064] Specifically, the target operating frequency is input into the first delay module to obtain multiple first initial phase offset clocks for timing adjustment. The first initial phase offset clocks include 8, expressed as drv degree phase0-7, which respectively represent the data transmission clock phase offsets of 0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315° after frequency division.

[0065] Further, it is determined whether the current communication mode is HS200 mode or HS400 mode. When the current communication mode is HS200 mode, the target operating frequency is selected as the second input clock through the third clock selector; when the current communication mode is HS400 mode, the Data Strobe clock sent by the eMMC device is obtained, and the Data Strobe clock is selected as the second input clock through the third clock selector. The determined second input clock is input into the second delay module to obtain multiple second initial phase offset clocks for timing adjustment. The second initial phase offset clock includes 8, which are represented by sample degreephase0-7. In HS200 mode, the phase offset of the target operating frequency after frequency division is 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°, which is the same as the first initial phase offset clock; in HS400 mode, the input Data Strobe clock phase offset is 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°.

[0066] Step S120: inputting a plurality of the first initial phase-shifted clocks into the first clock selector to obtain a first phase-shifted clock, and inputting a plurality of the second initial phase-shifted clocks into the second clock selector to obtain a second phase-shifted clock.

[0067] Preferably, if Figure 2 As shown, after a plurality of first initial phase-shifted clocks are input into a first clock selector, a first phase-shifted clock is selected through the first clock selector, which is mainly used for command input for data sampling. A plurality of second initial phase-shifted clocks are input into a second clock selector, and a second phase-shifted clock is selected through the second clock selector, which is mainly used for data input for data sampling.

[0068] It can be understood that the first phase-shifted clock and the second phase-shifted clock are only adjusted for command input and data input. The reason is that when writing data, the data goes from the master control to the eMMC device. The host can find the best waveform by itself and send it to the eMMC device, which is usually not affected by the eMMC device. However, the data input and command input are from the eMMC device to the master control. Different eMMC devices have a certain impact on the data sampling accuracy of the master control, so the timing of the data input and command input needs to be adjusted.

[0069] Step S130, controlling the sending module to send a preset command to the eMMC device, and when the receiving module receives the transmission command and transmission data returned by the eMMC device, controlling the comparing module to determine whether the transmission command and the transmission data meet a preset condition.

[0070] In this embodiment, the receiving module includes a command receiving submodule and a data receiving submodule.

[0071] When the master control sends a start clock adjustment command to the logic control module of the timing adjustment device, the logic control module starts the clock adjustment process, that is, the logic control module controls the sending module to send a preset command to the eMMC device. After the eMMC device receives the preset command sent by the sending module, it sends a transmission command in reply and sends transmission data to the master control. At this time, the logic control module controls the command receiving submodule to receive the transmission command returned by the eMMC device, and controls the data receiving submodule to receive the transmission data returned by the eMMC device.

[0072] It should be noted that, in this embodiment, the preset command is the CMD21 command (format as Figure 3 As shown), in other embodiments, the format of the preset command can be determined according to actual conditions, and this application does not limit this.

[0073] Then the logic control module controls the comparison module to determine whether the transmission command and the transmission data conform to the standard preset template (format such as Figure 4 ), when the transmission command and the transmission data meet the preset template, it is determined that the transmission command and the transmission data meet the preset conditions, and the result is fed back to the logic control module.

[0074] The preset template of the present application is fixed and has the characteristics of high noise, deterministic jitter, etc., which is conducive to improving the accuracy of timing adjustment.

[0075] Step S140, when the transmission command and the transmission data meet the preset condition, control the logic control module to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks, and use the optimal phase-shifted clock algorithm to determine the best phase-shifted clock from each of the correct phase-shifted clocks.

[0076] Preferably, when the transmission command and the transmission data meet the preset condition, the control logic control module traverses all phase-shifted clocks in the first phase-shifted clock drv degree phase0-7 and the second phase-shifted clock sample degree phase0-7 to determine multiple correct phase-shifted clocks.

[0077] like Figures 5 to 8 , projecting the first phase-shifted clock and the second phase-shifted clock onto a two-dimensional plane. Searching for multiple candidate phase-shifted clocks that meet preset conditions among multiple correct phase-shifted clocks on the two-dimensional plane, and then controlling the logic control module to determine the first phase-shifted clock and the second phase-shifted clock corresponding to the candidate phase-shifted clock closest to the center of the two-dimensional plane as the optimal phase-shifted clock. The specific steps are as follows:

[0078] (1) Determine whether the two-dimensional plane contains an area with four adjacent clocks that are all correct phase offsets. If the two-dimensional plane contains an area with four adjacent clocks that are all correct phase offsets, determine the area with the four adjacent clocks that are all correct phase offsets as a candidate phase offset clock. If there are multiple candidate phase offset clocks, determine the first phase offset clock and the second phase offset clock corresponding to the candidate phase offset clock closest to the center of the two-dimensional plane as the best phase offset clock. For example, Figure 5As shown, the horizontal axis represents the second phase offset clock, which are sample degree phase0-7 respectively, and the vertical axis represents the first phase offset clock, which are drv degree phase0-7 respectively. The corresponding positions of the horizontal axis and the vertical axis are marked in black, that is, the correct phase offset clock, indicating that the first phase offset clock and the second phase offset clock of the corresponding position are selected. When executing command sending, command receiving, data receiving and preset template comparison, the transmission command and transmission data can be correctly received, and the transmission command and transmission data are the same as the preset standard template. The four adjacent positions of position 1 are all marked in black, which are candidate phase offset clocks, and the four adjacent positions of position 2 are all marked in black, which are also candidate phase offset clocks; according to the center optimal principle, position 2 is closer to the center position 3 than position 1, so the first phase offset clock and the second phase offset clock corresponding to position 2 are the best phase offset clocks.

[0079] (2) If the two-dimensional plane in the previous step (1) does not contain an area with four adjacent clocks that are all correct phase offsets, then determine whether the two-dimensional plane contains an area with three adjacent clocks that are all correct phase offsets. If the two-dimensional plane contains an area with three adjacent clocks that are all correct phase offsets, determine the area with the three adjacent clocks that are all correct phase offsets as a candidate phase offset clock. If there are multiple candidate phase offset clocks, determine the first phase offset clock and the second phase offset clock corresponding to the candidate phase offset clock closest to the center of the two-dimensional plane as the best phase offset clock. For example, Figure 6 As shown, the three adjacent upper, lower and left clocks at position 1 are all correct phase-shifted clocks and are candidate phase-shifted clocks, and the three adjacent upper, lower and left clocks at position 2 are all correct phase-shifted clocks and are also candidate phase-shifted clocks; according to the center optimal principle, position 2 is closer to the center position 3 than position 1, so the first phase-shifted clock and the second phase-shifted clock corresponding to position 2 are the optimal phase-shifted clocks.

[0080] (3) If the two-dimensional plane in the previous step (2) does not contain an area with three adjacent clocks that are all correct phase offsets, then determine whether the two-dimensional plane contains an area with two adjacent clocks that are all correct phase offsets. If the two-dimensional plane contains an area with two adjacent clocks that are all correct phase offsets, determine the area containing the two adjacent clocks that are all correct phase offsets as a candidate phase offset clock. If there are multiple candidate phase offset clocks, determine the first phase offset clock and the second phase offset clock corresponding to the candidate phase offset clock closest to the center of the two-dimensional plane as the best phase offset clock. For example, Figure 7As shown, the two adjacent upper and lower clocks at position 1 are both correct phase-shifted clocks and are candidate phase-shifted clocks, and the two adjacent upper and lower clocks at position 2 are both correct phase-shifted clocks and are also candidate phase-shifted clocks; according to the center optimal principle, position 2 is closer to the center position 3 than position 1, so the first phase-shifted clock and the second phase-shifted clock corresponding to position 2 are the optimal phase-shifted clocks.

[0081] (4) If the two-dimensional plane in the previous step (3) does not contain an area where two adjacent clocks are both correct phase offsets, determine whether the two-dimensional plane contains an area where the intersection position is a correct phase offset clock. If the two-dimensional plane contains an area where the intersection position is a correct phase offset clock, determine the area where the intersection position is a correct phase offset clock as a candidate phase offset clock. If there are multiple candidate phase offset clocks, determine the first phase offset clock and the second phase offset clock corresponding to the candidate phase offset clock closest to the center of the two-dimensional plane as the best phase offset clock. For example, Figure 8 As shown, position 1 and position 2 are candidate phase-shifted clocks; according to the center optimal principle, position 2 is closer to the center position 3 than position 1, so the first phase-shifted clock and the second phase-shifted clock corresponding to position 2 are the optimal phase-shifted clocks.

[0082] The logic control module controls the use of the optimal phase offset clock algorithm to determine the optimal phase offset clock and feeds it back to the main control, that is, the main control starts the fixed frequency clock adjustment, and the timing adjustment device performs the fixed frequency clock adjustment, including data sending, data receiving, data comparison, and obtaining the optimal solution, and feeds back the optimal solution to the main control. The adjustment process does not require the participation of the main control, reducing the main control load, making it easier for software personnel to operate, faster to adjust, and realizing a more accurate eMMC timing adjustment method.

[0083] The eMMC timing adjustment method provided in the embodiment of the present application is applied to the eMMC timing adjustment system, wherein the eMMC timing adjustment system includes a timing adjustment device, an eMMC device and a main control, wherein the main control includes a first delay module, a second delay module, a first clock selector and a second clock selector, and the timing adjustment device includes a logic control module, a sending module, a receiving module and a comparing module, wherein the method includes: obtaining a first input clock, dividing the first input clock to obtain a target operating frequency, inputting the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtaining a second input clock, inputting the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks; and dividing the plurality of first initial phase The first phase-shifted clock is input into the first clock selector to obtain the first phase-shifted clock, and the multiple second initial phase-shifted clocks are input into the second clock selector to obtain the second phase-shifted clock; the sending module is controlled to send a preset command to the eMMC device, and when the receiving module receives the transmission command and transmission data returned by the eMMC device, the comparison module is controlled to determine whether the transmission command and the transmission data meet the preset conditions; when the transmission command and the transmission data meet the preset conditions, the logic control module is controlled to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks, and the optimal phase-shifted clock algorithm is used to determine the best phase-shifted clock from each correct phase-shifted clock. In this application, only data input and command input are adjusted, and the timing adjustment is simpler without affecting the data transmission accuracy, while reducing the wiring requirements of the PCB board.

[0084] Example 2

[0085] like Fig. 9 , which is a structural schematic diagram of an eMMC timing adjustment system 900 in an embodiment of the present application, wherein the eMMC timing adjustment system includes a timing adjustment device 910, a main control 920 and an eMMC device 930, wherein the main control 920 includes a first delay module 921, a second delay module 922, a first clock selector 923 and a second clock selector 924, and the timing adjustment device 910 includes a logic control module 911, a sending module 912, a receiving module 913 and a comparing module 914;

[0086] The master control 920 is used to obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module 921, obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module 922, and obtain a plurality of second initial phase offset clocks;

[0087] The master control 920 is further configured to input a plurality of the first initial phase-shifted clocks into the first clock selector 923 to obtain a first phase-shifted clock, and input a plurality of the second initial phase-shifted clocks into the second clock selector 924 to obtain a second phase-shifted clock;

[0088] The timing adjustment device 910 is used to control the sending module 912 to send a preset command to the eMMC device 930, and control the receiving module 913 to receive the transmission command and transmission data returned by the eMMC device 930, and control the comparison module 914 to determine whether the transmission command and the transmission data meet a preset condition;

[0089] The timing adjustment device 910 is further configured to control the logic control module 911 to traverse the first phase-shifted clock and the second phase-shifted clock to obtain a plurality of correct phase-shifted clocks when the transmission command and the transmission data meet the preset condition, and to determine the best phase-shifted clock from each of the correct phase-shifted clocks using the best phase-shifted clock algorithm;

[0090] The timing adjustment device 910 is further configured to receive a preset command sent by the master control, and return the transmission command and the transmission data.

[0091] The eMMC timing adjustment system 900 provided in the embodiment of the present application only adjusts data input and command input, which makes timing adjustment simpler without affecting data transmission accuracy and reduces the wiring requirements of the PCB board.

[0092] Example 3

[0093] The present application also provides a computer device. Fig.10 , Fig.10 A schematic diagram of the structure of a computer device provided in this embodiment.

[0094] The computer device 10 includes a memory 101, a processor 102, and a network interface 103 that are interconnected and communicated through a system bus. It should be noted that the figure only shows a computer device 10 having a memory 101, a processor 102, and a network interface 103, but it should be understood that it is not required to implement all the components shown, and more or fewer components can be implemented instead. Among them, those skilled in the art can understand that the computer device here is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application specific integrated circuits (ASIC), programmable gate arrays (FPGA), digital signal processors (DSP), embedded devices, etc.

[0095] The computer device may be a computing device such as a desktop computer, a notebook, a PDA, a cloud server, etc. The computer device may interact with a user through a keyboard, a mouse, a remote controller, a touch pad, or a voice control device.

[0096] The memory 101 includes at least one type of readable storage medium, and the readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or D slot compatibility test memory, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 101 can be an internal storage unit of the computer device 10, such as a hard disk or memory of the computer device 10. In other embodiments, the memory 101 can also be an external storage device of the computer device 10, such as a plug-in hard disk equipped on the computer device 10, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), etc. Of course, the memory 101 can also include both the internal storage unit of the computer device 10 and its external storage device. In this embodiment, the memory 101 is generally used to store the operating system and various application software installed on the computer device 10, such as computer readable instructions of the slot compatibility test method, etc. In addition, the memory 101 can also be used to temporarily store various data that have been output or will be output.

[0097] The processor 102 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor, or other eMMC timing adjustment chip in some embodiments. The processor 102 is generally used to control the overall operation of the computer device 10. In this embodiment, the processor 102 is used to run computer-readable instructions or process data stored in the memory 101, such as computer-readable instructions for running the slot compatibility test method.

[0098] The network interface 103 may include a wireless network interface or a wired network interface. The network interface 103 is generally used to establish a communication connection between the computer device 10 and other electronic devices.

[0099] The computer device provided in this embodiment can execute the above-mentioned eMMC timing adjustment method. Here, the eMMC timing adjustment method can be the eMMC timing adjustment method of each of the above-mentioned embodiments.

[0100] Example 4

[0101] This embodiment further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the eMMC timing adjustment method in the embodiment are implemented.

[0102] In this embodiment, the computer-readable storage medium includes flash memory, hard disk, multimedia card, card-type memory (for example, SD or DX memory, etc.), random access memory (RAM), static random access memory (SRAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), programmable read-only memory (PROM), magnetic memory, disk, optical disk, etc. In some embodiments, the computer-readable storage medium can be an internal storage unit of a computer device, such as a hard disk or memory of the computer device. In other embodiments, the computer-readable storage medium can also be an external storage device of a computer device, such as a plug-in hard disk equipped on the computer device, a smart memory card (Smart Media Card, referred to as SMC), a secure digital (Secure Digital, referred to as SD) card, a flash card, etc. Of course, the computer-readable storage medium can also include both the internal storage unit of the computer device and its external storage device. In this embodiment, the computer-readable storage medium is generally used to store an operating system and various application software installed on the computer device. In addition, the computer-readable storage medium can also be used to temporarily store various types of data that have been output or are to be output.

[0103] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in an alternative implementation, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the structure diagram and / or the flow chart, and the combination of boxes in the structure diagram and / or the flow chart, can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0104] In addition, the functional modules or units in the various embodiments of the present invention may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0105] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium can be a non-volatile storage medium or a volatile storage medium. For example, the storage medium can be: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk, and other media that can store program codes.

[0106] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. An eMMC timing adjustment method, characterized in that: Applied to an eMMC timing adjustment system, the eMMC timing adjustment system includes a master control, a timing adjustment device and an eMMC device, the master control includes a first delay module, a second delay module, a first clock selector and a second clock selector, the timing adjustment device includes a logic control module, a sending module, a receiving module and a comparison module, and the method includes: Obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks; Inputting a plurality of the first initial phase-shifted clocks into the first clock selector to obtain a first phase-shifted clock, and inputting a plurality of the second initial phase-shifted clocks into the second clock selector to obtain a second phase-shifted clock; Control the sending module to send a preset command to the eMMC device, and when the receiving module receives the transmission command and transmission data returned by the eMMC device, control the comparing module to determine whether the transmission command and the transmission data meet a preset condition; When the transmission command and the transmission data meet the preset condition, the logic control module is controlled to traverse the first phase-shifted clock and the second phase-shifted clock to obtain multiple correct phase-shifted clocks, and an optimal phase-shifted clock algorithm is used to determine the best phase-shifted clock from each of the correct phase-shifted clocks.

2. The eMMC timing adjustment method according to claim 1, characterized in that: The master control includes a clock source selector and a clock divider module, and the first input clock is obtained, and the first input clock is divided to obtain a target operating frequency, including: Selecting a first input clock from a plurality of clock sources provided by the master control through the clock source selector, and obtaining a preset frequency division coefficient; The clock divider module is controlled to divide the first input clock according to the preset division coefficient to obtain the target operating frequency.

3. The eMMC timing adjustment method according to claim 1, characterized in that: The master control further includes a third clock selector, and the obtaining of the second input clock includes: Determine the current communication mode; If the current communication mode is the HS200 mode, selecting the target operating frequency as the second input clock through the third clock selector; If the current communication mode is the HS400 mode, the Data Strobe clock sent by the eMMC device is obtained, and the Data Strobe clock is selected as the second input clock by the third clock selector.

4. The eMMC timing adjustment method according to claim 1, characterized in that: The receiving module includes a command receiving submodule and a data receiving submodule, and the controlling the sending module sends a preset command to the eMMC device. When the receiving module receives the transmission command and the transmission data returned by the eMMC device, the controlling the comparing module determines whether the transmission command and the transmission data meet a preset condition, including: When the master sends a start clock adjustment command to the logic control module, the logic control module controls the sending module to send a preset command to the eMMC device, the logic control module controls the command receiving submodule to receive the transmission command returned by the eMMC device, and the logic control module controls the data receiving submodule to receive the transmission data returned by the eMMC device; The logic control module controls the comparison module to determine whether the transmission command and the transmission data conform to a preset template; When the transmission command and the transmission data conform to the preset template, it is determined that the transmission command and the transmission data satisfy the preset condition.

5. The eMMC timing adjustment method according to claim 1, characterized in that: The preset command is the CMD21 command.

6. The eMMC timing adjustment method according to claim 1, characterized in that: The controlling logic control module traverses the first phase-shifted clock and the second phase-shifted clock to obtain a plurality of correct phase-shifted clocks, and uses an optimal phase-shifted clock algorithm to determine an optimal phase-shifted clock from each of the correct phase-shifted clocks, including: Projecting the first phase-shifted clock and the second phase-shifted clock onto a two-dimensional plane; Control the logic control module to determine a plurality of correct phase-offset clocks among the first phase-offset clock and the second phase-offset clock on the two-dimensional plane, and search for a plurality of candidate phase-offset clocks that meet preset conditions among the correct phase-offset clocks; The logic control module is controlled to determine the first phase-shifted clock and the second phase-shifted clock corresponding to the candidate phase-shifted clock closest to the center position of the two-dimensional plane as the optimal phase-shifted clock.

7. The eMMC timing adjustment method according to claim 6, characterized in that: The searching for a plurality of candidate phase-offset clocks that meet preset conditions among the correct phase-offset clocks comprises: Determine whether the two-dimensional plane includes an area where four adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes an area where four adjacent clocks are all the correct phase-shifted clocks, determine the area where the four adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock; If the two-dimensional plane does not include a region where four adjacent clocks are all the correct phase-shifted clocks, determine whether the two-dimensional plane includes a region where three adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes a region where three adjacent clocks are all the correct phase-shifted clocks, determine the region where the three adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock; If the two-dimensional plane does not include an area where three adjacent clocks are all the correct phase-shifted clocks, then determining whether the two-dimensional plane includes an area where two adjacent clocks are all the correct phase-shifted clocks; if the two-dimensional plane includes an area where two adjacent clocks are all the correct phase-shifted clocks, determining the area where the two adjacent clocks are all the correct phase-shifted clocks as the candidate phase-shifted clock; If the two-dimensional plane does not include two adjacent areas where both are the correct phase-shifted clocks, it is determined whether the two-dimensional plane includes an area where the intersection position is the correct phase-shifted clock; if the two-dimensional plane includes an area where the intersection position is the correct phase-shifted clock, the area where the intersection position is the correct phase-shifted clock is determined as the candidate phase-shifted clock.

8. An eMMC timing adjustment system, characterized in that: The eMMC timing adjustment system includes a timing adjustment device, an eMMC device and a main control, the main control includes a first delay module, a second delay module, a first clock selector and a second clock selector, and the timing adjustment device includes a logic control module, a sending module, a receiving module and a comparison module; The master control is used to obtain a first input clock, divide the first input clock to obtain a target operating frequency, input the target operating frequency into the first delay module to obtain a plurality of first initial phase offset clocks, obtain a second input clock, input the second input clock into the second delay module to obtain a plurality of second initial phase offset clocks; The master control is further configured to input a plurality of the first initial phase-shifted clocks into the first clock selector to obtain a first phase-shifted clock, and input a plurality of the second initial phase-shifted clocks into the second clock selector to obtain a second phase-shifted clock; The timing adjustment device is used to control the sending module to send a preset command to the eMMC device, control the receiving module to receive the transmission command and transmission data returned by the eMMC device, and control the comparison module to determine whether the transmission command and the transmission data meet a preset condition; The timing adjustment device is further used for traversing the first phase-shifted clock and the second phase-shifted clock to obtain a plurality of correct phase-shifted clocks when the transmission command and the transmission data meet the preset condition, and determining the best phase-shifted clock from each of the correct phase-shifted clocks by using the best phase-shifted clock algorithm; The timing adjustment device is also used to receive a preset command sent by the master control, and return the transmission command and the transmission data.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the eMMC timing adjustment method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the eMMC timing adjustment method according to any one of claims 1 to 7 are implemented.

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