Duty Cycle Adjustment Circuit and Random Access Memory

Abstract

The present application discloses a duty cycle adjustment circuit and a random access memory. The duty cycle adjustment circuit includes a duty cycle adjustment link, a duty cycle detector, a state machine, and a bias voltage generation module. The duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal. The duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal. The state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal. The bias voltage generation module is respectively coupled to the state machine and the duty cycle adjustment link, and is configured to generate a corresponding bias voltage based on the control code and provide it to the duty cycle adjustment link. In the above manner, the duty cycle adjustment circuit of the present application adjusts the slope of the rising edge or the falling edge of the intermediate clock signal generated by the intermediate node through the bias voltage, so as to more accurately adjust the duty cycle of the output clock signal.

Description

Technical Field

[0001] This application relates to the technical field of duty cycle adjustment, and particularly to a duty cycle adjustment circuit and a random access memory. Background Art

[0002] Double Data Rate (DDR) synchronous dynamic random access memory (SDRAM) is the mainstream of random access memory, and it is a typical semiconductor storage device. The DDR type of DRAM is designed to synchronously input or output data on the rising edge and falling edge of the clock signal. Therefore, the duty cycle of the clock signal needs to be accurately maintained at 50%. For this purpose, a duty cycle adjustment circuit is usually used in the chip to adjust the duty cycle of the clock signal. However, in the duty cycle adjustment circuit in the prior art, the duty cycle adjustment range is limited, and the duty cycle adjustment range is determined by the minimum charging and discharging currents of a single transistor; if the charging and discharging currents are too small, the duty cycle of the clock signal cannot be accurately adjusted; and when the duty cycle adjustment circuit in the prior art adjusts the duty cycle, the number of transistors coupled in the clock signal path is large, the parasitics are large, and there are certain requirements for the driving ability of the previous-stage circuit. Summary of the Invention

[0003] In order to solve the above problems, this application provides a duty cycle adjustment circuit and a random access memory, which can accurately adjust the duty cycle of the clock signal, and do not need to configure a large number of transistors, and the parasitic capacitance is small.

[0004] To solve the above technical problems, a technical solution adopted in this application is: to provide a duty cycle adjustment circuit, which includes a duty cycle adjustment link, a duty cycle detector, a state machine, and a bias voltage generation module. The duty cycle adjustment link receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; the duty cycle detector is coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; the state machine is coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; the bias voltage generation module is respectively coupled to the state machine and the duty cycle adjustment link, and is used to generate a corresponding bias voltage based on the control code and provide it to the duty cycle adjustment link. Among them, the duty cycle adjustment link adjusts the pull-down current of the intermediate node in the duty cycle adjustment link through the bias voltage, adjusts the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, and thus adjusts the duty cycle of the output clock signal.

[0005] Among them, the bias voltage generation module includes a first bias voltage generation module and a second bias voltage generation module. The first bias voltage generation module is used to generate a first bias voltage, and the duty cycle adjustment link narrows the duty cycle of the output clock signal based on the first bias voltage; the second bias voltage generation module is used to generate a second bias voltage, and the duty cycle adjustment link increases the duty cycle of the output clock signal based on the second bias voltage.

[0006] Among them, the first bias voltage generation module and the second bias voltage generation module respectively include a bias current generation module and a bias voltage generation module. The bias current generation module includes a plurality of parallel bias current branches, and adjusts and controls the conduction number of the bias current branches based on a control code to generate a corresponding bias current; the bias voltage generation module is coupled to the bias current generation module to generate and output a bias voltage based on the bias current.

[0007] Each bias current branch in the bias current generation module respectively includes: a first transistor and a switch. The control end of the first transistor receives a reference voltage, and the first path end of the first transistor receives a first operating voltage; the first end of the switch is coupled to the second path end of the first transistor, the second end of the switch is coupled to the bias current output module, and the control end of the switch is used to receive the control code to determine whether the corresponding bias current branch is conducting based on the control of the control code.

[0008] The bias voltage generation module includes a second transistor and a capacitor. The first path end of the second transistor receives the bias current and is coupled to the control end of the second transistor; the control end of the second transistor outputs the bias voltage; the first end of the capacitor is grounded, and the second end of the capacitor is coupled to the control end of the second transistor.

[0009] The size ratios of the multiple first transistors included in the bias current branch are successively 1, 2, 4, 8... 2^N, where N is the number of bias current branches, so that the accuracy of the bias current adjusted based on the control code is continuous within the range of 0 to (2^N - 1)*I0, where I0 is the bias current provided by connecting a first transistor of unit size.

[0010] Among them, the duty cycle adjustment link includes an input module, an output module, a first adjustment link, and a second adjustment link. The input module receives an initial clock signal and processes it to generate a first processed input clock signal; the output module is used to output an output clock signal; the first adjustment link is coupled to the input module to perform a first adjustment operation and a buffered inversion operation on the first input clock signal to output a first clock signal; the second adjustment link is coupled to the first adjustment link to perform a second adjustment operation and a buffered inversion operation on the second processed input clock signal to output a second clock signal, where the first processed input clock signal, the first clock signal, the second processed input clock signal, and the second clock signal are respectively used as intermediate clock signals of the duty cycle adjustment link; among them, in response to the first adjustment link performing the first adjustment operation, the first adjustment link adjusts the slope of the rising edge or the falling edge of the intermediate clock signal to narrow or increase the duty cycle of the output clock signal; in response to the second adjustment link performing the second adjustment operation, the second adjustment link adjusts the slope of the rising edge or the falling edge of the intermediate clock signal to increase or narrow the duty cycle of the output clock signal.

[0011] Among them, the duty cycle adjustment link further includes a buffer module, and the buffer module is coupled between the first adjustment link and the second adjustment link to buffer the first clock signal output by the first adjustment link to generate a second processed input clock signal.

[0012] Among them, the input module includes a first buffer unit, the first buffer unit is composed of an even number of inverters, and receives the initial clock signal to perform a buffer operation, thereby generating a processed input clock signal, where the processed input clock signal is in phase with the initial clock signal; or the input module includes a first buffer inversion unit, the first buffer inversion unit is composed of an odd number of inverters, and receives the initial clock signal to perform a buffer inversion operation, thereby generating a processed input clock signal, where the processed input clock signal is out of phase with the initial clock signal.

[0013] Among them, the output module includes a second buffer unit, the second buffer unit is composed of an even number of inverters, receives the second clock signal output by the second adjustment link, and performs a buffer operation, thereby generating an output clock signal; or the output module includes a second buffer inversion unit, the second buffer inversion unit is composed of an odd number of inverters, receives the second clock signal output by the second adjustment link, and performs a buffer inversion operation, thereby generating an output clock signal; among them, in response to the input module including the first buffer unit, the output module includes the second buffer unit; in response to the input module including the first buffer inversion unit, the output module includes the second buffer inversion unit.

[0014] Among them, the first adjustment link or the second adjustment link respectively includes an inverter and a discharge branch. The inverter unit is arranged on the main path of the duty cycle adjustment link to perform a buffer inversion operation. The discharge branch is coupled to the inverter unit and receives a first bias voltage or a second bias voltage to perform a discharge operation on the intermediate clock signal based on the first bias voltage or the second bias voltage, so as to adjust the slope of the rising edge or the falling edge of the intermediate clock signal. Among them, in response to the first adjustment link performing a first adjustment operation, the slope of the rising edge or the falling edge of the intermediate clock signal is adjusted by the discharge branch in the first adjustment link, and the buffer inversion operations are respectively performed by the inverter units in the first adjustment link and the second adjustment link. In response to the second adjustment link performing a second adjustment operation, the slope of the rising edge or the falling edge of the intermediate clock signal is adjusted by the discharge branch in the second adjustment link, and the buffer inversion operations are respectively performed by the inverter units in the first adjustment link and the second adjustment link.

[0015] Among them, the input module includes a first buffer unit, the output module includes a second buffer unit. The first adjustment link receives a first bias voltage to perform a first adjustment operation for narrowing the duty cycle of the output clock signal, and the second adjustment link receives a second bias voltage to perform a second adjustment operation for increasing the duty cycle of the output clock signal. Or the input module includes a first buffer inverter unit, the output module includes a second buffer inverter unit. The first adjustment link receives a second bias voltage to perform a first adjustment operation for increasing the duty cycle of the output clock signal, and the second adjustment link receives a first bias voltage to perform a second adjustment operation for narrowing the duty cycle of the output clock signal.

[0016] Among them, the discharge branch includes a third transistor and a fourth transistor. The control end of the third transistor receives the first bias voltage or the second bias voltage. The first path end of the third transistor is coupled to the input end of the inverter unit. The control end of the fourth transistor is coupled to the output end of the inverter. The first path end of the fourth transistor is coupled to the second path end of the third transistor. The second path end of the fourth transistor is grounded. Among them, when the control end of the third transistor receives the first bias voltage or the second bias voltage, the third transistor and the fourth transistor are turned on, and a pull-down current corresponding to the first bias voltage or the second bias voltage is generated between the third transistor and the fourth transistor to perform a discharge operation on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

[0017] Among them, the inverting unit includes a fifth transistor, a sixth transistor, and a seventh transistor. The control end of the fifth transistor is coupled to the input module, and the first path end of the fifth transistor receives a second operating voltage. The control end of the sixth transistor is coupled to the input module, and the first path end of the sixth transistor is coupled to the second path end of the fifth transistor. Among them, the node between the first path end of the sixth transistor and the second path end of the fifth transistor serves as the output end of the inverting unit. The control end of the seventh transistor is coupled to the input module, and the first path end of the seventh transistor is coupled to the second path end of the sixth transistor. The second path end of the seventh transistor is grounded. The discharge branch includes an eighth transistor. The control end of the eighth transistor receives a first bias voltage or a second bias voltage. The first path end of the eighth transistor is coupled to the second path end of the sixth transistor. The second path end of the eighth transistor is grounded. Among them, when the control end of the eighth transistor receives the first bias voltage or the second bias voltage, the eighth transistor is turned on, and the eighth transistor generates a corresponding pull-down current based on the first bias voltage or the second bias voltage to perform a discharge operation on the intermediate clock signal, so as to adjust the slope of the falling edge of the intermediate clock signal.

[0018] To solve the above technical problems, another technical solution adopted by this application is: to provide a random access memory, which includes the duty cycle adjustment circuit of any one of the above.

[0019] Different from the prior art, the duty cycle adjustment circuit of this application can provide the detection signal generated by the duty cycle detector to the state machine to generate a control code, and then generate a bias voltage acting on the duty cycle adjustment link through the control code. Through the bias voltage, the pull-down current of the intermediate node in the duty cycle adjustment link can be adjusted, and then the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node can be adjusted, so as to adjust the duty cycle of the output clock signal. Compared with the prior art, the duty cycle adjustment range of the clock signal of the duty cycle adjustment circuit of this application is wider, and its adjustment accuracy is more precise when adjusting the duty cycle by voltage. Moreover, the duty cycle adjustment circuit of this application requires fewer transistors, has a small parasitic capacitance, and has a small driving ability requirement for the previous-stage circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of this application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. Among them:

[0021] Figure 1 is a schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by this application;

[0022] Figure 2It is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by this application;

[0023] Figure 3 It is a schematic structural diagram of an embodiment of the first bias voltage generation module of this application;

[0024] Figure 4 It is a schematic structural diagram of the first embodiment of the duty cycle adjustment link provided by this application;

[0025] Figure 5 It is a schematic structural diagram of the second embodiment of the duty cycle adjustment link provided by this application;

[0026] Figure 6 It is a schematic circuit structural diagram of the first embodiment of the duty cycle adjustment link provided by this application;

[0027] Figure 7 It is a waveform schematic diagram of the input processing clock signal and the first clock signal adjustment process;

[0028] Figure 8 It is a schematic circuit structural diagram of the second embodiment of the duty cycle adjustment link provided by this application;

[0029] Figure 9 It is a schematic circuit structural diagram of the third embodiment of the duty cycle adjustment link provided by this application;

[0030] Figure 10 It is a schematic circuit structural diagram of the fourth embodiment of the duty cycle adjustment link provided by this application;

[0031] Figure 11 It is a schematic structural diagram of an embodiment of the random access memory of this application. Specific embodiments <> <>

[0032] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. It can be understood that the specific embodiments described herein are only used to explain this application, rather than limiting this application. Additionally, it should be noted that for the sake of convenience of description, only parts related to this application rather than all structures are shown in the accompanying drawings. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

[0033] Referring to "embodiment" herein means that the specific features, structures, or characteristics described in conjunction with the embodiment may be included in at least one embodiment of this application. The phrase appears in various positions in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0034] In the design of current random access memories, double data rate (DDR) synchronous dynamic random access memories (SDRAMs) are the mainstream of random access memories, and they are typical semiconductor storage devices. DDR-type DRAMs are designed to synchronously input or output data at both the rising and falling edges of a clock signal. Therefore, the duty cycle of the clock signal needs to be precisely maintained at 50%. For this purpose, a chip usually adopts a duty cycle adjustment circuit to adjust the duty cycle of the clock signal. However, in the duty cycle adjustment circuits in the prior art, the duty cycle adjustment range is limited, and the duty cycle adjustment range is determined by the minimum charging and discharging currents of a single transistor; if the charging and discharging currents are too small, the duty cycle of the clock signal cannot be precisely adjusted; moreover, when the duty cycle adjustment circuit in the prior art adjusts the duty cycle, the number of transistors coupled in the path of the clock signal is large, the parasitics are large, and there are certain requirements for the driving ability of the previous-stage circuit.

[0035] To solve the above problems, this application first proposes a duty cycle adjustment circuit. Please refer to Figure 1 , Figure 1 which is a schematic diagram of the first embodiment of the duty cycle adjustment circuit provided by this application. As Figure 1 shown, the duty cycle adjustment circuit 100 of this embodiment includes a duty cycle adjustment link 10, a duty cycle detector 20, a state machine 30, and a bias voltage generation module 40.

[0036] As Figure 1 shown, the duty cycle adjustment link 10 receives an initial clock signal CLKIN and adjusts the initial clock signal CLKIN to generate an output clock signal CLKOUT; the duty cycle detector 20 is coupled to the duty cycle adjustment link 10 to generate a corresponding detection signal based on the detected duty cycle of the output clock signal CLKOUT; the state machine 30 is coupled to the duty cycle detector 20 to generate a corresponding control code Code based on the detection signal. <n:1>; The bias voltage generation module 40 is respectively coupled to the state machine 30 and the duty cycle adjustment link 10, and is used to be based on the control code Code <n:1>Generate a corresponding bias voltage and provide it to the duty cycle adjustment link 10. Among them, the duty cycle adjustment link 10 adjusts the pull-down current of the intermediate node in the duty cycle adjustment link 10 through the bias voltage, and adjusts the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, so as to adjust the duty cycle of the output clock signal CLKOUT.

[0037] In this embodiment, the duty cycle adjustment link 10 adjusts the duty cycle of the clock signal CLKIN, and its specific circuit structure of the duty cycle adjustment link 10 is shown below. The duty cycle detector 20 detects the duty cycle of the output clock signal CLKOUT, and a detection signal will be obtained. In this embodiment, the detection signal is a level signal. The detection signal output as a logic level "1" indicates that the duty cycle is greater than 50%, and the output logic level "0" indicates that the duty cycle is less than 50%.

[0038] When the state machine 30 receives the detection signal of the duty cycle detector 20, it will generate a corresponding control code Code <n:1>, the bias voltage generation module 40 receives the corresponding control code Code <n:1>Generate a corresponding bias voltage to act on the duty cycle adjustment link 10 to adjust the pull-down current of the intermediate node in the duty cycle adjustment link 10, thereby adjusting the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, and further adjusting the duty cycle of the output clock signal CLKOUT.

[0039] Different from the prior art, the duty cycle adjustment circuit 100 of the present application can provide the detection signal generated by the duty cycle detector 20 to the state machine 30 to generate a control code, and then generate a bias voltage acting on the duty cycle adjustment link 10 through the control code. The pull-down current of the intermediate node in the duty cycle adjustment link 10 can be adjusted through the bias voltage, and then the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node can be adjusted, so as to adjust the duty cycle of the output clock signal. Compared with the prior art, the duty cycle adjustment range of the clock signal of the duty cycle adjustment circuit 100 of the present application is wider, and its adjustment accuracy is more precise when adjusting the duty cycle by voltage. Moreover, the duty cycle adjustment circuit 100 of the present application does not require many transistors, has a small parasitic capacitance, and has a small driving ability requirement for the previous-stage circuit.

[0040] Optionally, based on the above embodiment, please refer to Figure 2 , Figure 2 is a schematic diagram of the second embodiment of the duty cycle adjustment circuit provided by the present application. As Figure 2 shown, the bias voltage generation module 40 includes a first bias voltage generation module 41 and a second bias voltage generation module 42.

[0041] The first bias voltage generation module 41 is used to generate a first bias voltage, and the duty cycle adjustment link 10 narrows the duty cycle of the output clock signal based on the first bias voltage; the second bias voltage generation module 42 is used to generate a second bias voltage, and the duty cycle adjustment link 10 increases the duty cycle of the output clock signal based on the second bias voltage.

[0042] Among them, the first bias voltage and the second bias voltage generated by the first bias voltage generation module 41 and the second bias voltage generation module 42 have opposite effects in this embodiment.

[0043] Optionally, please refer to Figure 3 , Figure 3 is a schematic diagram of the structure of an embodiment of the first bias voltage generation module of the present application. As Figure 3 shown, the first bias voltage generation module 41 of this embodiment respectively includes a bias current generation module 411 and a bias voltage generation module 412.

[0044] The bias current generation module 411 includes a plurality of parallel bias current branches, and adjusts and controls the number of turned-on bias current branches based on a control code, so as to generate a corresponding bias current; the bias voltage generation module 412 is coupled to the bias current generation module 411 to generate and output a bias voltage based on the bias current.

[0045] As Figure 3 shown, each bias current branch in the bias current generation module 411 respectively includes: a first transistor MPn (n = 1, 2,..., N) and a switch Tn (n = 1, 2,..., N), the control end of the first transistor MPn receives a reference voltage Vref, and the first path end of the first transistor MPn receives a first operating voltage VCC; the first end of the switch Tn is coupled to the second path end of the first transistor MPn, the second end of the switch Tn is coupled to the bias voltage generation module 412, and the control end of the switch Tn is used to receive a control code Code <n:1>, based on the control code Code <n:1>is determined by the control to determine whether the corresponding bias current branch is turned on.

[0046] In this embodiment, the sizes of the multiple first transistors MPn included in the bias current branch are in the ratio of 1, 2, 4, 8... 2^(N-1) in sequence, where N is the number of bias current branches, so that the accuracy of the bias current adjusted based on the control code is continuous within the range of 0 to (2^N-1)*I0, where I0 is the bias current provided by the first transistor MPn with unit size connected. The "first transistor MPn with unit size" is, for example, Figure 3 MP1 in

[0047] For example, as Figure 3 shown, the size of the first transistor MP1 is the unit size, and the bias current it provides is I0. The size of the first transistor MP2 is 2 * unit size, and the bias current it provides is 2I0. The size of the first transistor MP3 is 4 * unit size, and the bias current it provides is 4I0... and so on. The size of the first transistor MP4 is 8 * unit size, and the bias current it provides is 8I0... and so on. The size of the first transistor MPN is 2^(N-1) * unit size, and the bias current it provides is 2^(N-1) * I0. If the control code Code <n:1>is all 0, then all of the first transistors MP1 to MPN are turned off, and the provided bias current is 0; if the control code Code <n:1>If it is all 1s, all the first transistors MP1 to MPN are turned on, and the provided bias current is the sum of N bias currents, which is (2^N - 1)*I0. That is to say, in this embodiment, by controlling the number of conducting bias current branches, the precision continuity of the bias current in the range of 0, I0, 2I0, 3I0... (2^N - 1)*I0 can be achieved, that is, the precision continuity of the bias voltage is achieved, so that the duty cycle of the clock signal can be accurately adjusted.

[0048] Among them, the bias voltage generation module 412 includes a second transistor 4121 and a capacitor C. The first path end of the second transistor 4121 is respectively coupled to the output end of the bias current generation module 411 and the control end of the second transistor 4121; the second path end of the second transistor 4121 is grounded; wherein, the control end of the second transistor 4121 is used as the output end of the bias voltage generation module 412 to output a bias voltage; the first end of the capacitor C is grounded, and the second end of the capacitor C is coupled to the control end of the second transistor 4121. The capacitor C is used to filter out the glitches in the bias voltage generation module 412.

[0049] In Figure 3 Among them, the size ratios of the first transistors MPn (n = 1, 2,... N) in the bias current branches conform to binary weights. When the control end of the first transistor MPn receives a reference voltage, the first transistor MPn is turned on. At this time, if the control code Code <n:1>When the switch Tn on a branch is controlled to close, a branch current will be generated on this branch based on the reference voltage Vref. In this embodiment, the control code Code can be changed <n:1>Furthermore, the number of turned-on bias current branches in the bias current generation module 411 is controlled, and finally, the bias voltage generation module 412 generates a corresponding bias voltage due to the change in the number of turned-on bias current branches in the bias current generation module 411.

[0050] That is, when the control code Code generated by the state machine 30 <n:1>When it changes, the bias current input to the bias voltage generation module 412 changes, and the finally output bias voltage also changes accordingly. In this embodiment, when the duty cycle adjustment circuit 100 of this embodiment operates, it requires the first bias voltage generation module 41 and the second bias voltage generation module 42. The first bias voltage generation module 41 is used to generate a first bias voltage, and the duty cycle adjustment link 10 narrows the duty cycle of the output clock signal based on the first bias voltage; the second bias voltage generation module 42 is used to generate a second bias voltage, and the duty cycle adjustment link 10 increases the duty cycle of the output clock signal based on the second bias voltage.

[0051] Among them, in this embodiment, the accuracy of the bias voltage adjustment is related to the bias voltage generated by the bias current at which the first transistor MPn with the smallest weight (such as Figure 3 MP1 in) is turned on, and the control code Code <n:1>The variation of the offset voltage caused is the adjustment accuracy of the offset voltage and also the adjustment accuracy of the duty cycle in this embodiment. In this embodiment, the size of the first transistor MPn can be selected according to the preset duty cycle adjustment accuracy.

[0052] Optionally, based on the above embodiment, in this embodiment, please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the first embodiment of the duty cycle adjustment link provided by this application. As Figure 4 shown, the duty cycle adjustment link 10 of this embodiment includes an input module 11, an output module 14, and a first adjustment link 12 and a second adjustment link 13. The input module 11 receives the initial clock signal CLKIN and processes it to generate a first input processed clock signal CLK1; the output module 14 is used to output an output clock signal CLKOUT; the first adjustment link 12 is coupled to the input module 11 to perform a first adjustment operation and a buffer inversion operation on the first input processed clock signal CLK1 to output a first clock signal CLK1b; the second adjustment link 13 is connected to the first adjustment link 12 to perform a second adjustment operation and a buffer inversion operation on the second input processed clock signal CLK2 to output a second clock signal CLK2b, where the first input processed clock signal CLK1, the first clock signal CLK1b, the second input processed clock signal CLK2, and the second clock signal CLK2b respectively serve as the intermediate clock signals of the duty cycle adjustment link 10.

[0053] Among them, in response to the first adjustment link 12 performing the first adjustment operation, the first adjustment link 12 adjusts the slope of the rising edge or the falling edge of the intermediate clock signal to narrow or increase the duty cycle of the output clock signal; in response to the second adjustment link 13 performing the second adjustment operation, the second adjustment link 13 adjusts the slope of the rising edge or the falling edge of the intermediate time signal to increase or narrow the duty cycle of the output clock signal.

[0054] In this embodiment, in order to accurately adjust the initial clock signal CLKIN to a duty cycle of 50%, the duty cycle adjustment link 10 including both the first adjustment link 12 and the second adjustment link 13 can achieve the purpose more quickly.

[0055] In other embodiments, please refer to Figure 5 , Figure 5 which is a schematic structural diagram of the second embodiment of the duty cycle adjustment link provided by this application. As Figure 5 shown, the duty cycle adjustment link 10 of this embodiment further includes a buffer module 15. The buffer module 15 is coupled between the first adjustment link 12 and the second adjustment link 13 to buffer the first clock signal CLK1b output by the first adjustment link 12 to generate a second input processed clock signal CLK2.

[0056] Among them, in this embodiment, the buffer module 15 is composed of an even number of inverters, so that the first clock signal CLK1b is in phase with the second input processing clock signal CLK2 after passing through the buffer module 15. In other embodiments, the buffer module 15 can also be omitted.

[0057] Optionally, based on the above embodiments, please refer to Figure 6 , Figure 6 which is a schematic circuit diagram of the first embodiment of the duty cycle adjustment link provided by this application.

[0058] As Figure 6 shown, in this embodiment, the input module 11 includes a first buffer unit, which is composed of an even number of inverters (inverters), and receives the initial clock signal CLKIN to perform a buffering operation, thereby generating the input first processing clock signal CLK1. Among them, the first input processing clock signal CLK1 is in phase with the initial clock signal CLKIN. In this embodiment, the input module 11 is composed of 2 inverters. In other embodiments, an even number of inverters can also be set based on actual needs, which is not limited here.

[0059] As Figure 6 shown, the output module 14 includes a second buffer unit, which is also composed of an even number of inverters, receives the second clock signal CLK2b output by the second adjustment link 13, and performs a buffering operation, thereby generating the output clock signal CLKOUT. The same as the input module 11, in this embodiment, the output module 14 is also composed of 2 inverters. In other embodiments, an even number of inverters can also be set based on actual needs, which is not limited here. Among them, in response to the input module 11 including the first buffer unit, the output module 14 is the second buffer unit. That is, in this embodiment, the number of inverters in the input module 11 and the output module 14 is even.

[0060] Please refer to Figure 6 , in the first adjustment link 12 of the duty cycle adjustment link 10 in this embodiment, it includes a first inversion unit 121 and a first discharge branch 122.

[0061] In this embodiment, the first inversion unit 121 is arranged on the main path of the duty cycle adjustment link 10 and is coupled to the input module 11 to perform a first buffer inversion operation; the first discharge branch 122 receives a first bias voltage to perform a discharge operation on the intermediate clock signal based on the first bias voltage to adjust the slope of the rising edge of the intermediate clock signal. It should be noted that in Figure 6 and subsequent Figure 8 embodiments, the first input processing clock signal CLK1 and the second input processing clock signal CLK2 are respectively used as the intermediate clock signal of the duty cycle adjustment link 10.

[0062] In this embodiment, the input module 11 is a first buffer unit, and the first buffer unit is composed of an even number of inverters. At this time, the first discharge branch 122 receives a first bias voltage to perform a discharge operation on the first input processing clock signal CLK1 based on the first bias voltage, thereby adjusting the slope of the rising edge of the first input processing clock signal CLK1.

[0063] Specifically, the working principle of the first adjustment link 12 for adjusting the slope of the rising edge of the first input processing clock signal CLK1 is as follows.

[0064] Please refer to Figure 6 , the first discharge branch 122 includes a third transistor 1221 and a fourth transistor 1222. The control terminal of the third transistor 1221 receives the first bias voltage. The first path terminal of the third transistor 1221 is coupled to the input terminal of the first inverter unit 121. The control terminal of the fourth transistor 1222 is coupled to the output terminal of the first inverter unit 121. The first path terminal of the fourth transistor 1222 is coupled to the second path terminal of the third transistor 1221. The second path terminal of the fourth transistor 1222 is grounded; wherein, when the control terminal of the third transistor 1221 receives the first bias voltage, the third transistor 1221 and the fourth transistor 1222 are turned on, and a pull-down current I1 corresponding to the first bias voltage is generated between the third transistor 1221 and the fourth transistor 1222 to perform a discharge operation on the first input processing clock signal CLK1, so as to adjust the slope of the rising edge of the first input processing clock signal CLK1, thereby narrowing the duty cycle of the output clock signal CLKOUT.

[0065] In an application scenario, when the duty cycle of the output clock signal CLKOUT is greater than 50%, the duty cycle detector 20 inputs a detection signal "1" to the state machine 30, and the state machine 30 generates a control code Code based on the detection signal "1" <n:1>, the first adjustment link 12 receives the first bias voltage generated by the first bias voltage generation module 41 to perform a discharging operation on the first input processing clock signal CLK1, so as to adjust the slope of the rising edge of the first input processing clock signal CLK1, thereby narrowing the duty cycle of the output clock signal CLKOUT.

[0066] Please refer to Figure 7 , Figure 7 is a waveform schematic diagram of the input processing clock signal and the first clock signal adjustment process. As Figure 7 shown, when the first input processing clock signal CLK1 is at the rising edge, at this time the first clock signal CLK1B still stays at the high level, and at this time the fourth transistor 1222 is in the conducting state. As the voltage of the first input processing clock signal CLK1 node increases, the third transistor 1221 and the fourth transistor 1222 generate a pull-down current I1, making the rising speed of the first input processing clock signal CLK1 node slower; when the first input processing clock signal CLK1 node rises to the inversion point of the first inverter unit 121, the first clock signal CLK1B node starts to change from high to low; when the first clock signal CLK1B node drops below the control terminal threshold voltage of the fourth transistor 1222, the fourth transistor 1222 is turned off, and I1 gradually decreases to 0; when I1 = 0, the first input processing clock signal CLK1 node continues to be driven by the previous-stage input module 11, and its voltage is quickly pulled up to the power supply voltage. After being shaped by the inverter in the subsequent link, the duty cycle of the finally output clock signal CLKOUT is narrowed. It can be seen that during the adjustment process, the higher the first bias voltage, the larger the pull-down current I1, the slower the rising speed of the first input processing clock signal CLK1 node, and the more the duty cycle of the output clock signal CLKOUT is narrowed.

[0067] In this embodiment, the second adjustment link 13 includes a second inverter unit 131 and a second discharging branch 132. The structure of the second adjustment link 13 is the same as that of the first adjustment link 12.

[0068] Among them, the second adjustment link 13 is coupled to the first adjustment link 12. If the first adjustment link 12 responds to the duty cycle of the output clock signal CLKOUT being greater than 50% to work to narrow the duty cycle of the output clock signal CLKOUT, then the second adjustment link 13 only performs a second buffered inversion operation on the second input processing clock signal CLK2 to output the second clock signal CLK2b, that is, the second discharging branch 132 does not work. When the duty cycle of the output clock signal CLKOUT is less than 50%, the duty cycle detector 20 inputs a detection signal "0" to the state machine 30, and the state machine 30 generates a control code Code based on the detection signal "0" <n:1>, the second adjustment link 13 receives the second bias voltage generated by the second bias voltage generation module 42 to perform a discharging operation on the second input processing clock signal CLK2. Specifically, the second discharging branch 132 receives the second bias voltage to perform a discharging operation on the second input processing clock signal CLK2 based on the second bias voltage, so as to adjust the slope of the rising edge of the second input processing clock signal CLK2.

[0069] The circuit structure of the second discharging branch 132 of the second adjustment link 13 is the same as that of the first discharging branch 122 in terms of structure and working principle, which will not be elaborated here. Since the intermediate clock signal received by the second adjustment link 13 is the second input processing clock signal CLK2, and the second input processing clock signal CLK2 is inverted with respect to the initial clock signal CLKIN. That is, the second adjustment link 13 performs a discharging operation on the second input processing clock signal CLK2 based on the second bias voltage, thereby adjusting the slope of the rising edge of the second input processing clock signal CLK2. Since the second input processing clock signal CLK2 is inverted with respect to the initial clock signal CLKIN, that is, the second adjustment link 13 realizes the function of adjusting the initial clock signal CLKIN to increase the duty cycle. During the adjustment process of the second adjustment link 13, the higher the second bias voltage, the larger the pull-down current I2, the slower the rising speed of the second input processing clock signal CLK2, and the more the duty cycle of the output clock signal CLKOUT is increased.

[0070] In Figure 6 the embodiment, in response to the first adjustment link 12 performing the first adjustment operation, the slope of the rising edge of the first input processing clock signal CLK1 is adjusted by the first discharging branch 122 in the first adjustment link 12, and buffer inversion operations are respectively performed by the first inversion unit 121 in the first adjustment link 12 and the second inversion unit 131 in the second adjustment link 13.

[0071] In response to the second adjustment link 13 performing the second adjustment operation, the slope of the rising edge of the second input processing clock signal CLK2 is adjusted by the second discharging branch 132 in the second adjustment link 13, and buffer inversion operations are respectively performed by the first inversion unit 121 in the first adjustment link 12 and the second inversion unit 131 in the second adjustment link 13.

[0072] Since in Figure 6 the embodiment, the input module 11 is the first buffer unit and the output module 14 is the second buffer unit, therefore, the first adjustment link 12 receives the first bias voltage to perform the first adjustment operation for narrowing the duty cycle of the output clock signal, and the second adjustment link 13 receives the second bias voltage to perform the second adjustment operation for increasing the duty cycle of the output clock signal.

[0073] Optionally, please refer to Figure 8 , Figure 8 It is a schematic circuit diagram of the second embodiment of the duty cycle adjustment link provided by this application.

[0074] As Figure 8 shown, in this embodiment, the input module 11 includes a first buffer inverter unit, which is composed of an odd number of inverters (inverters), and receives the initial clock signal CLKIN to perform a buffer inversion operation, thereby generating a first input processed clock signal CLK1. At this time, the first input processed clock signal CLK1 is inverted with respect to the initial clock signal CLKIN. In this embodiment, the input module 11 is composed of 1 inverter. In other embodiments, an odd number of inverters can also be set based on actual needs, which is not limited here.

[0075] As Figure 8 shown, the output module 14 includes a second buffer inverter unit, which is also composed of an odd number of inverters, receives the second clock signal CLK2b output by the second adjustment link 13, and performs a buffer inversion operation, thereby generating an output clock signal CLKOUT. In this embodiment, the output module 14 is composed of 3 inverters. In other embodiments, an odd number of inverters can also be set based on actual needs, which is not limited here. Among them, the input module 11 includes a first buffer inverter unit, and the output module 14 is a second buffer inverter unit. That is, in this embodiment, the number of inverters in both the input module 11 and the output module 14 is odd.

[0076] In Figure 8 the embodiment of Figure 8 the structure and working principle of the first adjustment link 12 and the second adjustment link 13 in the embodiment are as described above, and will not be elaborated here. Since Figure 8 in the embodiment of

[0077] the input module 11 is a first buffer inverter unit and the output module 14 is a second buffer inverter unit.

[0078] Optionally, this application further proposes a duty cycle adjustment link. Please refer to Figure 9 , Figure 9 which is a schematic circuit diagram of the third embodiment of the duty cycle adjustment link provided by this application.

[0079] As Figure 9 shown, the structures and working principles of the input module 11, the output module 14, and the buffer module 15 in this embodiment are all the same as those in Figure 6 and Figure 8 In the embodiments, the structures and working principles of the input module 11, the output module 14, and the buffer module 15 are similar.

[0080] As Figure 9 shown, the input module 11 includes a first buffer inverter unit. The first buffer unit is composed of an odd number of inverters and receives the initial clock signal CLKIN to perform a first buffer inversion operation, thereby generating a first input processing clock signal CLK1. Among them, the first input processing clock signal CLK1 is inverted with respect to the initial clock signal CLKIN. In this embodiment, the input module 11 is composed of 1 inverter. In other embodiments, an odd number of inverters can also be set according to actual needs, which is not limited here. The output module 14 includes a second buffer inverter unit. The second buffer inverter unit is also composed of an odd number of inverters, receives the second clock signal CLK2b output by the second adjustment link 13, and performs a second buffer inversion operation, thereby generating an output clock signal CLKOUT. In this embodiment, the output module 14 is composed of 3 inverters. In other embodiments, an odd number of inverters can also be set according to actual needs, which is not limited here. Among them, since the input module 11 includes a first buffer inverter unit, the output module 14 is a second buffer inverter unit. That is, in this embodiment, the number of inverters in both the input module 11 and the output module 14 is odd.

[0081] In Figure 9 the embodiment, because Figure 9 in the embodiment, the input module 11 is a first buffer inverter unit and the output module 14 is a second buffer inverter unit. Therefore, Figure 9 in it, the first adjustment link 12 receives a second bias voltage to perform a first adjustment operation to increase the duty cycle of the output clock signal, and the second adjustment link 13 receives a first bias voltage to perform a second adjustment operation to narrow the duty cycle of the output clock signal.

[0082] In Figure 9 it, different from the above embodiment is the circuit structure and working principle of the first adjustment link 12 and the second adjustment link 13.

[0083] As Figure 9 shown, in the first adjustment link 12 of the duty cycle adjustment link 10 in this embodiment includes a first inverter unit 121 and a first discharge branch 122.

[0084] In this embodiment, the first inverter unit 121 is arranged on the main path of the duty cycle adjustment link 10 and is coupled to the input module 11 to perform a first buffer inversion operation; the first discharge branch 122 receives the second bias voltage to perform a discharge operation on the first clock signal CLK1b based on the second bias voltage to adjust the slope of the falling edge of the first clock signal CLK1b. It should be noted that in Figure 9 and subsequently Figure 10 In the embodiment, the first clock signal CLK1b and the second clock signal CLK2b serve as the intermediate clock signals of the duty cycle adjustment link 10, respectively.

[0085] Specifically, the working principle of the first adjustment link 12 for adjusting the slope of the falling edge of the first clock signal CLK1b is described as follows.

[0086] Please refer to Figure 9 , the first inverter unit 121 includes a fifth transistor 1211, a sixth transistor 1212, and a seventh transistor 1213. The control end of the fifth transistor 1211 is coupled to the input module 11 or. The first path end of the fifth transistor 1211 receives the second operating voltage. The control end of the sixth transistor 1212 is coupled to the input module 11. The first path end of the sixth transistor 1212 is coupled to the second path end of the fifth transistor 1211. Wherein, the node between the first path end of the sixth transistor 1212 and the second path end of the fifth transistor 1211 serves as the output end of the first inverter unit 121. The output end of the first inverter unit 121 is coupled to the second adjustment link 13. The control end of the seventh transistor 1213 is coupled to the input module 11. The first path end of the seventh transistor 1213 is coupled to the second path end of the sixth transistor 1212. The second path end of the seventh transistor 1213 is grounded. The first discharge branch 122 includes an eighth transistor 1223. The control end of the eighth transistor 1223 receives the second bias voltage. The first path end of the eighth transistor 1223 is coupled to the second path end of the sixth transistor 1212. The second path end of the eighth transistor 1223 is grounded. Wherein, when the control end of the eighth transistor 1223 receives the second bias voltage, the eighth transistor 1223 is turned on. The eighth transistor 1223 generates a corresponding pull-down current I1 based on the second bias voltage to perform a discharge operation on the first clock signal CLK1b to adjust the first clock signal CLK1b.

[0087] In an application scenario, in Figure 9 the first adjustment link 12 of the embodiment, when the first adjustment link 12 does not perform duty cycle adjustment on the initial clock signal CLKIN, the control code Code<n:1> output by the state machine 30 can be set to make the generated second bias voltage reach the highest value. At this time, the on-resistance of the eighth transistor 1223 is very small, and the fifth transistor 1211, the sixth transistor 1212, and the seventh transistor 1213 are equivalent to an inverter.

[0088] When the first adjustment link 12 performs duty cycle adjustment on the initial clock signal CLKIN, the state machine 30 changes the control code Code<n:1> to make the generated second bias voltage change, adjusts the slope of the first clock signal CLK1b, and thus adjusts the initial clock signal CLKIN.

[0089] In Figure 9 the embodiment, the second adjustment link 13 includes a second inverting unit 131 and a second discharge branch 132. The structure of the second adjustment link 13 is the same as that of the first adjustment link 12.

[0090] Among them, the second adjustment link 13 is coupled to the first adjustment link 12. If the first adjustment link 12 operates in response to the duty cycle of the output clock signal CLKOUT being less than 50% to increase the duty cycle of the output clock signal CLKOUT, the second adjustment link 13 only performs a second buffered inverting operation on the second input processing clock signal CLK2 to output the second clock signal CLK2b, that is, the second discharge branch 132 does not work. When the duty cycle of the output clock signal CLKOUT is greater than 50%, the duty cycle detector 20 inputs a detection signal "1" to the state machine 30, and the state machine 30 generates a control code Code based on the detection signal "1" <n:1>, the second adjustment link 13 receives the first bias voltage generated by the first bias voltage generation module 41 to perform a discharging operation on the second clock signal CLK2b. Specifically, the second discharging branch 132 receives the first bias voltage to perform a discharging operation on the second clock signal CLK2b based on the first bias voltage, so as to adjust the slope of the falling edge of the second clock signal CLK2b.

[0091] The circuit structure of the second discharging branch 132 of the second adjustment link 13 is the same as that of the first discharging branch 122 in terms of structure and working principle, which will not be elaborated here. Since the intermediate clock signal received by the second adjustment link 13 is the second input processing clock signal CLK2, Figure 9 in the embodiment, the second input processing clock signal CLK2 is in phase with the initial clock signal CLKIN, and the second clock signal CLK2b is out of phase with the initial clock signal CLKIN. The second adjustment link 13 performs a discharging operation on the second clock signal CLK2b based on the first bias voltage, so as to adjust the slope of the rising edge of the second clock signal CLK2b. Since the second clock signal CLK2b is out of phase with the initial clock signal CLKIN, that is, the second adjustment link 13 realizes the function of adjusting the initial clock signal CLKIN to narrow the duty cycle.

[0092] In Figure 9 the embodiment, in response to the first adjustment link 12 performing the first adjustment operation, the slope of the falling edge of the first clock signal CLK1b is adjusted by the first discharging branch 122 in the first adjustment link 12, and buffer inversion operations are respectively performed by the first inversion unit 121 in the first adjustment link 12 and the second inversion unit 131 in the second adjustment link 13.

[0093] In response to the second adjustment link 13 performing the second adjustment operation, the slope of the falling edge of the second clock signal CLK2b is adjusted by the second discharging branch 132 in the second adjustment link 13, and inversion operations are respectively performed by the first inversion unit 121 in the first adjustment link 12 and the second inversion unit 131 in the second adjustment link 13.

[0094] In Figure 9 the embodiment, the input module 11 is the first buffer inversion unit, and the output module 14 is the second buffer inversion unit. Therefore, Figure 9 in

[0095] Please refer to Figure ...... , ​ which ​ In the embodiment of ​ In the embodiment, the structures and working principles of the first adjustment link 12 and the second adjustment link 13 are as described in the above ​ embodiment and will not be elaborated here. Since ​ in the embodiment of , the input module 11 is the first buffer unit, and the output module 14 is the second buffer unit.

[0096] Therefore, when the first adjustment link 12 performs the first adjustment operation, it is ​ contrary to the function of the embodiment of . The first adjustment link 12 receives a first bias voltage to perform the first adjustment operation for narrowing the duty cycle of the output clock signal, and the second adjustment link 13 receives a second bias voltage to perform the second adjustment operation for increasing the duty cycle of the output clock signal.

[0097] Different from the prior art, the duty cycle adjustment circuit 100 of the present application can provide the detection signal generated by the duty cycle detector 20 to the state machine 30 to generate a control code, and then generate a bias voltage acting on the duty cycle adjustment link 10 through the control code. The bias voltage can adjust the pull-down current of the intermediate node in the duty cycle adjustment link 10, and further adjust the slope of the rising edge or falling edge of the intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal. Compared with the prior art, the duty cycle adjustment range of the clock signal of the duty cycle adjustment circuit 100 of the present application is wider, and its adjustment accuracy is more precise when adjusting the duty cycle by voltage. Moreover, the duty cycle adjustment circuit 100 of the present application requires fewer transistors, has a small parasitic capacitance, and has a small driving ability requirement for the previous-stage circuit.

[0098] Optionally, the present application further proposes a random access memory. Please refer to ​ , ​ which is a schematic structural diagram of an embodiment of the random access memory of the present application. As ​ shown, the random access memory 200 of this embodiment includes the duty cycle adjustment circuit 100 of any of the above embodiments. The random access memory 200 can be a dynamic random access memory DRAM, a static random access memory SRAM, or a pseudo-static random access memory (Pseudo SRAM, PSRAM).

[0099] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0100] The above are only the embodiments of the present application, and do not limit the patent scope of the present application. Any equivalent structural or equivalent process transformation made according to the content of the specification and drawings of the present application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

Claims

1. A duty cycle adjustment circuit, characterized in that Comprising: A duty cycle adjustment link that receives an initial clock signal and adjusts the initial clock signal to generate an output clock signal; A duty cycle detector coupled to the duty cycle adjustment link to generate a corresponding detection signal based on the detected duty cycle of the output clock signal; A state machine coupled to the duty cycle detector to generate a corresponding control code based on the detection signal; A bias voltage generation module coupled to the state machine and the duty cycle adjustment link respectively, for generating a corresponding bias voltage based on the control code and providing it to the duty cycle adjustment link, wherein the duty cycle adjustment link adjusts the pull-down current of an intermediate node in the duty cycle adjustment link through the bias voltage, adjusts the slope of the rising edge or falling edge of an intermediate clock signal generated by the intermediate node, thereby adjusting the duty cycle of the output clock signal; the bias voltage generation module includes a first bias voltage generation module and a second bias voltage generation module, and the first bias voltage generation module and the second bias voltage generation module each include a bias current generation module and a bias voltage generation module, wherein the bias current generation module includes a plurality of parallel bias current branches and adjusts the number of the bias current branches connected based on the control code, thereby generating a corresponding bias current; the bias voltage generation module is coupled to the bias current generation module to generate and output the bias voltage based on the bias current.

2. The duty cycle adjustment circuit according to claim 1, wherein: The first bias voltage generation module is used to generate a first bias voltage, and the duty cycle adjustment link narrows the duty cycle of the output clock signal based on the first bias voltage; The second bias voltage generation module is used to generate a second bias voltage, and the duty cycle adjustment link increases the duty cycle of the output clock signal based on the second bias voltage.

3. The duty cycle adjustment circuit according to claim 1, wherein Each of the bias current branches in the bias current generation module respectively includes: A first transistor, the control end of the first transistor receives a reference voltage, and the first path end of the first transistor receives a first operating voltage; A switch, the first end of the switch is coupled to the second path end of the first transistor, the second end of the switch is coupled to the bias current output module, and the control end of the switch is used to receive the control code to determine whether the corresponding bias current branch is turned on based on the control of the control code.

4. The duty cycle adjustment circuit according to claim 1, wherein The bias voltage generation module includes: A second transistor, the first path end of the second transistor receives the bias current and is coupled to the control end of the second transistor; the control end of the second transistor outputs the bias voltage; A capacitor, the first end of the capacitor is grounded, and the second end of the capacitor is coupled to the control end of the second transistor.

5. The duty cycle adjustment circuit according to claim 3, characterized in that, Among them, the size ratios of the multiple first transistors included in the multiple bias current branches are successively 1, 2, 4, 8... 2^N, where N is the number of the bias current branches, so that the accuracy of the bias current adjusted based on the control code is continuous within the range of 0 to (2^N - 1)*I0, where I0 is the bias current provided when the first transistor of unit size is connected.

6. The duty cycle adjustment circuit according to claim 2, wherein The duty cycle adjustment link includes: An input module, which receives the initial clock signal and processes it to generate a first input processed clock signal; An output module, which is used to output the output clock signal; A first adjustment link, coupled to the input module, to perform a first adjustment operation and a buffered inversion operation on the first input processed clock signal to output a first clock signal; and A second adjustment link, coupled to the first adjustment link, to perform a second adjustment operation and a buffered inversion operation on a second input processed clock signal to output a second clock signal, where the first input processed clock signal, the second input processed clock signal, the first clock signal, and the second clock signal are respectively used as the intermediate clock signals of the duty cycle adjustment link; Among them, in response to the first adjustment link performing the first adjustment operation, the first adjustment link adjusts the slope of the rising edge or the falling edge of the intermediate clock signal to narrow or increase the duty cycle of the output clock signal; In response to the second adjustment link performing the second adjustment operation, the second adjustment link adjusts the slope of the rising edge or the falling edge of the intermediate clock signal to increase or narrow the duty cycle of the output clock signal.

7. The duty cycle adjustment circuit according to claim 6, wherein The duty cycle adjustment link further includes: A buffer module, coupled between the first adjustment link and the second adjustment link, to buffer the first clock signal output by the first adjustment link to generate a second input processed clock signal.

8. The duty cycle adjustment circuit according to claim 6 or 7, wherein The input module includes: a first buffer unit, which consists of an even number of inverters and receives the initial clock signal to perform a buffer operation, thereby generating the input processed clock signal, where the input processed clock signal is in phase with the initial clock signal; or The input module includes: a first buffer inversion unit, which consists of an odd number of inverters and receives the initial clock signal to perform a buffer inversion operation, thereby generating the input processed clock signal, where the input processed clock signal is out of phase with the initial clock signal.

9. The duty cycle adjustment circuit according to claim 8, wherein The output module includes: a second buffer unit, which consists of an even number of inverters, receives the second clock signal output by the second adjustment link, and performs a buffer operation, thereby generating the output clock signal; or The output module includes: a second buffer inversion unit, which consists of an odd number of inverters, receives the second clock signal output by the second adjustment link, and performs a buffer inversion operation, thereby generating the output clock signal; Wherein, if the input module includes a first buffer unit, the output module includes a second buffer unit; if the input module includes a first buffer inverter unit, the output module includes a second buffer inverter unit.

10. The duty cycle adjustment circuit according to claim 6, wherein the first adjustment link or the second adjustment link respectively includes: an inverter unit, disposed on the main path of the duty cycle adjustment link to perform the buffer inversion operation; a discharge branch, coupled to the inverter unit, receiving the first bias voltage or the second bias voltage, to perform a discharge operation on the intermediate node based on the first bias voltage or the second bias voltage, so as to adjust the slope of the rising edge or the falling edge of the intermediate clock signal; wherein, in response to the first adjustment link performing a first adjustment operation, the slope of the rising edge or the falling edge of the intermediate clock signal is adjusted by the discharge branch in the first adjustment link, and the buffer inversion operations are respectively performed by the inverter units in the first adjustment link and the second adjustment link; in response to the second adjustment link performing the second adjustment operation, the slope of the rising edge or the falling edge of the intermediate clock signal is adjusted by the discharge branch in the second adjustment link, and the buffer inversion operations are respectively performed by the inverter units in the first adjustment link and the second adjustment link.

11. The duty cycle adjustment circuit according to claim 10, wherein the input module includes a first buffer unit, the output module includes a second buffer unit, the first adjustment link receives the first bias voltage to perform the first adjustment operation for narrowing the duty cycle of the output clock signal, and the second adjustment link receives the second bias voltage to perform the second adjustment operation for increasing the duty cycle of the output clock signal; or the input module includes a first buffer inverter unit, the output module includes a second buffer inverter unit, the first adjustment link receives the second bias voltage to perform the first adjustment operation for increasing the duty cycle of the output clock signal, and the second adjustment link receives the first bias voltage to perform the second adjustment operation for narrowing the duty cycle of the output clock signal. ​ ​ ​ ​ When the control terminal of the third transistor receives the first bias voltage or the second bias voltage, the third transistor and the fourth transistor are turned on, and a pull-down current corresponding to the first bias voltage or the second bias voltage is generated between the third transistor and the fourth transistor, and a discharging operation is performed on the intermediate clock signal to adjust the slope of the rising edge of the intermediate clock signal.

13. The duty cycle adjustment circuit according to claim 10, wherein the inverting unit includes: a fifth transistor, the control terminal of the fifth transistor is coupled to the input module, and the first conduction terminal of the fifth transistor receives a second operating voltage; a sixth transistor, the control terminal of the sixth transistor is coupled to the input module, and the first conduction terminal of the sixth transistor is coupled to the second conduction terminal of the fifth transistor, wherein a node between the first conduction terminal of the sixth transistor and the second conduction terminal of the fifth transistor serves as the output terminal of the inverting unit; a seventh transistor, the control terminal of the seventh transistor is coupled to the input module, and the first conduction terminal of the seventh transistor is coupled to the second conduction terminal of the sixth transistor; the second conduction terminal of the seventh transistor is grounded; the discharging branch includes: an eighth transistor, the control terminal of the eighth transistor receives the first bias voltage or the second bias voltage, and the first conduction terminal of the eighth transistor is coupled to the second conduction terminal of the sixth transistor; the second conduction terminal of the eighth transistor is grounded; wherein, when the control terminal of the eighth transistor receives the first bias voltage or the second bias voltage, the eighth transistor is turned on, and the eighth transistor generates a corresponding pull-down current based on the first bias voltage or the second bias voltage, and a discharging operation is performed on the intermediate clock signal to adjust the slope of the falling edge of the intermediate clock signal.

14. A random access memory, characterized in that, including the duty cycle adjustment circuit according to any one of claims 1-13.

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