A circuit for suppressing current overshoot of PFC switch

Abstract

A circuit for suppressing current overshoot of a PFC switch includes a current sampling mode automatic switching circuit, including a voltage regulator tube ZD1 having one end connected to a power supply end of a main control unit U1, the other end of the voltage regulator tube ZD1 being grounded through a resistor R26 and a capacitor C11 respectively, the other end of the voltage regulator tube ZD1 being also connected to one end of a resistor R25, the other end of the resistor R25 being grounded through a capacitor C12, the other end of the resistor R25 being also connected to a gate of a MOS tube Q4, the source being grounded, the drain being connected to a current sampling mode enabling end of the main control unit U1 through a resistor R24, and the current sampling mode enabling end being also connected to ground through a capacitor C9.

Description

Technical Field

[0001] The invention relates to the field of LED power supplies, and in particular to a circuit for suppressing current overshoot of a PFC switch. Background Art

[0002] In traditional switching power supplies, power greater than 75 watts requires a power correction circuit (PFC circuit for short). With a PFC circuit, when the power is turned on and off, a large peak current will flow through the switch tube (MOS tube) in the circuit. The reason is that the output end of the circuit is equipped with a large electrolytic capacitor. When the power is turned on, the charge of the large electrolytic capacitor is 0. At the same time, the transient capacitor voltage cannot change suddenly, which is equivalent to an output short circuit. Therefore, the input peak current is particularly large. At this time, the current flowing through the PFC inductor is very large, so the energy stored in the inductor is very large. At the moment the MOS tube is turned on, the stored energy will be released through the MOS tube, so the current flowing through the MOS is very large. If it is not suppressed, the MOS tube will be damaged due to overcurrent. In the process of power shutdown, the principle is the same, because the energy of the output large electrolytic capacitor has been drawn away by the load, and the input energy of the power grid is cut off due to shutdown. At this time, the energy stored in the PFC inductor must be discharged through the MOS tube. At this time, the reverse peak current is also very large and must be suppressed. The overcurrent protection of the MOS tube can be achieved by controlling the opening time of the MOS tube. Summary of the invention

[0003] In order to solve the above problem, the present technical solution provides a circuit for suppressing current overshoot of a PFC switch.

[0004] To achieve the above purpose, the technical solution is as follows:

[0005] A circuit for suppressing current overshoot of a PFC switch, comprising:

[0006] A main power circuit, wherein the main power is provided with an input end and an output end, and further comprises a transformer LF2, wherein one end of a first coil of the transformer LF2 is connected to the input end, and the end is also connected to the positive electrode of a diode D1, the negative electrode of the diode D1 is connected to the positive electrode of the output end, the other end of the first coil is connected to the positive electrode of a diode D2, the negative electrode of the diode D2 is connected to the positive electrode of the output end, one end of a second coil is connected to the positive electrode of a diode D3 via a resistor R5, and the other end of the second coil is grounded;

[0007] A control IC circuit includes a main control unit U1, a power supply end of the main control unit U1 is connected to the cathode of the diode D3, a driving end of the main control unit U1 is connected to the base of the transistor Q1 through a resistor R17, an emitter of the transistor Q1 is connected to one end of a resistor R15, the resistor R17 is also connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R15, the collector of the transistor Q3 is grounded, the other end of the resistor R15 is connected to the gate of the MOS tube Q2, the source is grounded, the drain is connected to the anode of the diode D2, and the collector of the transistor Q1 is connected to the cathode of the diode D3 through a resistor R9;

[0008] The current sampling mode automatic switching circuit includes a voltage regulator tube ZD1 having one end connected to the power supply end of the main control unit U1, the other end of the voltage regulator tube ZD1 is grounded through a resistor R26 and a capacitor C11 respectively, the other end of the voltage regulator tube ZD1 is also connected to one end of a resistor R25, the other end of the resistor R25 is grounded through a capacitor C12, the other end of the resistor R25 is also connected to the gate of the MOS tube Q4, the source is grounded, and the drain is connected to the current sampling mode enable end of the main control unit U1 through a resistor R24, and the current sampling mode enable end is also connected to ground through a capacitor C9.

[0009] In some embodiments, the output terminal of the error operational amplifier of the main control unit U1 is grounded via the capacitor C4 and the resistor R22 in sequence, and is also grounded via the capacitor C10.

[0010] In some embodiments, the current limiting end of the main control unit U1 is connected to the sampling resistor RCS1 of the input end through the resistor R20, and the end is also grounded through the diode D4 and the diode D5 in sequence, and the end is also grounded through the capacitor C5.

[0011] In some embodiments, the undervoltage protection terminal of the main control unit U1 is connected to the input terminal through resistors R19, R18, R14, R11, R6 and R3 in sequence, and the undervoltage protection terminal is also grounded through resistor R21.

[0012] In some embodiments, the output voltage feedback end of the main control unit U1 is also connected to the positive electrode of the output end through resistors R13, R10, R7, R2 and R1 in sequence, and the output voltage feedback is also grounded through resistor R23 and capacitor C6 respectively.

[0013] In some embodiments, the input end is connected to the power supply end of the main control unit U1 through resistors R4, R8 and R12 in sequence.

[0014] The beneficial effects of this application are:

[0015] The present application uses voltage sampling to determine the moment of power supply startup or shutdown, and automatically switches the current collection mode of the PFC control circuit. Peak current sampling is used at the startup moment to achieve a fast response. After the normal working state, average current sampling is started to improve the stability of the power supply and prevent false operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for describing the embodiments are briefly introduced below.

[0017] Figure 1 It is a schematic structural diagram of an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0019] In view of the above situation, the patent of this invention is mainly used in the field of PFC power factor correction topology technology improvement. A current suppression circuit is added to the traditional switching power supply PFC circuit to improve the failure rate of the power supply, improve the quality of the power supply, and enhance the customer experience and satisfaction. The circuit has high reliability, simple circuit, easy implementation, lower cost, and is conducive to mass use. For details, please refer to Figure 1 As shown, a circuit for suppressing current overshoot of a PFC switch includes:

[0020] A main power circuit, wherein the main power is provided with an input end and an output end, and further comprises a transformer LF2, wherein one end of a first coil of the transformer LF2 is connected to the input end, and the end is also connected to the positive electrode of a diode D1, the negative electrode of the diode D1 is connected to the positive electrode of the output end, the other end of the first coil is connected to the positive electrode of a diode D2, the negative electrode of the diode D2 is connected to the positive electrode of the output end, one end of a second coil is connected to the positive electrode of a diode D3 via a resistor R5, and the other end of the second coil is grounded;

[0021] A control IC circuit includes a main control unit U1, a power supply end of the main control unit U1 is connected to the cathode of the diode D3, a driving end of the main control unit U1 is connected to the base of the transistor Q1 through a resistor R17, an emitter of the transistor Q1 is connected to one end of a resistor R15, the resistor R17 is also connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R15, the collector of the transistor Q3 is grounded, the other end of the resistor R15 is connected to the gate of the MOS tube Q2, the source is grounded, the drain is connected to the anode of the diode D2, and the collector of the transistor Q1 is connected to the cathode of the diode D3 through a resistor R9;

[0022] The current sampling mode automatic switching circuit includes a voltage regulator tube ZD1 having one end connected to the power supply end of the main control unit U1, the other end of the voltage regulator tube ZD1 is grounded through a resistor R26 and a capacitor C11 respectively, the other end of the voltage regulator tube ZD1 is also connected to one end of a resistor R25, the other end of the resistor R25 is grounded through a capacitor C12, the other end of the resistor R25 is also connected to the gate of the MOS tube Q4, the source is grounded, and the drain is connected to the current sampling mode enable end of the main control unit U1 through a resistor R24, and the current sampling mode enable end is also connected to ground through a capacitor C9.

[0023] In this embodiment, the output terminal of the error operational amplifier of the main control unit U1 is grounded via the capacitor C4 and the resistor R22 in sequence, and is also grounded via the capacitor C10.

[0024] In this embodiment, the current limiting end of the main control unit U1 is connected to the sampling resistor RCS1 of the input end through the resistor R20, and the end is also grounded through the diode D4 and the diode D5 in sequence, and the end is also grounded through the capacitor C5.

[0025] In this embodiment, the undervoltage protection terminal of the main control unit U1 is connected to the input terminal through resistors R19, R18, R14, R11, R6 and R3 in sequence, and is also grounded through resistor R21.

[0026] In this embodiment, the output voltage feedback end of the main control unit U1 is also connected to the positive electrode of the output end through resistors R13, R10, R7, R2 and R1 in sequence, and the output voltage feedback is also grounded through resistor R23 and capacitor C6 respectively.

[0027] In this embodiment, the input end is connected to the power supply end of the main control unit U1 through the resistor R4, the resistor R8 and the resistor R12 in sequence.

[0028] A circuit for suppressing current overshoot of a PFC switch machine works as follows:

[0029] 001 is the main power circuit, which is a power factor correction circuit (PFC circuit for short). AC power is input through L and N lines, passes through surge absorber RV1, and then filtered by EMI filter CX1, LF1, and then rectified by rectifier bridge BD1, and then filtered by C2, and sent to PFC inductor LF2 for energy storage. Q2 is the power conversion power tube of the PFC circuit, which plays the role of chopper switch. D2 is a boost diode. After passing through the diode, the energy reaches the output electrolytic E1. The output electrolytic is directly sent to the subsequent electrical appliances for use after energy storage filtering. D1 is an accelerating diode to prevent the PFC inductor from saturating instantly when it is turned on.

[0030] 002 is the control IC circuit:

[0031] Pin 1 of the IC of the main control unit U1 is the reference ground.

[0032] Pin 2 of the IC is the current sampling mode enable pin. If a capacitor is connected to the ground, it is in peak current sampling mode. If a resistor is connected to the ground, it is in average current sampling mode.

[0033] The third pin of IC is the current limiting pin. The negative voltage signal is taken out from the sampling resistor RCS1, and then sent to the third pin after the first-order filtering by R20 and C5. When the voltage of the third pin is higher than the internal reference level, the driving signal of IC will be turned off and the power supply will stop working. Among them, D4 and D5 are clamping diodes to prevent the surge voltage from being too high and burning the IC.

[0034] The 4th pin of IC is the undervoltage protection pin. The input voltage is collected by R3, R6, R11, and R14, then filtered by C3, divided and filtered by R18, R19, R21, and C8, and sent to the 4th pin for comparison with the internal comparator reference value. When the input voltage is lower than the internal threshold, the IC drive signal will be turned off and the power supply will stop working.

[0035] Pin 5 of IC is the output pin of the error operational amplifier inside IC. It is connected with C4, R22 and C10 to form an IPD proportional integral negative feedback network to stabilize the driving signal inside IC and keep the system in a stable state.

[0036] Pin 6 of IC is the output voltage feedback pin. After being filtered through the voltage divider circuit composed of R1, R2, R7, R10, R13, R23 and C6, it is sent to pin 6 and adjusted through the internal operational amplifier to stabilize the output voltage.

[0037] The 7th pin of IC is the power supply pin of IC, which provides all the energy required by IC. The initial energy is formed by the starting resistor composed of R4, R8, and R12, and the power is taken from the rectifier bridge BD1 to start the IC. After the IC works, the auxiliary winding of LF2 is rectified and filtered by R5 and D3 and then sent to the 7th pin to maintain the energy required for the normal operation of the system. Among them, E2 and C7 are used for energy storage and filtering of the 7th pin VCC.

[0038] The 8th pin of IC is the driving signal pin. The driving signal of IC will pass through R17, the totem drive composed of R9, Q1, Q3, and R15, and then be sent to the gate of the power switch tube Q2 to perform PWM driving on Q2. The gate voltage signal is used to adjust the chopping action of the power tube Q2.

[0039] 003 is the required circuit of this right (current sampling mode automatic switching circuit), in which ZD1 voltage regulator takes out the voltage signal from IC7 pin. Because the startup voltage of IC is greater than 12V, the normal working voltage is 15V, and then the IC stops working when it is lower than 8V. Therefore, when the circuit is just started, the VCC voltage of IC's 7th pin will slowly rise. When it exceeds 12V, IC starts to work. At this time, the startup voltage will break through the voltage regulator ZD1, and then the voltage will pass through R26, C11, R25, C12 for second-order filtering. Then the voltage signal is sent to the gate of Q4 for driving. Q4 is a low-voltage MOS tube with a gate startup voltage of 2.5V. As long as the gate voltage is greater than 2.5V, Q4 (MOS tube) will be turned on. When the DS pole of Q4 is turned on, the resistor connected to the 2nd pin of the main control unit U1 will be connected to the ground through the Q4DS pin, realizing the conversion of the current acquisition mode. When the 2nd pin of the main control unit U1 is connected to the ground with a capacitor, it is the peak current acquisition mode, and when it is connected to a resistor, it is the average current acquisition mode. When the main control unit U1 is in the peak current acquisition mode, the current peak value of each cycle will be collected. When the current value exceeds the internal limit threshold, the drive signal output will be stopped and the power MOS tube will be turned off to suppress the current overshoot problem when the system is turned on and off. When the main control unit U1 is in the average current acquisition mode, the current of each cycle will be integrated, and then the current current average value will be taken out, and then compared with the internal limit threshold. When the threshold is exceeded, the output of the drive signal will be stopped and the system will be turned off. The benefit of average current acquisition is to prevent the system from malfunctioning due to external noise interference, and to ensure the reliable operation of the system without shutdown. This application is introduced for the purpose of automatically switching the current mode. When the system starts or shuts down, but the voltage threshold of VCC is not high enough to break through ZD1, Q4 is closed, and the 2nd foot of the main control unit U1 is only connected to the capacitor, so the peak current mode is adopted at this time. When starting or shutting down, the peak value of each current cycle is collected, and the drive of the MOS tube Q2 is turned off when necessary to achieve the purpose of protecting the MOS tube. When the power supply is working normally, the voltage at pin 7 of the main control unit U1 is high enough to break down ZD1, causing Q4 to turn on. Then pin 2 of the main control unit U1 is connected to the ground through a resistor, and the power supply IC is in average current acquisition mode, so the system can operate reliably.

[0040] Because the voltage waveform of the power grid is a sine wave, when the input voltage is at the trough, according to Lenz's law, the PFC inductor starts to release energy, and the input voltage is superimposed at the same time. At this time, the MOS tube is still in the open state. At this time, the peak current flowing through the MOS tube is very large and needs to be suppressed. If necessary, the MOS tube must be turned off. Therefore, at this time, the peak current sampling mechanism of the control IC must be used. When the peak current reaches the protection threshold, the MOS tube must be turned off to prevent large current from flowing through the MOS tube and damaging the MOS tube. When the output electrolytic voltage on the PFC circuit has been fully established, the energy of the PFC inductor has been fully transmitted to the large electrolytic. At this time, the current of the power grid through the PFC inductor has been reduced, and the opening current of the MOS tube has also become smaller. At this time, the current sampling mechanism of the control IC needs to be adjusted to the average current sampling mode to prevent the circuit from malfunctioning due to sudden changes in the output load or grid noise, so as to improve the stability of the power supply system. When shutting down, the working sequence is reversed. After shutdown, the PFC outputs electrolytic energy to be extracted by the load, and the AC power grid no longer provides energy. At this time, the PFC control IC switches the current collection mode from the average current collection mode to the peak current sampling mode to prevent energy backflow after shutdown, which causes a sharp increase in the current of the MOS tube and damage to the device.

[0041] This application is mainly used in the field of PFC circuits. On the basis of traditional PFC circuits, the current flowing through the MOS tube on the PFC circuit is suppressed at the moment of power on and off. By controlling the automatic switching of the IC current sampling mode, the purpose is to solve the problem of a sharp increase in the current flowing through the MOS tube when the output electrolytic energy is lost at the moment of power on and off, thereby causing PFC circuit failure. The circuit is simple, reliable, easy to implement, and can improve the reliability of the switching power supply system and improve user satisfaction.

[0042] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of implementation of the present application. Other principles and basic structures that are the same or similar to those of the present application are within the protection scope of the present application.

Claims

1. A circuit for suppressing current overshoot of a PFC switch, characterized in that: include; A main power circuit, wherein the main power is provided with an input end and an output end, and further comprises a transformer LF2, wherein one end of a first coil of the transformer LF2 is connected to the input end, and the end is also connected to the positive electrode of a diode D1, the negative electrode of the diode D1 is connected to the positive electrode of the output end, the other end of the first coil is connected to the positive electrode of a diode D2, the negative electrode of the diode D2 is connected to the positive electrode of the output end, one end of a second coil is connected to the positive electrode of a diode D3 via a resistor R5, and the other end of the second coil is grounded; A control IC circuit includes a main control unit U1, a power supply end of the main control unit U1 is connected to the cathode of the diode D3, a driving end of the main control unit U1 is connected to the base of the transistor Q1 through a resistor R17, an emitter of the transistor Q1 is connected to one end of a resistor R15, the resistor R17 is also connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to one end of the resistor R15, the collector of the transistor Q3 is grounded, the other end of the resistor R15 is connected to the gate of the MOS tube Q2, the source is grounded, the drain is connected to the anode of the diode D2, and the collector of the transistor Q1 is connected to the cathode of the diode D3 through a resistor R9; The current sampling mode automatic switching circuit includes a voltage regulator tube ZD1 having one end connected to the power supply end of the main control unit U1, the other end of the voltage regulator tube ZD1 is grounded through a resistor R26 and a capacitor C11 respectively, the other end of the voltage regulator tube ZD1 is also connected to one end of a resistor R25, the other end of the resistor R25 is grounded through a capacitor C12, the other end of the resistor R25 is also connected to the gate of the MOS tube Q4, the source is grounded, and the drain is connected to the current sampling mode enable end of the main control unit U1 through a resistor R24, and the current sampling mode enable end is also connected to ground through a capacitor C9.

2. The circuit for suppressing current overshoot of a PFC switch according to claim 1, characterized in that: The output terminal of the error operational amplifier of the main control unit U1 is connected to the ground through the capacitor C4 and the resistor R22 in sequence, and is also connected to the ground through the capacitor C10.

3. The circuit for suppressing current overshoot of PFC switching according to claim 2, characterized in that: The current limiting end of the main control unit U1 is connected to the sampling resistor RCS1 of the input end through the resistor R20, and the end is also grounded through the diode D4 and the diode D5 in sequence, and the end is also grounded through the capacitor C5.

4. The circuit for suppressing current overshoot of a PFC switch according to claim 3, characterized in that: The undervoltage protection terminal of the main control unit U1 is connected to the input terminal through resistors R19, R18, R14, R11, R6 and R3 in sequence, and is also grounded through resistor R21.

5. The circuit for suppressing current overshoot of a PFC switch according to claim 4, characterized in that: The output voltage feedback end of the main control unit U1 is also connected to the positive electrode of the output end through resistors R13, R10, R7, R2 and R1 in sequence, and the output voltage feedback is also grounded through resistor R23 and capacitor C6 respectively.

6. The circuit for suppressing current overshoot of a PFC switch according to claim 5, characterized in that: The input end is connected to the power supply end of the main control unit U1 through the resistor R4, the resistor R8 and the resistor R12 in sequence.

Images