High-precision noise shaping pipelined SAR ADC based on gain error shaping

Abstract

The application discloses a high-precision noise shaping pipeline SAR ADC based on gain error shaping, solves the problems of low quantization precision and resolution in the prior art, and comprises the following steps: rough quantization is performed on an input voltage, and an 8-bit digital code is output; the weight of the first digital code is digitally weighted to obtain a weighted first digital code; a gain error shaping circuit is used for shaping filtering a second digital code to obtain a third digital code; the weighted first digital code is converted into an analog voltage, the third digital code is converted into a residual voltage, and subtraction calculation is performed on the analog voltage and the residual voltage to obtain a voltage Q1; the voltage Q1 is processed to obtain an amplified voltage; the amplified voltage is quantized, noise shaping is performed, and a fourth digital code is obtained; and the output digital code of the shaping circuit is calculated according to the first digital code, the third digital code and the fourth digital code; and the application realizes the improvement of the signal-to-noise ratio of the ADC and has the advantages of high speed, high precision and low power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-precision noise shaping pipeline SAR ADC based on gain error shaping. Background Art

[0002] Analog-to-digital converters (ADCs) bridge the gap between the analog world and digital systems and are widely used in various scenarios, such as camera sensors, microphones, and light sensors. The accuracy and speed of ADCs are crucial to the operating speed and performance of subsequent digital circuits.

[0003] The pipelined SAR ADC reuses the single-stage SAR ADC structure by amplifying the residual voltage, reducing circuit area and exponentially increasing the ADC's operating speed. Thanks to the pipelined structure and the operating principles of the SAR ADC, high speed and low power consumption are achieved.

[0004] However, amplifiers struggle to provide perfectly accurate interstage gain, and gain inaccuracies significantly reduce the quantization accuracy of pipeline ADCs. Furthermore, comparator noise and the exponentially increasing capacitance array with the number of bits also limit further improvements in SAR ADC resolution. Summary of the Invention

[0005] The present invention provides a high-precision noise-shaping pipeline SAR ADC based on gain error shaping, which solves the problems of low quantization accuracy and low resolution of pipeline ADCs in the prior art. It uses the gain error shaping technology to calibrate the residual amplifier gain and reduce the nonlinear error caused by it. At the same time, the quantization error is shaped by the noise shaping technology, thereby improving the signal-to-noise ratio of the ADC. The invention has the advantages of high speed, high precision and low power consumption.

[0006] The present invention provides a high-precision noise shaping pipeline SAR ADC based on gain error shaping, the circuit comprising:

[0007] The first-stage auxiliary dual-residual pipeline SAR ADC circuit, dynamic weighted average circuit, gain error shaping circuit, main digital-to-analog converter circuit, feedforward two-stage floating inverting amplifier circuit and second-stage noise shaping SAR ADC circuit;

[0008] The first-stage auxiliary dual-residual pipeline SAR ADC circuit is used to coarsely quantize the input voltage and output an 8-bit digital code; wherein the 8-bit digital code includes: a first 6-bit digital code and a last 2-bit digital code; the first 6-bit digital code is a first digital code, and the last 2-bit digital code is a second digital code;

[0009] The dynamic weighted averaging circuit is used to digitally weight the weight of the first digital code to obtain a weighted first digital code;

[0010] The gain error shaping circuit is used to perform gain error shaping filtering on the second digital code to obtain a third digital code; wherein the third digital code is a 3-bit digital code;

[0011] The main digital-to-analog converter circuit is used to convert the weighted first digital code into an analog voltage, convert the third digital code into a residual voltage, and perform a subtraction calculation on the analog voltage and the residual voltage to obtain a digital-to-analog conversion voltage Q1;

[0012] The feedforward two-stage floating inverting amplifier circuit is used to process the voltage Q1 into an amplified digital-to-analog conversion voltage Q1 with a stable common-mode voltage;

[0013] The second-stage noise shaping SAR ADC circuit is used to quantize the amplified digital-to-analog conversion voltage Q1 and perform noise shaping to obtain a fourth digital code; wherein the fourth digital code is a 7-bit digital code;

[0014] An output digital code of the shaping circuit is obtained by calculation according to the first digital code, the third digital code and the fourth digital code.

[0015] In a possible implementation, the first-stage auxiliary dual-residual pipeline SAR ADC circuit includes: a CDAC circuit, a first SWITCH circuit, a capacitor C T , SHIFT_BIT circuit, residual amplifier circuit, CDAC U Circuit, CDAC L circuit, an amplifier circuit, a first switch, and a control circuit;

[0016] A first terminal of the CDAC circuit is connected to the input voltage, and a second terminal is connected to the first terminal of the first SWITCH circuit;

[0017] The second end of the first SWITCH circuit is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage;

[0018] The capacitor C T A first end of the MOSFET is connected to the input voltage, and a second end of the MOSFET is connected to the first end of the SHIFT_BIT circuit;

[0019] The second end of the SHIFT_BIT circuit is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage;

[0020] The first end of the residual amplifier circuit is connected to the input voltage, and the second end is connected to the CDAC U The first end of the circuit;

[0021] The CDAC U The second end of the circuit is connected to the first end of the first switch;

[0022] The second end of the first switch is connected to the voltage Vcm;

[0023] The CDAC L The first end of the circuit is connected to the second end of the residual amplifier circuit, and the second end is connected to the first end of the first switch;

[0024] The first input terminal of the amplifier circuit is connected to the first terminal of the first switch, the second input terminal is connected to the Vcm voltage, and the output terminal is connected to the first terminal of the control circuit;

[0025] The second end of the control circuit is connected to the dynamic weighted averaging circuit and the gain error shaping circuit.

[0026] In one possible implementation, the CDAC U circuit with the CDAC L The circuit structures are the same, both comprising: a first capacitor, a second capacitor and a second SWITCH circuit; the second SWITCH circuit is connected in parallel with the first capacitor and the second capacitor.

[0027] In one possible implementation, the first-stage auxiliary dual-residual pipeline SAR ADC circuit is specifically configured to:

[0028] The CDAC circuit and the first SWITCH circuit cooperate to quantize the input voltage using a successive approximation method to obtain the first digital code;

[0029] By switching the capacitor C T The voltages of the upper and lower plates are obtained to obtain the second digital code;

[0030] The first digital code and the second digital code are combined to form the 8-bit digital code.

[0031] In one possible implementation, the feedforward two-stage floating inverting amplifier circuit includes: a first-stage feedforward floating amplifier circuit, a second-stage feedforward floating amplifier circuit, and a feedforward circuit; the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit both include energy storage capacitors and inverters;

[0032] The first-stage feedforward floating amplifier circuit is configured to charge an energy storage capacitor in the first-stage feedforward floating amplifier circuit using a power supply voltage VDD, and the charged voltage drives an inverter in the first-stage feedforward floating amplifier circuit to process the voltage Q1 and output a first voltage;

[0033] The second-stage feedforward floating amplifier circuit is configured to charge an energy storage capacitor in the second-stage feedforward floating amplifier circuit using a power supply voltage VDD, and the charged voltage drives an inverter in the second-stage feedforward floating amplifier circuit to process the first voltage and output a second voltage;

[0034] The feedforward circuit is used to feedforward the input voltage of the first-stage feedforward floating amplifier circuit to the output end of the second-stage feedforward floating amplifier circuit.

[0035] In a possible implementation, the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit have the same circuit structure.

[0036] In one possible implementation, the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit include: a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first energy storage capacitor, a first inverter, and a second inverter;

[0037] A first end of the second switch is connected to the high level end of the voltage Q1, and a second end is connected to the Vcm voltage;

[0038] The first end of the third switch is connected to the low level end of the voltage Q1, and the second end is connected to the Vcm voltage;

[0039] A first end of the fourth switch is connected to the power supply voltage VDD, and a second end is connected to the first end of the first energy storage capacitor;

[0040] The second end of the first energy storage capacitor is connected to the second end of the fifth switch;

[0041] A first terminal of the fifth switch is grounded;

[0042] The first end of the sixth switch is connected to the second end of the fourth switch, the first end is connected to the first input end of the first inverter, and the first end is also connected to the input end of the feedforward circuit;

[0043] The second input terminal of the first inverter is connected to the high level end of the voltage Q1, the third input terminal is connected to the first end of the seventh switch, and the output terminal is connected to the second-stage feedforward floating amplifier circuit;

[0044] The second end of the seventh switch is connected to the second end of the fifth switch;

[0045] The first input end of the second inverter is connected with the input end of the feedforward circuit, the second input end is connected with the low level end of the voltage Q1, the third input end is connected with the first input end of the feedforward circuit, and the output end is connected with the second-stage feedforward floating amplifier circuit.

[0046] In a possible implementation, the output end of the feedforward circuit is connected on the output end of the first-stage feedforward floating amplifier circuit, and the input end of the feedforward circuit is connected with the output end of the first-stage feedforward floating amplifier circuit.

[0047] The one or more technical solutions provided in the application have at least the following technical effects or advantages:

[0048] (1) The application reduces the influence of mismatch error by adopting a dynamic weighted average circuit and performing digital weighted average on the weight of a bit, reduces the mismatch error caused by the manufacturing process, and thus affects the weight of different bits, and further affects the overall conversion accuracy, thereby improving the conversion accuracy of the ADC.

[0049] (2) The feedforward circuit in the feedforward two-stage floating inverting amplifier circuit can improve the phase in the high-frequency region, although some gain is sacrificed, but the conversion rate and the gain-bandwidth product are increased. BRIEF DESCRIPTION OF DRAWINGS

[0050] Figure 1 The circuit block diagram of the high-precision noise shaping SAR ADC based on gain error shaping provided for the embodiment of the application is provided;

[0051] Figure 2 The first-stage auxiliary double residual pipeline SAR ADC circuit diagram provided for the embodiment of the application is provided;

[0052] Figure 3 The first-stage auxiliary double residual pipeline SAR ADC circuit diagram provided for the embodiment of the application is provided;

[0053] Figure 4 The feedforward two-stage floating inverting amplifier circuit diagram provided for the embodiment of the application is provided. DETAILED DESCRIPTION

[0054] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative labor fall within the protection scope of the application.

[0055] The application provides a high-precision noise shaping pipeline SAR ADC based on gain error shaping. Figure 1 As shown in the figure, it comprises: a first-stage auxiliary dual-residue pipeline SAR ADC circuit, a dynamic weighted averaging circuit, a gain error shaping circuit, a main digital-to-analog converter circuit, a feedforward two-stage floating inverter amplifier circuit and a second-stage noise shaping SAR ADC circuit. Figure 1 In the figure, Δ represents gain error; G represents ideal amplification multiple; Auxiliary Dual-residue Pipelined-SAR ADC: auxiliary dual-residue pipeline SAR ADC circuit, which is composed of a sampling switch, a DAC array, a comparator, a successive approximation register and a residue amplifier; DWA: dynamic weighted averaging circuit, which is composed of an encoder, a shifter, an adder and a register; GES: gain error shaping circuit, which is composed of a register and an adder; main DAC: main digital-to-analog converter circuit, which is mainly composed of a sampling switch and a capacitor array; FIA: floating inverter amplifier, which is composed of an energy storage capacitor, an inverter and a feedforward circuit; 2 nd NS SAR ADC: second-stage noise shaping SAR ADC circuit, which is composed of a sampling switch, a DAC array, a comparator, a successive approximation register, a dynamic amplifier (DA), a feedforward capacitor and a feedback capacitor.

[0056] The first-stage auxiliary dual-residue pipeline SAR ADC circuit is used for rough quantization of an input voltage and output of an 8-bit digital code; wherein the 8-bit digital code comprises: a first 6-bit digital code and a second 2-bit digital code; the first 6-bit digital code is a first digital code, and the second 2-bit digital code is a second digital code.

[0057] Specifically, the first-stage auxiliary dual-residue pipeline SAR ADC circuit, as shown in the figure, Figure 2 and Figure 3 comprises: a CDAC circuit, a first SWITCH circuit SWITCH1, a capacitor C T , a SHIFT_BIT circuit, a residue amplifier circuit, a CDAC U circuit, a CDAC L circuit, an amplifier circuit, a first switch K1 and a control circuit.

[0058] The first end of the CDAC circuit is connected with an input voltage, and the second end is connected with the first end of the first SWITCH circuit SWITCH1.

[0059] A second terminal of the first SWITCH circuit SWITCH1 is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage;

[0060] Capacitor C T A first end of is connected to the input voltage, and a second end of is connected to the first end of the SHIFT_BIT circuit;

[0061] The second terminal of the SHIFT_BIT circuit is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage;

[0062] The first terminal of the residual amplifier circuit is connected to the input voltage, and the second terminal is connected to the CDAC U The first end of the circuit;

[0063] CDAC U The second end of the circuit is connected to the first end of the first switch K1;

[0064] The second end of the first switch K1 is connected to the voltage Vcm;

[0065] CDAC L The first end of the circuit is connected to the second end of the residual amplifier circuit, and the second end is connected to the first end of the first switch K1;

[0066] The first input terminal of the amplifier circuit is connected to the first terminal of the first switch K1, the second input terminal is connected to the Vcm voltage, and the output terminal is connected to the first terminal of the control circuit;

[0067] The second end of the control circuit is connected to the dynamic weighted average circuit and the gain error shaping circuit.

[0068] Specifically, CDAC U Circuit and CDAC L The circuit structures are the same, both including: a first capacitor 2C, a second capacitor C and a second SWITCH circuit SWITCH2; the second SWITCH circuit SWITCH2 is connected to the first capacitor 2C and the second capacitor C in parallel.

[0069] Exemplarily, the first-stage auxiliary dual-residual pipeline SAR ADC circuit performs coarse quantization on the input voltage and outputs an 8-bit digital code. The upper 6-bit code (first digital code) is dynamically weighted averaged by the DWA circuit to reduce the error caused by capacitor mismatch.

[0070] Specifically, the first-stage auxiliary dual-residual pipeline SAR ADC circuit is specifically used for:

[0071] (1) The CDAC circuit and the first SWITCH circuit SWITCH1 cooperate to quantize the input voltage using a successive approximation method to obtain a first digital code;

[0072] (2) By switching capacitor C T The voltages of the upper and lower plates are adjusted to obtain a second digital code; wherein the first digital code and the second digital code are combined to form an 8-bit digital code.

[0073] For example, the first-stage auxiliary dual-residual pipeline SAR ADC circuit first quantizes the input voltage by successive approximation and outputs a 6-bit digital code. T The voltage of the lower plate, first let the voltage of the lower plate be V refp The upper plate voltage is amplified by the residual amplifier and outputs A·V RES_U , then let the lower plate voltage be V refn The upper plate voltage is amplified by the residual amplifier and outputs A·V RES_L The two voltages are stored in CDAC U and CDAC L When sampling, the upper plate voltage is set to V cm , first CDAC L The lower board is suspended, A·V RES_U Sampled into CDAC U On, after, CDAC U The lower board is suspended, A·V RES_L Sampled into CDAC L superior.

[0074] Then enter the comparison stage, first the upper plate is floating, disconnected from V cm connection.

[0075] (1) CDAC U and CDAC L The lower plate of capacitor C in the circuit is connected to V cm , at this time the upper plate voltage is:

[0076] V TOP =(A·V RES_U +A·V RES_L ) / 2

[0077] V TOP With V cm For comparison, if V TOP >V cm , it means that the first-stage residual voltage is greater than V cm , the 7th digit code is "1", otherwise, the 7th digit code is "0".

[0078] (2) If the 7th digit is "1", continue to CDAC L The capacitor 2C in the lower plate is connected to V cm , at this time the upper plate voltage is:

[0079] V TOP =(A·V RES_U +3A·V RES_L ) / 4

[0080] V TOP With V cm For comparison, if V TOP >V cm , the 8th digit code is "1", otherwise, the 8th digit code is "0".

[0081] Similarly, if the 7th digit is "0", then CDAC U The capacitor 2C in the lower plate is connected to V cm , at this time the upper plate voltage is:

[0082] V TOP =(3A·V RES_U +A·V RES_L ) / 4

[0083] V TOP With V cm For comparison, if V TOP >V cm , the 8th digit code is "1", otherwise, the 8th digit code is "0".

[0084] The dynamic weighted averaging circuit is used to digitally weight the weight of the first digital code to obtain a weighted first digital code; illustratively, the upper 6-bit code is dynamically weighted averaged through the DWA circuit to reduce the error caused by capacitor mismatch.

[0085] The gain error shaping circuit is used to perform gain error shaping filtering on the second digital code to obtain a third digital code; wherein the third digital code is a 3-bit digital code; illustratively, the lower 2 bits (the second digital code) are input into the dynamic weighted averaging circuit for gain error shaping, and a 3-bit digital code (the weighted first digital code) is output.

[0086] The main digital-to-analog converter circuit is used to convert the weighted first digital code into an analog voltage, convert the third digital code into a residual voltage, and perform subtraction calculation on the analog voltage and the residual voltage to obtain a digital-to-analog conversion voltage Q1;

[0087] For example, after the input signal is input, it is first sampled simultaneously by the main DAC (main digital-to-analog converter circuit) and the auxiliary dual-residual pipeline SAR ADC (first-stage auxiliary dual-residual pipeline SAR ADC circuit). At this time, the voltages sampled on the main DAC and the auxiliary SAR capacitor array are equal. The auxiliary dual-residual pipeline SAR ADC then quantizes the input signal and outputs an 8-bit digital code. The first 6 bits serve as the output of the first-stage SAR ADC, and the last two bits are filtered to produce a 3-bit digital code. The main DAC converts this into an analog voltage and subtracts it from the residual voltage for gain error shaping.

[0088] The main DAC receives the digital code generated by the auxiliary dual-residual pipeline SAR ADC and converts it into a residual voltage to drive the residual amplifier. It also subtracts the quantization error prediction of the gain error shaping filter from the residual voltage to achieve gain error shaping. To mitigate mismatch errors introduced during the manufacturing process, which can lead to inaccurate bit weightings and thus affect overall conversion accuracy, DWA (dynamic weighted averaging) technology is employed. DWA reduces the impact of mismatch errors by performing a digital weighted average of the bit weights, thereby improving ADC conversion accuracy.

[0089] The feedforward two-stage floating inverting amplifier circuit is used to process the voltage Q1 into an amplified digital-to-analog conversion voltage Q1 having a stable common-mode voltage.

[0090] Specifically, a feedforward two-stage floating inverting amplifier circuit, such as Figure 4 The circuit diagram includes a first-stage feedforward floating amplifier circuit, a second-stage feedforward floating amplifier circuit, and a feedforward circuit. Both the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit include energy storage capacitors and inverters. The first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit have the same circuit structure.

[0091] The first-stage feedforward floating amplifier circuit is used to charge the energy storage capacitor in the first-stage feedforward floating amplifier circuit using the power supply voltage VDD, and the charged voltage drives the inverter in the first-stage feedforward floating amplifier circuit to process the voltage Q1 and output a first voltage;

[0092] The second-stage feedforward floating amplifier circuit is configured to charge the energy storage capacitor in the second-stage feedforward floating amplifier circuit using the power supply voltage VDD, and the charged voltage drives the inverter in the second-stage feedforward floating amplifier circuit to process the first voltage and output a second voltage;

[0093] The feedforward circuit is used for feeding forward the input voltage of the first-stage feedforward floating amplifier circuit to the output end of the second-stage feedforward floating amplifier circuit.

[0094] Specifically, the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit are as follows: Figure 4 The diagram includes: a second switch K2, a third switch K3, a fourth switch K4, a fifth switch K5, a sixth switch K6, a seventh switch K7, a first energy storage capacitor C R1 , a first inverter F1 and a second inverter F2;

[0095] A first end of the second switch K2 is connected to the high level end of the voltage Q1, and a second end is connected to the voltage Vcm;

[0096] A first end of the third switch K3 is connected to the low level end of the voltage Q1, and a second end is connected to the voltage Vcm;

[0097] The first end of the fourth switch K4 is connected to the power supply voltage VDD, and the second end is connected to the first energy storage capacitor C R1 The first end of

[0098] The first energy storage capacitor C R1 The second end of is connected to the second end of the fifth switch K5;

[0099] A first end of the fifth switch K5 is grounded;

[0100] A first end of the sixth switch K6 is connected to the second end of the fourth switch K4, is connected to the first input end of the first inverter F1, and is also connected to the input end of the feedforward circuit;

[0101] The second input terminal of the first inverter F1 is connected to the high level end of the voltage Q1, the third input terminal is connected to the first end of the seventh switch K7, and the output terminal is connected to the second-stage feedforward floating amplifier circuit;

[0102] The second end of the seventh switch K7 is connected to the second end of the fifth switch K5;

[0103] The first input terminal of the second inverter F2 is connected to the input terminal of the feedforward circuit, the second input terminal is connected to the low level terminal of the voltage Q1, the third input terminal is connected to the first input terminal of the feedforward circuit, and the output terminal is connected to the second-stage feedforward floating amplifier circuit.

[0104] Specifically, such as Figure 4 The circuit shown includes: the output end of the feedforward circuit is connected to the output end of the first-stage feedforward floating amplifier circuit, and the input end is connected to the output end of the first-stage feedforward floating amplifier circuit.

[0105] Here, as Figure 4 As shown, the red and blue lines in the figure are connected to each other.

[0106] The feedforward two-stage floating inverting amplifier circuit adopts a standard closed-loop structure. The core part is a two-stage FIA ​​with feedforward, which is composed of energy storage capacitors C R1 、C R2. C DAC2 The DAC capacitor array of the second-stage SAR ADC acts as the load of the dynamic amplifier. When the amplifier is working, the output current flows through C int Feedback to the input terminal reduces the input differential voltage at the input terminal, and finally establishes the voltage at the output terminal, completing the amplification process. Similar to traditional closed-loop OTA, the transfer function of the system mainly depends on the ratio of the capacitance, that is, C int / C DAC In addition, due to the feedback structure, the circuit is insensitive to clock jitter. The two-stage FIA ​​structure can provide higher open-loop gain, improve bandwidth, and enable the amplifier to operate at higher frequencies.

[0107] Exemplary, feedforward two-stage floating inverting amplifier circuit working principle: the first stage auxiliary dual residual pipeline SARADC circuit consists of a storage capacitor C R1 Drive. When When high, FIA is in reset state, and the input and output are reset to V cm , energy storage capacitor C R1 After that, Φ1 is high, FIA starts to work, and the energy storage capacitor C R1 Drive the inverter. As the amplification process proceeds, current flows through the inverter, the charge on the capacitor is completely exhausted, and finally the inverter is turned off, and the voltage on the output load reaches a stable state. Among them, the voltage at the second switch K2, the third switch K3, the fourth switch K4 and the fifth switch K5 is expressed as The voltages at the sixth switch K6 and the seventh switch K7 are denoted by Φ1.

[0108] The same principle applies to the first-stage auxiliary dual-residual pipeline SAR ADC circuit. The energy storage capacitor acts as a power source during operation. According to the law of charge conservation, the current flowing out of the top plate of the capacitor is equal to the current flowing into the bottom plate. Therefore, the current flowing through the two inverters is necessarily a differential current signal, ultimately resulting in a stable common-mode output voltage.

[0109] In order to improve the stability of the operational amplifier, a feedforward circuit is introduced. The main structure of the feedforward circuit is an inverter, which shares a storage capacitor C with the first-stage FIA. R1 The input stage itself uses a differential structure, which provides sufficient common-mode feedback and bandwidth. However, at high frequencies, the phase drops sharply, reducing the stability of the amplifier. Introducing a feedforward circuit can improve the phase in the high-frequency region, although this sacrifices some gain, but increases the slew rate and gain-bandwidth product.

[0110] The second-stage noise shaping SAR ADC circuit is used to quantize the amplified digital-to-analog conversion voltage Q1 and perform noise shaping to obtain a fourth digital code; wherein the fourth digital code is a 7-bit digital code;

[0111] An output digital code of the shaping circuit is obtained by calculation according to the first digital code, the third digital code and the fourth digital code.

[0112] For example, for the recovery of the predicted value (third digital code), the present invention adopts the recovery technology of the digital domain. The digital code corresponding to the predicted value is actually the three-digit digital code generated by the corresponding filter. The present invention adopts the off-chip recovery method and directly adds it to the output code in the digital domain to complete the recovery.

[0113] Therefore, the second-stage noise shaping SAR ADC circuit only needs to quantize the amplified residual voltage, perform noise shaping, and output a 7-bit digital code.

[0114] The final output is:

[0115] D OUT =D 1,6MSB +D GES +D2 / G

[0116] Among them, D 1,6MSB Indicates the first digital code; D GES represents the third digital code; D2 represents the fourth digital code; G represents the ideal magnification.

[0117] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, it should be understood by those skilled in the art that the technical solutions described in the aforementioned embodiments may still be modified, or some or all of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the present invention.

Claims

1. A high-precision noise shaping pipeline SAR ADC based on gain error shaping, characterized in that: include: The first-stage auxiliary dual-residual pipeline SAR ADC circuit, dynamic weighted average circuit, gain error shaping circuit, main digital-to-analog converter circuit, feedforward two-stage floating inverting amplifier circuit and second-stage noise shaping SAR ADC circuit; The first-stage auxiliary dual-residual pipeline SAR ADC circuit is used to coarsely quantize the input voltage and output an 8-bit digital code; wherein the 8-bit digital code includes: a first 6-bit digital code and a last 2-bit digital code; the first 6-bit digital code is a first digital code, and the last 2-bit digital code is a second digital code; The dynamic weighted averaging circuit is used to digitally weight the weight of the first digital code to obtain a weighted first digital code; The gain error shaping circuit is used to perform gain error shaping filtering on the second digital code to obtain a third digital code; wherein the third digital code is a 3-bit digital code; The main digital-to-analog converter circuit is used to convert the weighted first digital code into an analog voltage, convert the third digital code into a residual voltage, and perform a subtraction calculation on the analog voltage and the residual voltage to obtain a digital-to-analog conversion voltage Q1; The feedforward two-stage floating inverting amplifier circuit is used to process the voltage Q1 into an amplified digital-to-analog conversion voltage Q1 with a stable common-mode voltage; The second-stage noise shaping SAR ADC circuit is used to quantize the amplified digital-to-analog conversion voltage Q1 and perform noise shaping to obtain a fourth digital code; wherein the fourth digital code is a 7-bit digital code; An output digital code of the shaping circuit is calculated based on the first digital code, the third digital code, and the fourth digital code, wherein the output digital code is expressed as: ； in, Indicates the first digital code; Indicates the third digit code; Indicates the fourth digit code; Represents the amplification factor of the ideal residual amplifier circuit.

2. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 1, wherein: The first-stage auxiliary dual-residual pipeline SAR ADC circuit includes: a CDAC circuit, a first SWITCH circuit, a capacitor , SHIFT_BIT circuit, residual amplifier circuit, Circuits, circuit, an amplifier circuit, a first switch, and a control circuit; A first terminal of the CDAC circuit is connected to the input voltage, and a second terminal is connected to the first terminal of the first SWITCH circuit; The second end of the first SWITCH circuit is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage; The capacitor A first end of the MOSFET is connected to the input voltage, and a second end of the MOSFET is connected to the first end of the SHIFT_BIT circuit; The second end of the SHIFT_BIT circuit is connected to any one of the Vrefp voltage, the Vcm voltage and the Vrefn voltage; The first end of the residual amplifier circuit is connected to the input voltage, and the second end is connected to the The first end of the circuit; described The second end of the circuit is connected to the first end of the first switch; The second end of the first switch is connected to the voltage Vcm; described The first end of the circuit is connected to the second end of the residual amplifier circuit, and the second end is connected to the first end of the first switch; The first input terminal of the amplifier circuit is connected to the first terminal of the first switch, the second input terminal is connected to the Vcm voltage, and the output terminal is connected to the first terminal of the control circuit; The second end of the control circuit is connected to the dynamic weighted averaging circuit and the gain error shaping circuit.

3. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 2, wherein: described Circuit and the The circuit structures are the same, and both include: a first capacitor, a second capacitor, and a second SWITCH circuit; the second SWITCH circuit is connected in parallel with the first capacitor and the second capacitor.

4. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 2, wherein: The first-stage auxiliary dual-residual pipeline SAR ADC circuit is specifically used for: The CDAC circuit and the first SWITCH circuit cooperate to quantize the input voltage using a successive approximation method to obtain the first digital code; By switching the capacitor The voltages of the upper and lower plates are obtained to obtain the second digital code; The first digital code and the second digital code are combined to form the 8-bit digital code.

5. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 1, wherein: The feedforward two-stage floating inverting amplifier circuit includes: a first-stage feedforward floating amplifier circuit, a second-stage feedforward floating amplifier circuit and a feedforward circuit; the first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit both include energy storage capacitors and inverters; The first-stage feedforward floating amplifier circuit is configured to charge an energy storage capacitor in the first-stage feedforward floating amplifier circuit using a power supply voltage VDD, and the charged voltage drives an inverter in the first-stage feedforward floating amplifier circuit to process the voltage Q1 and output a first voltage; The second-stage feedforward floating amplifier circuit is configured to charge an energy storage capacitor in the second-stage feedforward floating amplifier circuit using a power supply voltage VDD, and the charged voltage drives an inverter in the second-stage feedforward floating amplifier circuit to process the first voltage and output a second voltage; The feedforward circuit is used to feedforward the input voltage of the first-stage feedforward floating amplifier circuit to the output end of the second-stage feedforward floating amplifier circuit.

6. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 5, characterized in that: The first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit have the same circuit structure.

7. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 5, characterized in that: The first-stage feedforward floating amplifier circuit and the second-stage feedforward floating amplifier circuit each include: a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first energy storage capacitor, a first inverter, and a second inverter; A first end of the second switch is connected to the high level end of the voltage Q1, and a second end is connected to the Vcm voltage; The first end of the third switch is connected to the low level end of the voltage Q1, and the second end is connected to the Vcm voltage; A first end of the fourth switch is connected to the power supply voltage VDD, and a second end is connected to the first end of the first energy storage capacitor; The second end of the first energy storage capacitor is connected to the second end of the fifth switch; A first terminal of the fifth switch is grounded; The first end of the sixth switch is connected to the second end of the fourth switch, the first end is connected to the first input end of the first inverter, and the first end is also connected to the input end of the feedforward circuit; The second input terminal of the first inverter is connected to the high level end of the voltage Q1, the third input terminal is connected to the first end of the seventh switch, and the output terminal is connected to the second-stage feedforward floating amplifier circuit; The second end of the seventh switch is connected to the second end of the fifth switch; The first input terminal of the second inverter is connected to the input terminal of the feedforward circuit, the second input terminal is connected to the low level terminal of the voltage Q1, the third input terminal is connected to the first input terminal of the feedforward circuit, and the output terminal is connected to the second-stage feedforward floating amplifier circuit.

8. The high-precision noise shaping pipeline SAR ADC based on gain error shaping according to claim 5, wherein: The output end of the feedforward circuit is connected to the output end of the first-stage feedforward floating amplifier circuit, and the input end of the feedforward circuit is connected to the output end of the first-stage feedforward floating amplifier circuit.

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