AUX channel signal conversion device and conversion method of DP interface

Abstract

The present invention relates to an AUX channel signal conversion device and conversion method of a DP interface, wherein the first end of a first transceiver module is connected to the Source end of an AUX channel, and the second end is connected to the first end of a second transceiver module; the second end of the second transceiver module is connected to the Sink end of an AUX channel signal; the first transceiver module is used to receive an AUX access signal initiated by the Source end and convert it into a first TTL signal; it is also used to receive a second TTL signal sent by the second transceiver module and convert it into a second LVDS signal; the second transceiver module is used to receive an AUX reply signal sent by the Sink end and convert it into a second TTL signal; it is also used to receive a first TTL signal sent by the first transceiver module and convert it into a first LVDS signal. The present invention converts an AUX channel of a differential bidirectional half-duplex transmission mode into a bidirectional TTL mode, so that the AUX channel can be directly connected to a serial-to-parallel conversion circuit without the intervention of an FPGA chip, providing a simpler implementation method for optical communication extension, signal recovery, long-distance transmission, etc. of a DP interface.

Description

Technical Field

[0001] The present invention relates to the field of information communication technology, and in particular to an AUX channel signal conversion device and a conversion method of a DP interface. Background Art

[0002] DisplayPort (DP for short) is a digital video interface standard standardized by the Video Electronics Standards Association (VESA). Its DP1.4 version interface specification requires support for a maximum video resolution of 7680x4320 and a 60Hz refresh rate output. It is widely used in the video input and output interfaces of various display sources and display devices such as computers, monitors, TVs, projectors, etc.

[0003] The DP AUX channel is an auxiliary channel of the DP interface, which is mainly used to read the extended display identification data (EDID); read the DP interface information supported by the display (such as the number of main channels, the transmission rate of DP signals, etc.); set various display configuration registers; read the display status register, etc. It plays a vital role in the DP transmission process and must exist in the DP interface.

[0004] In the actual transmission process, the DP signal (including AUX channel information) is affected by step-by-step attenuation, linear attenuation and interference signals, which limits the transmission distance of the DP signal in some applications. It is necessary to adopt signal relay, optical fiber extension and other measures to make up for its inability to transmit over long distances.

[0005] In order to solve the transmission problem of AUX in DP, the traditional method requires adding an FPGA chip to the system to parse the data information on the AUX channel and then perform information proxy, simulation and recovery mechanisms on it. This not only increases the technical difficulty of the solution and application but also has high cost requirements, thus limiting the application and demand for DP functions in many consumer markets. Summary of the invention

[0006] In view of this, the purpose of the present invention is to provide an AUX channel signal conversion device and conversion method of a DP interface, so as to overcome the technical problems of signal step-by-step attenuation, linear attenuation and the influence of interference signals in the transmission process of DP signals (including AUX channel information) in the prior art.

[0007] To achieve the above objectives, the present invention adopts the following technical solutions:

[0008] According to a first aspect of the present invention, the present invention provides an AUX channel signal conversion device of a DP interface, the device comprising a first transceiver module and a second transceiver module;

[0009] The first end of the first transceiver module is connected to the Source end of the AUX channel;

[0010] The second end of the first transceiver module is connected to the first end of the second transceiver module;

[0011] The second end of the second transceiver module is connected to the Sink end of the AUX channel signal;

[0012] The first transceiver module is used to receive the AUX access signal initiated by the Source end, and convert the AUX access signal into a first TTL signal; and is also used to receive the second TTL signal sent by the second transceiver module, and convert the second TTL signal into a second LVDS signal;

[0013] The second transceiver module is used to receive the AUX reply signal sent by the Sink end and convert the AUX reply signal into a second TTL signal; it is also used to receive the first TTL signal sent by the first transceiver module and convert the first TTL signal into a first LVDS signal.

[0014] Furthermore, the first transceiver module includes: a resistor R03, a resistor R04, a capacitor C01, a capacitor C02 and a first converter chip; the first converter chip is an LVDS and TTL signal converter chip with controllable transceiver function;

[0015] The resistor R03 is a pull-down resistor for the AUX negative electrode of the first transceiver module; the resistor R04 is a 3.3V pull-up resistor for the AUX positive electrode of the first transceiver module; the capacitor C01 is a negative electrode DC blocking capacitor for the AUX channel of the first transceiver module; the capacitor C02 is a positive electrode DC blocking capacitor for the AUX channel of the first transceiver module;

[0016] The first end of the capacitor C01 is connected to the B-end pin of the first converter chip, and the second end is connected to the first end of the resistor R03;

[0017] The first end of the capacitor C02 is connected to the A-end pin of the first converter chip, and the second end is connected to the first end of the resistor R04.

[0018] Furthermore, the first transceiver module further includes: a resistor R01 and a resistor R02;

[0019] The first end of the resistor R01 is respectively connected to the A-end pin of the first converter chip and the first end of the capacitor C02, and the second end is connected to the first end of the resistor R02;

[0020] The second end of the resistor R02 is connected to the B-end pin of the first converter chip and the first end of the capacitor C01 respectively; a first TX-ADJ voltage adjustment terminal is provided on the common electrode of the resistor R01 and the resistor R02.

[0021] Furthermore, the first transceiver module further includes: a capacitor C03, a resistor R05, and a resistor R06;

[0022] A first end of the capacitor C03 is connected to the VCC pin of the first converter chip, and a second end is grounded;

[0023] The resistor R05 is a pull-up resistor for TTL input to 3.3V; the resistor R06 is a pull-up resistor for TTL output to 3.3V;

[0024] The first end of the resistor R05 is respectively connected to the DI pin of the first converter chip and the first TTL input terminal;

[0025] The first end of the resistor R06 is respectively connected to the RO pin of the first converter chip and the first TTL output end;

[0026] The GND pin of the first converter chip is grounded; the DE pin of the first converter chip and The terminal pin is connected to the EN1 enable signal terminal.

[0027] Furthermore, the second transceiver module includes: a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a second converter chip; the second converter chip is an LVDS and TTL signal converter chip with controllable transceiver function;

[0028] The resistor R3 is a 3.3V pull-up resistor for the AUX negative electrode of the second transceiver module; the resistor R4 is a pull-down resistor for the AUX positive electrode of the second transceiver module; the capacitor C1 is a positive electrode DC blocking capacitor for the AUX channel of the second transceiver module; the capacitor C2 is a negative electrode DC blocking capacitor for the AUX channel of the second transceiver module;

[0029] The first end of the capacitor C1 is connected to the B-end pin of the second converter chip, and the second end is connected to the first end of the resistor R4;

[0030] The first end of the capacitor C2 is connected to the A-end pin of the second converter chip, and the second end is connected to the first end of the resistor R3.

[0031] Furthermore, the second transceiver module further includes: a resistor R1 and a resistor R2;

[0032] The first end of the resistor R1 is respectively connected to the B-end pin of the second converter chip and the first end of the capacitor C1, and the second end is connected to the first end of the resistor R2;

[0033] The second end of the resistor R2 is connected to the A-end pin of the second converter chip and the first end of the capacitor C2 respectively; a first TX-ADJ voltage adjustment terminal is provided on the common electrode of the resistor R1 and the resistor R2.

[0034] Furthermore, the second transceiver module further includes: a capacitor C3, a resistor R5, and a resistor R6;

[0035] A first end of the capacitor C3 is connected to the VCC pin of the second converter chip, and a second end is grounded;

[0036] The resistor R5 is a pull-up resistor for TTL output to 3.3V; the resistor R6 is a pull-up resistor for TTL input to 3.3V;

[0037] The first end of the resistor R5 is respectively connected to the RO pin of the second converter chip and the second TTL output end;

[0038] The first end of the resistor R6 is respectively connected to the DI pin of the second converter chip and the second TTL input terminal;

[0039] The GND pin of the second converter chip is grounded; the DE pin of the second converter chip and The terminal pin is connected to the EN2 enable signal terminal.

[0040] Furthermore, the resistance value of the resistor R03 and the resistor R04 is 1M; the capacitance value of the capacitor C01 and the capacitor C02 is 100nF; the resistance value of the resistor R01 and the resistor R02 is 49.9Ω;

[0041] The resistance values ​​of the resistor R3 and the resistor R4 are 100K; the capacitance values ​​of the capacitor C1 and the capacitor C2 are 100nF; and the resistance values ​​of the resistor R01 and the resistor R02 are 49.9Ω.

[0042] According to a second aspect of the present invention, the present invention provides an AUX channel signal conversion method of a DP interface of the device provided by the first aspect of the present invention, the method comprising:

[0043] When the AUX channel at the Source end initiates an AUX access signal, resistors R03 and R04 perform voltage bias matching processing on the AUX access signal and then send it to capacitors C01 and C02;

[0044] The AUX access signal passing through the capacitor C01 and the capacitor C02 is sent to the first converter chip after signal amplitude adjustment and matching processing using the resistor R01 and the resistor R02;

[0045] Using the first converter chip to convert the AUX access signal into a first TTL signal, and sending the first TTL signal to the second converter chip; using the second converter chip to convert the first TTL signal into a first LVDS signal;

[0046] Using resistors R1 and R2 to adjust the signal amplitude of the first LVDS signal to obtain a first LVDS signal with a signal amplitude matching the Sink end;

[0047] Removing an asymmetric DC bias voltage of the first LVDS signal by using the capacitor C1 and the capacitor C2;

[0048] The resistor R3 and the resistor R4 are used to restore the signal DC bias voltage matching the Sink end, and the processed first LVDS signal is sent to the AUX channel of the Sink end.

[0049] Furthermore, the method further comprises:

[0050] When the Sink end receives the access request from the Source end, the AUX channel of the Sink end initiates an AUX reply signal, and the resistors R3 and R4 perform voltage bias matching on the AUX reply signal and then send it to the capacitors C1 and C2;

[0051] The AUX reply signal passing through the capacitor C1 and the capacitor C2 is sent to the second converter chip after signal amplitude adjustment and matching processing is performed by the resistor R1 and the resistor R2;

[0052] Using the second converter chip to convert the AUX reply signal into a second TTL signal, and sending the second TTL signal to the first converter chip; using the first converter chip to convert the second TTL signal into a second LVDS signal;

[0053] Using the resistor R01 and the resistor R02 to adjust the signal amplitude of the second LVDS signal to obtain a second LVDS signal with a signal amplitude matching the Source end;

[0054] Removing an asymmetric DC bias voltage of the second LVDS signal by using the capacitor C01 and the capacitor C02;

[0055] The resistor R03 and the resistor R04 are used to restore the signal DC bias voltage matching the Source end, and the processed second LVDS signal is sent to the AUX channel of the Source end.

[0056] The present invention provides an AUX channel signal conversion device and conversion method of a DP interface, the device includes a first transceiver module and a second transceiver module; the first end of the first transceiver module is connected to the Source end of the AUX channel; the second end of the first transceiver module is connected to the first end of the second transceiver module; the second end of the second transceiver module is connected to the Sink end of the AUX channel signal; the first transceiver module is used to receive the AUX access signal initiated by the Source end, and convert the AUX access signal into a first TTL signal; it is also used to receive the second TTL signal sent by the second transceiver module, and convert the second TTL signal into a second LVDS signal; the second transceiver module is used to receive the AUX reply signal sent by the Sink end, and convert the AUX reply signal into a second TTL signal; it is also used to receive the first TTL signal sent by the first transceiver module, and convert the first TTL signal into a first LVDS signal. The present invention converts the AUX channel of the differential bidirectional half-duplex transmission mode into a bidirectional TTL mode, so that the AUX channel can be directly connected to the serial-to-parallel conversion circuit without the intervention of the FPGA chip, which provides a simpler implementation method for the optical communication extension, signal recovery, and long-distance transmission of the DP interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0058] Figure 1 It is a structural schematic diagram of the AUX channel circuit principle in the DP interface and the connection with the transmission cable in the prior art;

[0059] Figure 2 A schematic diagram of the structure of an AUX channel signal conversion device of a DP interface proposed in one embodiment of the present invention;

[0060] Figure 3 This is a schematic diagram of the structure of an AUX channel signal conversion device of a DP interface proposed in another embodiment of the present invention. DETAILED DESCRIPTION

[0061] To make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described in detail below. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other implementation methods obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0062] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0063] In order to enhance the understanding of the technical solution of the present invention, before the technical solution of the present invention is described in detail, the present invention provides the circuit principle of the AUX channel in the DP interface in the prior art and the connection relationship between the transmission cable, such as Figure 1 As shown. Figure 1 It can be seen that the data communication direction in the AUX channel is bidirectional, that is, the Source end accesses the Sink end, and the Sink end returns to the Source end.

[0064] The embodiment of the present invention provides an AUX channel signal conversion device of a DP interface, such as Figure 2 As shown, it includes a first transceiver module and a second transceiver module.

[0065] Among them, the first end of the first transceiver module is connected to the Source end of the AUX channel; the second end of the first transceiver module is connected to the first end of the second transceiver module; the second end of the second transceiver module is connected to the Sink end of the AUX channel signal.

[0066] In the embodiment of the present invention, the first transceiver module is used to receive the AUX access signal initiated by the Source end, and convert the AUX access signal into a first TTL signal; the second transceiver module is used to receive the first TTL signal sent by the first transceiver module, and convert the first TTL signal into a first LVDS signal. The second transceiver module is used to receive the AUX reply signal sent by the Sink end, and convert the AUX reply signal into a second TTL signal; the first transceiver module is also used to receive the second TTL signal sent by the second transceiver module, and convert the second TTL signal into a second LVDS signal.

[0067] It should be noted that the TTL signal and LVDS signal in the embodiment of the present invention are essentially AUX signals in TTL mode and AUX signals in LVDS mode. For the sake of simplicity, TTL signal and LVDS signal are still used as references in the following. In addition, the first LVDS signal and the second LVDS signal obtained after signal conversion are not matched with the AUX channel. Therefore, the first transceiver module and the second transceiver module in the embodiment of the present invention are also respectively provided with a signal matching device and a signal amplitude modulation device to convert the LVDS signal into a transmission signal that matches the Source end and the Sink end.

[0068] Furthermore, if Figure 3 , which is a component schematic diagram of the AUX channel signal conversion device proposed in an embodiment of the present invention.

[0069] based on Figure 3 The first transceiver module in the embodiment of the present invention may also include a resistor R03, a resistor R04, a capacitor C01, a capacitor C02 and a first converter chip; the first converter chip is an LVDS and TTL signal converter chip with controllable transceiver function. The first converter chip is used to convert the received AUX access signal into a first TTL signal, and also to convert the second TTL signal returned by the Sink end into a second LVDS signal that does not match the AUX channel.

[0070] Resistor R03 is a pull-down resistor for the AUX negative electrode of the first transceiver module; resistor R04 is a 3.3V pull-up resistor for the AUX positive electrode of the first transceiver module; capacitor C01 is a negative DC-isolating capacitor for the AUX channel of the first transceiver module; capacitor C02 is a positive DC-isolating capacitor for the AUX channel of the first transceiver module; the first end of capacitor C01 is connected to the B-end pin of the first converter chip, and the second end is connected to the first end of resistor R03; the first end of capacitor C02 is connected to the A-end pin of the first converter chip, and the second end is connected to the first end of resistor R04.

[0071] Preferably, the resistance values ​​of resistors R03 and R04 are both 1M, which are used to simulate the pull-up and pull-down resistors of the Sink terminal so that the signal bias voltage is relatively matched with the actual application. Preferably, the capacitance values ​​of capacitors C01 and C02 are both 100nF.

[0072] Furthermore, the first transceiver module in the embodiment of the present invention may also include a resistor R01 and a resistor R02; the first end of the resistor R01 is respectively connected to the A-end pin of the first converter chip and the first end of the capacitor C02, and the second end is connected to the first end of the resistor R02; the second end of the resistor R02 is respectively connected to the B-end pin of the first converter chip and the first end of the capacitor C01; and a first TX-ADJ voltage adjustment terminal is arranged on the common electrode of the resistor R01 and the resistor R02.

[0073] Preferably, the resistance values ​​of resistors R01 and R02 are both 49.9Ω. By adjusting the amplitude of the TX-ADJ voltage connected to the common electrode of resistors R01 and R02, the amplitude of the AUX signal of the first transceiver module can be adjusted to match the amplitude in actual application.

[0074] In addition, the first transceiver module in the embodiment of the present invention may also include: a capacitor C03, a resistor R05, and a resistor R06; the first end of the capacitor C03 is connected to the VCC end pin of the first converter chip, and the second end is grounded; the resistor R05 is a TTL input to 3.3V pull-up resistor; the resistor R06 is a TTL output to 3.3V pull-up resistor; the first end of the resistor R05 is respectively connected to the DI end pin of the first converter chip and the first TTL input end; the first end of the resistor R06 is respectively connected to the RO end pin of the first converter chip and the first TTL output end; the GND end pin of the first converter chip is grounded; the DE end pin and The terminal pin is connected to the EN1 enable signal terminal.

[0075] based on Figure 3 The second transceiver module in the embodiment of the present invention may also include a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a second converter chip; the second converter chip is an LVDS and TTL signal converter chip with controllable transceiver function. The second converter chip is used to convert the received first TTL signal into a first LVDS signal that is not matched with the AUX channel, and is also used to convert the AUX reply signal returned by the Sink end into a second TTL signal.

[0076] Resistor R3 is a 3.3V pull-up resistor for the AUX negative electrode of the second transceiver module; resistor R4 is a pull-down resistor for the AUX positive electrode of the second transceiver module; capacitor C1 is a positive DC-isolating capacitor for the AUX channel of the second transceiver module; capacitor C2 is a negative DC-isolating capacitor for the AUX channel of the second transceiver module; the first end of capacitor C1 is connected to the B-end pin of the second converter chip, and the second end is connected to the first end of resistor R4; the first end of capacitor C2 is connected to the A-end pin of the second converter chip, and the second end is connected to the first end of resistor R3.

[0077] Preferably, the resistance values ​​of resistors R3 and R4 are both 100K, which are used to simulate the pull-up and pull-down resistors at the Source end, so that the signal bias voltage is relatively matched with the actual application. Preferably, the capacitance values ​​of capacitors C1 and C2 are both 100nF.

[0078] Furthermore, the second transceiver module in the embodiment of the present invention may also include a resistor R1 and a resistor R2; the first end of the resistor R1 is respectively connected to the B-end pin of the second converter chip and the first end of the capacitor C1, and the second end is connected to the first end of the resistor R2; the second end of the resistor R2 is respectively connected to the A-end pin of the second converter chip and the first end of the capacitor C2; and a first TX-ADJ voltage adjustment terminal is arranged on the common electrode of the resistor R1 and the resistor R2.

[0079] Preferably, the resistance values ​​of resistors R1 and R2 are both 49.9Ω. By adjusting the amplitude of the TX-ADJ voltage connected to the common electrode of resistors R1 and R2, the amplitude of the AUX signal of the second transceiver module can be adjusted to match the amplitude in actual application.

[0080] In addition, the second transceiver module in the embodiment of the present invention may also include: a capacitor C3, a resistor R5, and a resistor R6; the first end of the capacitor C3 is connected to the VCC terminal pin of the second converter chip, and the second end is grounded; the resistor R5 is a TTL output to 3.3V pull-up resistor; the resistor R6 is a TTL input to 3.3V pull-up resistor; the first end of the resistor R5 is respectively connected to the RO terminal pin of the second converter chip and the second TTL output terminal; the first end of the resistor R6 is respectively connected to the DI terminal pin and the second TTL input terminal of the second converter chip; the GND terminal pin of the second converter chip is grounded; the DE terminal pin and The terminal pin is connected to the EN2 enable signal terminal.

[0081] Below, based on Figure 3 The AUX channel signal conversion device of the DP interface shown in the figure, the working principle of the conversion device in the example application is described in detail in the embodiment of the present invention:

[0082] It can be understood that in a conventional DP interface transmission application, the Source end AUX+, AUX- are respectively connected to AUX0+, AUX0- of the first transceiver module of the conversion device; the Sink end AUX+, AUX- are respectively connected to AUX1+, AUX1- of the second transceiver module of the conversion device.

[0083] When the AUX channel at the Source end initiates an AUX access signal, resistors R03 and R04 (pull-up and pull-down resistors) perform voltage bias matching processing on the AUX access signal and then send it to the DC-isolating capacitors C01 and C02; the AUX access signal passing through the DC-isolating capacitors C01 and C02 is subjected to signal amplitude adjustment and matching processing by resistors R01 and R02 and then sent to the first converter chip; the receiving enable of the first converter chip is turned on, the AUX access signal is converted into a first TTL signal by the first converter chip, and the first TTL signal is sent to the second converter chip. The first converter chip is used to convert the first TTL signal into a first LVDS signal; the first LVDS signal is adjusted by resistors R1 and R2 to obtain a first LVDS signal with a signal amplitude matching the Sink end; the asymmetric DC bias voltage of the first LVDS signal is removed by blocking capacitors C1 and C2; the DC bias voltage of the signal matching the Sink end is restored by resistors R3 and R4 (upper and lower pull-down resistors), and the processed first LVDS signal is sent to the AUX channel of the Sink end. After the AUX1+ and AUX1- signals after the above signal matching processing are connected to the DP interface of the Sink end, an AUX signal access process through the above conversion device is completed.

[0084] When the Sink end receives the access request from the Source end, the AUX channel of the Sink end initiates an AUX reply signal, and the resistor R3 and the resistor R3 (pull-up and pull-down resistors) perform voltage bias matching processing on the AUX reply signal, and then send it to the DC-isolating capacitor C1 and the DC-isolating capacitor C2; the AUX reply signal after the DC-isolating capacitor C1 and the DC-isolating capacitor C2 is sent to the second converter chip after signal amplitude adjustment matching processing using the resistor R1 and the resistor R2; the receiving enable of the second converter chip is turned on, and the AUX reply signal is converted into a second TTL signal using the second converter chip, and the second TTL signal is sent to The first converter chip; turn on the transmission enable of the first converter chip, and use the first converter chip to convert the second TTL signal into a second LVDS signal; use resistors R01 and R02 to adjust the signal amplitude of the second LVDS signal to obtain a second LVDS signal with a signal amplitude that matches the Source end; remove the asymmetric DC bias voltage of the second LVDS signal through DC blocking capacitors C01 and C02; use resistors R03 and R04 to restore the signal DC bias voltage that matches the Source end, and send the processed second LVDS signal to the AUX channel of the Source end. After the AUX0+ and AUX0- signals after the above signal matching processing are connected to the DP interface of the Source end, an AUX signal recovery process through the above conversion device is completed.

[0085] In summary, the present invention converts the AUX channel of the differential bidirectional half-duplex transmission mode into a bidirectional TTL mode, so that the AUX channel can be directly connected to the serial-to-parallel conversion circuit without the intervention of an FPGA chip, providing a simpler implementation method for optical communication extension, signal recovery, and long-distance transmission of the DP interface.

[0086] It can be understood that the same or similar parts of the above embodiments can be referenced to each other, and the contents not described in detail in some embodiments can refer to the same or similar contents in other embodiments.

[0087] It should be noted that, in the description of the present invention, the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, the meaning of "plurality" refers to at least two.

[0088] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0089] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A DP interface AUX channel signal conversion device, characterized in that: The device comprises a first transceiver module and a second transceiver module; The first end of the first transceiver module is connected to the Source end of the AUX channel; The second end of the first transceiver module is connected to the first end of the second transceiver module; The second end of the second transceiver module is connected to the Sink end of the AUX channel signal; The first transceiver module is used to receive the AUX access signal initiated by the Source end, and convert the AUX access signal into a first TTL signal; and is also used to receive the second TTL signal sent by the second transceiver module, and convert the second TTL signal into a second LVDS signal; The second transceiver module is used to receive the AUX reply signal sent by the Sink end, and convert the AUX reply signal into a second TTL signal; it is also used to receive the first TTL signal sent by the first transceiver module, and convert the first TTL signal into a first LVDS signal; The first transceiver module includes: a resistor R03, a resistor R04, a capacitor C01, a capacitor C02 and a first converter chip; the first converter chip is an LVDS and TTL signal converter chip with controllable transceiver function; The second transceiver module includes: a resistor R3, a resistor R4, a capacitor C1, a capacitor C2 and a second converter chip; the second converter chip is an LVDS and TTL signal converter chip with controllable transceiver function.

2. The device according to claim 1, characterized in that The resistor R03 is a pull-down resistor for the AUX negative electrode of the first transceiver module; the resistor R04 is a 3.3V pull-up resistor for the AUX positive electrode of the first transceiver module; the capacitor C01 is a negative electrode DC blocking capacitor for the AUX channel of the first transceiver module; the capacitor C02 is a positive electrode DC blocking capacitor for the AUX channel of the first transceiver module; The first end of the capacitor C01 is connected to the B-end pin of the first converter chip, and the second end is connected to the first end of the resistor R03; The first end of the capacitor C02 is connected to the A-end pin of the first converter chip, and the second end is connected to the first end of the resistor R04.

3. The device according to claim 2, characterized in that The first transceiver module further includes: a resistor R01 and a resistor R02; The first end of the resistor R01 is respectively connected to the A-end pin of the first converter chip and the first end of the capacitor C02, and the second end is connected to the first end of the resistor R02; The second end of the resistor R02 is connected to the B-end pin of the first converter chip and the first end of the capacitor C01 respectively; a first TX-ADJ voltage adjustment terminal is provided on the common electrode of the resistor R01 and the resistor R02.

4. The device according to claim 3, characterized in that The first transceiver module further includes: a capacitor C03, a resistor R05, and a resistor R06; A first end of the capacitor C03 is connected to the VCC pin of the first converter chip, and a second end is grounded; The resistor R05 is a pull-up resistor for TTL input to 3.3V; the resistor R06 is a pull-up resistor for TTL output to 3.3V; The first end of the resistor R05 is respectively connected to the DI pin of the first converter chip and the first TTL input terminal; The first end of the resistor R06 is respectively connected to the RO pin of the first converter chip and the first TTL output end; The GND pin of the first converter chip is grounded; the DE pin of the first converter chip and The terminal pin is connected to the EN1 enable signal terminal.

5. The device according to claim 1, characterized in that The resistor R3 is a 3.3V pull-up resistor for the AUX negative electrode of the second transceiver module; the resistor R4 is a pull-down resistor for the AUX positive electrode of the second transceiver module; the capacitor C1 is a positive electrode DC blocking capacitor for the AUX channel of the second transceiver module; the capacitor C2 is a negative electrode DC blocking capacitor for the AUX channel of the second transceiver module; The first end of the capacitor C1 is connected to the B-end pin of the second converter chip, and the second end is connected to the first end of the resistor R4; The first end of the capacitor C2 is connected to the A-end pin of the second converter chip, and the second end is connected to the first end of the resistor R3.

6. The device according to claim 5, characterized in that The second transceiver module further includes: a resistor R1 and a resistor R2; The first end of the resistor R1 is respectively connected to the B-end pin of the second converter chip and the first end of the capacitor C1, and the second end is connected to the first end of the resistor R2; The second end of the resistor R2 is connected to the A-end pin of the second converter chip and the first end of the capacitor C2 respectively; a first TX-ADJ voltage adjustment terminal is provided on the common electrode of the resistor R1 and the resistor R2.

7. The device according to claim 6, characterized in that The second transceiver module further includes: a capacitor C3, a resistor R5, and a resistor R6; A first end of the capacitor C3 is connected to the VCC pin of the second converter chip, and a second end is grounded; The resistor R5 is a pull-up resistor for TTL output to 3.3V; the resistor R6 is a pull-up resistor for TTL input to 3.3V; The first end of the resistor R5 is respectively connected to the RO pin of the second converter chip and the second TTL output end; The first end of the resistor R6 is respectively connected to the DI pin of the second converter chip and the second TTL input terminal; The GND pin of the second converter chip is grounded; the DE pin of the second converter chip and The terminal pin is connected to the EN2 enable signal terminal.

8. The device according to claim 3, characterized in that The resistance value of the resistor R03 and the resistor R04 is 1M; the capacitance value of the capacitor C01 and the capacitor C02 is 100nF; the resistance value of the resistor R01 and the resistor R02 is 49.9Ω; The resistance value of the resistor R3 and the resistor R4 is 100K; the capacitance value of the capacitor C1 and the capacitor C2 is 100nF; the resistance value of the resistor R1 and the resistor R2 is 49.9Ω.

9. A method for converting an AUX channel signal of a DP interface of the device according to claim 8, characterized in that: The method comprises: When the AUX channel at the Source end initiates an AUX access signal, resistors R03 and R04 perform voltage bias matching processing on the AUX access signal and then send it to capacitors C01 and C02; The AUX access signal passing through the capacitor C01 and the capacitor C02 is sent to the first converter chip after signal amplitude adjustment and matching processing using the resistor R01 and the resistor R02; Using the first converter chip to convert the AUX access signal into a first TTL signal, and sending the first TTL signal to the second converter chip; using the second converter chip to convert the first TTL signal into a first LVDS signal; Using resistors R1 and R2 to adjust the signal amplitude of the first LVDS signal to obtain a first LVDS signal with a signal amplitude matching the Sink end; Removing an asymmetric DC bias voltage of the first LVDS signal by using the capacitor C1 and the capacitor C2; The resistor R3 and the resistor R4 are used to restore the signal DC bias voltage matching the Sink end, and the processed first LVDS signal is sent to the AUX channel of the Sink end.

10. The method according to claim 9, characterized in that The method further comprises: When the Sink end receives the access request from the Source end, the AUX channel of the Sink end initiates an AUX reply signal, and the resistors R3 and R4 perform voltage bias matching on the AUX reply signal and then send it to the capacitors C1 and C2; The AUX reply signal passing through the capacitor C1 and the capacitor C2 is sent to the second converter chip after signal amplitude adjustment and matching processing is performed by the resistor R1 and the resistor R2; Using the second converter chip to convert the AUX reply signal into a second TTL signal, and sending the second TTL signal to the first converter chip; using the first converter chip to convert the second TTL signal into a second LVDS signal; Using the resistor R01 and the resistor R02 to adjust the signal amplitude of the second LVDS signal to obtain a second LVDS signal with a signal amplitude matching the Source end; Removing an asymmetric DC bias voltage of the second LVDS signal by using the capacitor C01 and the capacitor C02; The resistor R03 and the resistor R04 are used to restore the signal DC bias voltage matching the Source end, and the processed second LVDS signal is sent to the AUX channel of the Source end.

Images