A method of programming a non-volatile memory

Abstract

The application discloses a programming method of a non-volatile memory, which comprises at least one memory cell, the memory cell comprises adjacent P-well and N-well in a deep N-well, a first PMOS transistor and an NMOS capacitor in the N-well and the P-well respectively, and a floating gate covering the PMOS transistor and the NMOS capacitor; wherein the first PMOS transistor in the memory cell is programmed by band-to-band tunneling. The programming method of the application does not need a high driving charge pump, and is more competitive in the application of low-power and small-capacity memories.

Description

TECHNICAL FIELD

[0001] The present invention relates to a programming method of non-volatile memory, and more particularly to a band-to-band tunneling programming method of non-volatile memory. BACKGROUND

[0002] Non-volatile memory contains a plurality of memory cells arranged in rows and columns. The memory cells generally contain PMOS and / or NMOS transistors, and some contain MOS coupling capacitors.

[0003] Currently, many programming methods of non-volatile memory are: PMOS or NMOS transistors in the memory cells use channel hot electron tunneling to inject negative charges into the floating gate of the transistors. The advantage of this programming method is: it can be applied to a larger programming voltage range, as long as the voltage difference between the source and the drain and the gate and the drain of the MOS transistor device meets the opening condition and enters the saturation state, programming can be achieved. In addition, this method is suitable for a variety of transistor devices prepared by different process platforms. The disadvantage of this programming method is that a high drive capability charge pump is required, and the programming power consumption is high; and the area of the high drive charge pump is large, which is not conducive to reducing the size of the memory.

[0004] In the channel hot electron tunneling programming method, the positive and negative voltages required for memory programming are usually generated by a Dickson charge pump circuit. In the programming of channel hot hole-induced hot electron injection into the floating gate of the transistor in the memory cell, it is required to form a high lateral electric field in the channel to accelerate the carriers to generate the required saturated hole current for programming. The high lateral electric field in the channel and the large channel current require high driving capability of the charge pump positive and negative voltage, and the power consumption is large.

[0005] The charge pump is a voltage multiplier circuit that uses MOS tube capacitors in multiple stages in series and parallel to generate the required voltage and driving capability. A high drive charge pump requires more and larger MOS tubes in parallel, and the area is large. The area of the charge pump in the memory is usually large, for example, in a single polysilicon PMOS memory, especially in a small capacity (such as 256 x 8 bits) memory, the area can exceed 50%. Therefore, a high drive charge pump will hinder the reduction of the size of the memory.

[0006] Therefore, there is a need in the industry for a new programming method that can further reduce power consumption and facilitate the reduction of the area of the memory. SUMMARY

[0007] The present invention relates to a programming method for a non-volatile memory. The memory comprises at least one non-volatile memory cell, which is constructed on a P-type substrate, wherein each non-volatile memory cell comprises: a deep N-well, which is located in the P-type substrate, wherein a P-well and an N-well are located in the deep N-well; a first PMOS transistor, which is located in the N-well; an NMOS capacitor, which is located in the P-well, and comprises an N+ coupling region, which is located in the P-well; and a floating gate, which covers the PMOS transistor and the NMOS capacitor; and the programming method is to program the first PMOS transistor in the non-volatile memory cell by band-to-band tunneling, which comprises the following steps: (a) making the potential of the N-well greater than the potential of an electrode of the first PMOS transistor, so that a reverse bias voltage is formed on the PN junction at the interface between the N-well and the electrode, which makes the electrons of the PN junction tend to concentrate on the side of the PN junction close to the N-well; (b) making the potential on the floating gate of the first PMOS transistor greater than the potential of the above-mentioned electrode, and the potential difference between the two can form a strong electric field with an electric field strength greater than 8 MV / cm between the floating gate and the electrode; and (c) under the action of the above-mentioned strong electric field, the electrons on the side of the PN junction at the interface between the N-well and the electrode close to the N-well are injected into the floating gate of the first PMOS transistor to realize programming.

[0008] In a preferred embodiment, the potential difference between the N-well and the electrode is less than the avalanche breakdown voltage of the PN junction at the interface between the two, and more preferably, the potential difference is 0.1-1.0 V less than the avalanche breakdown voltage of the PN junction at the interface between the two.

[0009] In another preferred embodiment, the potential on the floating gate of the first PMOS transistor is coupled by the potential applied to the N+ coupling region of the NMOS capacitor, and the potential applied to the N+ coupling region is less than or equal to the potential of the N-well. More preferably, the potential applied to the N+ coupling region is equal to the potential of the N-well.

[0010] In still another preferred embodiment, the electrode of the first PMOS transistor involved in programming is the source electrode of the transistor, and the potential during programming is 0 V; and the other electrode of the first PMOS transistor, i.e. the drain electrode, is in a suspended state during programming.

[0011] In still another preferred embodiment, the capacitance of the NMOS capacitor is greater than the gate capacitance of the PMOS.

[0012] In yet another preferred embodiment, the non-volatile memory cell further comprises a second PMOS transistor located in the N-well, wherein the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor, and the drain of the second PMOS transistor does not participate in programming during programming. More preferably, the drain of the second PMOS transistor is in a floating state, or the channel of the second PMOS transistor is not conductive during programming. Still more preferably, the drain of the second PMOS transistor is in a floating state, and the gate of the second PMOS transistor has the same potential as the N-well during programming.

[0013] In yet another preferred embodiment, the floating gate in the memory cell is a single layer of polysilicon.

[0014] In yet another preferred embodiment, the non-volatile memory is electrically programmable and erasable.

[0015] In the prior art, when programming is performed using the channel hot electron tunneling method, a charge pump with high positive and negative voltage driving capability is required to achieve a high lateral electric field in the channel. Moreover, the working current in the channel is large, typically > 5 mA, and the programming power consumption is high. In the present application, when programming is performed using the band-to-band tunneling method, the voltage requirement is simple, and negative voltage is not required, so the driving capability requirement for the charge pump is low. Moreover, the programming current is extremely small, typically < 100 µA, reaching the nA level / bit. The programming power consumption of the memory is greatly reduced.

[0016] The programming method of the present application does not require a high driving charge pump, and compared with the prior art channel hot electron tunneling programming method, the area of the charge pump is greatly reduced. For example, for a 0.18 µm process platform 5 V transistor device, when programming is performed using the band-to-band tunneling method of the present application, the area of the required charge pump is only 0.03 mm 2 , while when programming is performed using the channel hot electron tunneling method, the area of the required charge pump is as high as 0.15 mm 2 . The programming method of the present application greatly reduces the area occupied by the charge pump in the memory, which is very advantageous for reducing the size of the memory.

[0017] In addition, the programming method of the present application does not require a high driving charge pump, which is easy for memory design, and is more competitive in the application of low power consumption and small capacity memories. BRIEF DESCRIPTION OF DRAWINGS

[0018] The embodiments of the application are illustrated by way of example in the accompanying drawings in which like reference numerals indicate similar elements, and this application is not limited to the examples of the pictures shown in the drawings.

[0019] Figures la-1cA top view, a cross-sectional view along the section line A-A, and a cross-sectional view along the section line B-B of one memory cell of a non-volatile memory programmed by the inventive programming method are shown.

[0020] Figure 2 A relationship between a reverse bias voltage and an output current on a PN junction between a terminal of a first PMOS transistor and an N-well of the memory cell shown in Fig. 1 in one embodiment is shown.

[0021] Figure 3a A relationship between a program voltage (VPP) and a read-out current after programming for different programming times (10 μs / 100 μs / 1 ms / 10 ms) of the first PMOS transistor of the memory cell shown in Fig. 1 in one embodiment is shown.

[0022] Figure 3b and 3c A relationship between a control gate potential and a read-out current in a read-out operation after programming for different time periods at a program voltage (VPP) of 9.5 V and 10.5 V of the first PMOS transistor of the memory cell shown in Fig. 1 is shown.

[0023] Figure 3d A relationship between a control gate potential and a read-out current in a read-out operation after 1 / 10 / 100 / 1000 / 10K program and erase operations of the first PMOS transistor of the memory cell shown in Fig. 1 is shown.

[0024] Figure 4 A 2 row x 2 column arranged array of the memory cell shown in Fig. 1 is shown.

[0025] Figure 5 A Figure 4 Bias signals connected to the array during different operations of the array are shown.

[0026] Figure 6 A top view of one memory cell of another non-volatile memory programmed by the inventive programming method is shown.

[0027] Figure 7 A Figure 6 A cross-sectional view along the section line A-A of the memory cell shown is shown.

[0028] Figure 8 A Figure 6 A cross-sectional view along the section line B-B of the memory cell shown is shown.

[0029] Figure 9 A Figure 6 A cross-sectional view along the section line C-C of the memory cell shown is shown.

[0030] Figure 10An array is shown Figure 6 A 2 row by 2 column arrangement of memory cells is shown.

[0031] Figure 11 An array is shown Figure 10 Bias signals connected to the array during different operations of the array are shown.

[0032] Other features of embodiments of the invention can be apparent from the accompanying drawings and from the detailed description which follows. DETAILED DESCRIPTION

[0033] The non-volatile memory described herein includes one-time programmable memory and multi-time programmable erasable memory, preferably electrically programmable erasable non-volatile memory.

[0034] The memory described herein can be fabricated using processes common in silicon chip foundries with deep sub-micron technology, for example, 40 nm to 350 nm process platforms, preferably from a BCD (bipolar, CMOS, and DMOS devices on the same chip) process platform.

[0035] The memory cell of the memory described herein has a deep N-well to isolate the memory cell from the substrate. A first PMOS transistor and an NMOS capacitor in the memory cell are located in adjacent N-well and P-well in the deep N-well. The PMOS transistor includes a PMOS gate oxide and a gate electrode overlying the PMOS gate oxide; the NMOS capacitor includes an N+ coupling region in the P-well, a gate oxide, and a gate electrode overlying the gate oxide. The N+ coupling region is formed by an N+ source / drain ion implant. The gate electrode of the NMOS capacitor extends and merges with the gate of the PMOS to form a floating gate of the memory cell. The floating gate overlies the PMOS transistor and the NMOS capacitor, but does not cover the N+ coupling region of the NMOS capacitor. The floating gate is preferably a single layer of polysilicon gate. The N+ coupling region connects a control word line (WL) to a control gate of the memory cell. The control gate is formed by a channel region of the NMOS capacitor. Application of a potential to the N+ coupling region is coupled through the channel region of the NMOS capacitor to the floating gate. Thus, the coupling capacitor structure is composed of the floating gate with partial overlap of the active region in the P-well, the underlying gate oxide, and the NMOS channel. To improve the efficiency of the coupling gate, the coupling capacitor is made much larger than the capacitance of the PMOS gate.

[0036] The memory cell of the present application can also include a second PMOS transistor in series with the first PMOS transistor and located in the N-well. The second PMOS transistor also includes a gate oxide and a gate electrode overlying the gate oxide, the gate electrode preferably being a single layer of polysilicon gate electrode connected to an access word line (WL) signal. The N+ coupling region of the NMOS capacitor connects a control gate signal (CG) to the control gate of the memory cell, the control gate being formed by the channel region of the NMOS capacitor. The second PMOS transistor acts as a pass transistor for the programmable first PMOS transistor and does not participate in the programming of the memory cell.

[0037] The programming of the memory cell occurs in the first PMOS transistor and is by band-to-band tunneling. One terminal (e.g., the source) of the first PMOS transistor participates in the programming. The other terminal (e.g., the drain) can or can not participate in the programming. Preferably, the other terminal does not participate in the programming, and more preferably, the terminal that does not participate in the programming is in a floating state during the programming.

[0038] At the beginning of the programming, for the terminal of the first PMOS transistor that participates in the programming, first perform step (a): make the potential of the N-well greater than the potential of the terminal, and the potential difference between the two forms a reverse bias voltage at the PN junction at the interface between the N-well and the terminal, which causes the electrons in the PN junction to concentrate on the side of the PN junction closer to the N-well.

[0039] The greater the potential difference between the N-well and the terminal of the first PMOS transistor that participates in the programming, the more electrons in the PN junction are concentrated on the side closer to the N-well. The upper limit of the potential difference is less than the avalanche breakdown voltage of the PN junction at the interface between the N-well and the terminal of the first PMOS transistor that participates in the programming. Preferably, the potential difference is 0.1-1.0 V less than the avalanche breakdown voltage of the PN junction at the interface between the N-well and the terminal of the first PMOS transistor that participates in the programming, more preferably 0.1-0.7 V, and even more preferably 0.1-0.5 V. The potential difference can be 5.0-10.5 V, preferably 7.0-10.5 V, and more preferably 9.0-10.5 V. When the potential difference is close to the avalanche breakdown voltage of the PN junction, the electrons on the side of the PN junction closer to the N-well are more easily injected into the floating gate under the action of the electric field, resulting in good programming, short programming time, good convergence of the programming, and high programming efficiency.

[0040] The design of the memory circuit in the prior art can ensure that the above-mentioned potential difference is close to but does not exceed the avalanche breakdown voltage of the PN junction, so that successful programming can be achieved while avoiding irreversible damage to the PN junction. In addition, the inventors have found that when the programming is performed with the above-mentioned potential difference less than the avalanche breakdown voltage of the PN junction, the number of programming times of the memory can reach 10,000 times, which is sufficient to meet application requirements.

[0041] Then, steps (b) and (c) are performed in sequence to make the potential on the floating gate of the first PMOS transistor greater than the potential of the terminal of the first PMOS transistor involved in programming, and the potential difference between the two is capable of forming an electric field with an intensity greater than 8 MV / cm between the floating gate and the terminal. Such a strong electric field can cause band-to-band tunneling of the electrons near the N-well side of the PN junction to inject the floating gate to perform programming.

[0042] The electric field formed between the potential on the floating gate of the first PMOS transistor and the potential of the terminal involved in programming is preferably > 8 MV / cm. For example, the potential on the floating gate can be 6.5-10.5 V, more preferably 7.0-10.5 V, and even more preferably 9.0-10.5 V.

[0043] The potential on the floating gate of the first PMOS transistor is coupled through the channel of the NMOS capacitor from the potential applied to the N+ coupling region of the NMOS capacitor. In order to improve the coupling efficiency, the capacitance of the NMOS capacitor is much larger than that of the PMOS gate. The gate capacitance of the NMOS capacitor can be 1-10 times, preferably 1.5-7 times, and more preferably 2-5 times, the gate capacitance of the first PMOS transistor.

[0044] During programming, the potential applied to the N+ coupling region is preferably equal to or less than the potential of the N-well. This can avoid leakage between the P-well and the N-well. More preferably, the potential applied to the N+ coupling region is the same as the potential of the N-well.

[0045] Preferably, the terminal of the first PMOS transistor involved in programming has a potential of 0 V during programming, and the other terminal not involved in programming is in a floating state during programming. The terminal involved in programming can be referred to as the source, and the other terminal not involved in programming can be referred to as the drain.

[0046] In the programming method of the present application, steps (a) and (b) can be performed in sequence, in reverse order, or simultaneously. Regardless of the order of steps (a) and (b), step (c) is always performed after steps (a) and (b).

[0047] In the above non-volatile memory cell of the present application, a second PMOS transistor can also be included, which is located in the N-well and has one terminal coupled to the terminal of the first PMOS transistor not involved in programming (e.g., the drain) and the other terminal not involved in programming.

[0048] In the case where the source of the first PMOS transistor is involved in programming, the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor, and then the drain of the second PMOS transistor is not involved in programming, preferably in a floating state during programming, or the channel of the second PMOS transistor is not conductive during programming.

[0049] More preferably, during programming, the potential of the gate of the second PMOS transistor is the same as the potential of the N-well. This avoids the formation of electrical stress on the gate oxide of the second PMOS transistor, affecting the service life of the gate oxide and the transistor.

[0050] The first PMOS transistor and the second PMOS transistor can be the same or different, depending on the actual application. Preferably, they are the same.

[0051] In a more preferred embodiment, for the memory cell without the second PMOS transistor, during programming, the potential of the N-well is the same as the potential of the N+ coupling region, the potential of the end of the first PMOS transistor involved in programming is 0 V, and the end of the first PMOS transistor not involved in programming is in a suspended state; for the memory cell with the second PMOS transistor, during programming, the potential of the N-well, the potential of the N+ coupling region, and the potential of the gate of the second PMOS transistor are the same, the potential of the end of the first PMOS transistor involved in programming is 0 V, and the end of the second PMOS transistor not involved in programming is in a suspended state. In this case, the voltage requirement during programming is single, and the operation is very convenient.

[0052] The programming method of the non-volatile memory according to the present application will be further described in detail below in conjunction with specific embodiments. Although the following is described with reference to specific embodiments, it is obvious that various adjustments and changes can be made to these embodiments without departing from the spirit and broader scope of various embodiments of the present application. In addition, although specific voltage values are provided in the embodiments and the drawings, it should be understood that these values are not necessarily accurate values, but are used to express the general concept of the bias scheme.

[0053] The memory in the embodiments is an electrically programmable and erasable non-volatile memory, which is prepared by a 180 nm BCD process platform. The first and second PMOS transistors in the memory cell are the same, both of the transistors and the NMOS capacitor are 5 V devices, the gate oxide thickness is 120 angstroms, and the floating gate of the transistor is a single layer of polysilicon.

[0054] Figure la A top view of one non-volatile memory cell 100 in the memory in this embodiment is shown, Figures lb-1c Cross-sectional views of the memory cell along the cross-sectional lines A-A and B-B in Figure la are shown, respectively.

[0055] In this embodiment, the non-volatile memory cell 100 is constructed in a P-type silicon substrate 101. A deep N-well 104 is provided in the P-substrate 101 to electrically isolate the memory cell from the substrate. An N-well 102 and a P-well 103 are provided in close proximity to each other in the N-deep well 104. A first PMOS transistor 110 is provided in the N-well 102. The PMOS transistor 110 includes a P-type drain 112 and a source 111. The drain 112 includes a lightly doped region 112A and a heavily doped P+ contact region 112B. The source 111 includes a lightly doped region 111A and a heavily doped P+ contact region 111B.

[0056] The source 111 is connected to a common line (COM) and the drain 112 is connected to a bit line (BL). The transistor 110 is surrounded by a shallow trench which is filled with a thick field oxide 114. Between the source 111 and the drain 112 is a channel region 113. A gate oxide layer 115 overlies the channel 113 and has a thickness of 120 Angstroms. A conductive doped polysilicon gate is provided on top of the gate oxide 115 to form a floating gate 116 of the first PMOS transistor.

[0057] The floating gate 116 and the gate oxide 115 extend into the P-well 103 and partially overlap an active region 125 to form the top plate and dielectric of an NMOS capacitor 120. The floating gate 116 also partially overlaps a charge injection element 122 which is comprised of a lightly doped N region 122A and a heavily doped N+ region 122B. The floating gate 116 is surrounded by a sidewall spacer 117 which is typically formed of silicon nitride or silicon oxide.

[0058] The sidewall spacer 117 prevents N+ or P+ implants from entering the lightly doped N or P region when the N+ or P+ regions are formed. The charge injection element 122 is connected to a word line (WL) which is also connected to the P-well through a P+ contact region (not shown). During operation, when the potential of the floating gate 116 is less than the WL, the voltage difference is greater than the threshold voltage of the NMOS capacitor, and the P-well region 121 under the floating gate inverts, and an electron layer is formed in the region 121 by the electrons emitted from the injection element 122, thereby forming the bottom plate of the NMOS capacitor 120. The bottom plate 121 is connected to the WL through the injection element 122. An N+ coupling region connects the control word line (WL) to the control gate of the memory cell which is formed by the channel region of the NMOS capacitor. By applying a potential to the N+ coupling region, the potential can be coupled to the floating gate through the channel region of the NMOS capacitor.

[0059] All of the processing steps required to form the memory cell 100 are those used in the logic process to form other circuitry on the chip. No additional processing steps are required. The gate capacitance of the NMOS capacitor 120 is 3.4 times the gate capacitance of the first PMOS transistor 110.

[0060] When programming memory cell 100, source 111 of first PMOS transistor 110 participates in programming, while drain 112 does not participate and is in a floating state. The N-well and deep N-well are first driven to VPP, COM is set to 0V, BL is floated, and then WL is driven to VPP to begin programming. VPP is a positive value. Because COM is 0V, VPP can also be called the programming voltage.

[0061] The N-well potential is a positive value, VPP, and the potentials of the doped regions 111A and 111B of the source 111 of the first PMOS transistor are 0V. A reverse bias voltage, VPP, is applied to the PN junction between the N-well and the source doped region of the first PMOS transistor, causing electrons in the PN junction to tend to concentrate on the side of the PN junction near the N-well. Next, the floating gate 116 couples the potential VPP of the N+ coupling region of the NMOS capacitor to a positive potential 0.95 times greater than VPP. A strong electric field with an intensity greater than 8MV / cm is formed between the floating gate 116 and the doped region of the source 111 of the first PMOS transistor, causing electrons in the PN junction near the N-well to undergo band-to-band tunneling and transition to the floating gate, completing programming.

[0062] Figure 2 The figure shows the relationship between the reverse bias voltage on the PN junction between the source doping region and the N-well of the first PMOS transistor 110 in the memory cell 100 and its output current. In this figure, the horizontal axis is the source potential and the vertical axis is the output current (ampere). At this time, the N-well potential is 0V. Figure 2 As can be seen in the figure, when the reverse bias voltage of the PN junction is above 10.2V, its output current increases rapidly. At this time, a large number of electron-hole pairs are generated, and when the voltage exceeds about 10.6V, avalanche breakdown of the junction occurs. When programming is performed close to the breakdown voltage before avalanche breakdown, a large number of electrons will tend to concentrate on the side of the PN junction near the N well, which helps to improve programming efficiency, shorten programming time, and improve convergence. Therefore, the most preferred value for VPP is the bias voltage value of 10.05-10.5V before the PN junction avalanche breakdown occurs. When the programming voltage VPP is close to the PN junction avalanche breakdown (a large number of electron-hole pairs are generated), it will not affect the programming life of the memory. The inventors have experimentally proved that when programming is performed at a voltage close to the PN junction avalanche breakdown voltage, for example 10.5V, the service life of the memory can reach 10,000 times.

[0063] When VPP is set to 10.5 V, an electric field with a strength of 8.3 MV / cm is formed between the floating gate 116 and the doped region of the source 111 of the first PMOS transistor, which is greater than 8 MV / cm, and can achieve electron band-to-band tunneling to the floating gate.

[0064] During programming, electrons are injected into the floating gate of the memory cell, causing the threshold voltage of the first PMOS transistor to decrease, making the transistor channel more conductive and causing the read current to increase during a read operation.

[0065] In a read operation after programming, a potential is applied to the control gate to cause the difference between the floating gate potential of the first PMOS transistor and the N-well potential to be greater than the threshold voltage of the transistor, thereby causing the channel of the transistor to turn on and a potential difference to exist between the source and the drain of the transistor, forming a channel read current that flows from the bit line.

[0066] Figure 3a The first PMOS transistor 110 in the memory cell 100 is shown, at different programming times (10 µs / 100 µs / 1 ms / 10 ms), the relationship between the programming voltage (VPP) and the read current of the cell after programming. From Figure 3a It can be seen that when VPP≥9V, the programming effect is more obvious. When VPP is 9V and the programming time is 10ms, the channel read current after programming is >10µA, which is more obvious. When VPP increases in the range of 9-10V, the channel read current increases sharply and the programming speed is obviously accelerated; when VPP exceeds 10V, the channel read current after programming for 10µs reaches >20µA. At this time, the programming has tended to saturation, and the convergence is good, and further increasing the programming time or voltage does not obviously improve the programming effect.

[0067] Figure 3b and 3c The first PMOS transistor 110 in the memory cell 100 is shown, at different programming times, the relationship between the control gate potential and the read current in a read operation after programming with VPP of 9.5V and 10.5V, respectively. From Figure 3b and 3c It can be seen that when VPP is 9.5V, the convergence of the channel read current flowing from the bit line at different programming times is poor; when VPP is 10.5V, the convergence of the channel read current at different programming times is very good.

[0068] Figure 3d The first PMOS transistor 110 in the memory cell 100 is shown, at different programming times, the relationship between the control gate potential and the read current in a read operation after programming with VPP of 9.5V and 10.5V, respectively. From Figure 5 It can be seen that when VPP is 9.5V, the convergence of the channel read current flowing from the bit line at different programming times is poor; when VPP is 10.5V, the convergence of the channel read current at different programming times is very good. Figure 3d It can be seen that after 10K repeated programming and erasing, the difference (read window) between the programming and erasing currents is still greater than 20µA, meeting the circuit design requirement (the difference between the programming and erasing currents >=3µA).

[0069] In most applications, multiple non-volatile cells 100 can be placed together to form a memory array. For the purpose of illustration,Figure 4 The operation of a 2x2 memory array 250 is described and shown. The array contains 4 memory cells arranged in 2 rows and 2 columns. Arrays of different sizes can be formed by increasing and / or decreasing the number of rows and / or columns. Memory array 250 includes memory cells 200, 210, 220, and 230. Memory array 250 also includes NMOS capacitors 201, 211, 221, and 231, and first PMOS transistors 202, 212, 222, and 232.

[0070] In one embodiment, the WLs of memory cells 200 and 210 are connected to WL0, forming one memory row, and the WLs of memory cells 220 and 230 are connected to WL1, forming another memory row. The common lines (COM) and bit lines (BL) of cells 200 and 220 are connected to COM0 and BL0, respectively, forming one memory column. Similarly, the common lines (COM) and bit lines (BL) of cells 210 and 230 are connected to COM1 and BL1, respectively, forming another memory column. The memory array is built in a P-type substrate. The deep N-wells of the memory cells are merged together to form a single deep N-well (e.g., deep N-well 254). The N-wells and P-wells of the memory cells in each memory row are merged together. Thus, each memory row contains one N-well (e.g., NW 252A, NW 252B) and one P-well (e.g., PW 253A, PW 253B).

[0071] Each N-well is connected to a deep N-well, which is in turn connected to a DNW. The P-well of the "m" memory row is connected to word line WLm, where "m" represents the row number. By merging the wells in a row together, the memory cells in the array can be packed more tightly because the space between the wells is eliminated. The memory array is built in the same substrate as other logic circuits on the chip, which require the substrate to be grounded or at 0v.

[0072] Figure 5 The bias voltages for the above array in program and read modes are shown. Each memory cell in array 250 can be programmed or erased independently. Thus, memory array 250 can be used to form a large electrically programmable and erasable memory (EEPROM), which is different from a FLASH memory in which all cells in a page are erased together. Alternatively, memory array 250 can be used to form a FLASH memory by programming or erasing the cells in array 250 together.

[0073] The designated memory cell can be programmed individually. During programming, the electron band band-to-band tunneling injects into the floating gate of the selected cell, causing the threshold voltage of the first PMOS transistor in the memory cell to decrease, making it easier to turn on, and causing the read current during a read operation to increase.

[0074] For example, memory cell 200 can be programmed by driving WL0 to VPP, BL0 floating, COM0 at 0V. The potentials of the N-well and deep N-well are VPP. VPP is 10.5V. The programming of memory cell 200 is the same as that of memory cell 100 described above.

[0075] Memory cell 210 has COM1 floating, so in its first PMOS transistor, there is no reverse bias voltage across the PN junction between the N-well and the transistor source, and no electrons can tunnel through the PN junction, nor can a strong electric field be formed between the floating gate and the source to excite electrons to tunnel. Therefore, cell 210 cannot be programmed. Cell 220 has WL1 floating, and a strong electric field cannot be formed between the floating gate and the source of its first PMOS transistor to excite electrons to tunnel, so it cannot be programmed. Cell 230 has COM1, BL1, and WL1 all floating, and cannot be programmed.

[0076] During programming, the deep N-well is driven to VPP to ensure that all junctions in array 250 are reverse biased.

[0077] In a read operation, the data in a row of memory cells can be read out simultaneously. The PMOS transistors in programmed and unprogrammed cells have threshold voltages of approximately 0V and -1.5V, respectively. In one embodiment, the memory cells in row 0 are selected for a read operation, and cell 200 is in a programmed state, while the other cells are unprogrammed. As a result, all of the common lines (COM) are driven to 1.2V, all of the bit lines (BL) are precharged to 0V, and the N-well and deep N-well are driven to 1.5V. The unselected word lines are driven to 1.5V, but the selected word line WL0 is driven to 0V.

[0078] As a result, PMOS transistor 202 in cell 200 is turned on, pulling BL0 up to 1.2V, but PMOS transistor 212 in cell 210 remains off, and BL1 remains at 0V, because the negative threshold voltage of transistor 212 is lower than the floating gate bias. The high voltage in BL0 is then sensed by a sense amplifier and driven out as a data signal with a state of "1". Similarly, the low state of BL1 is sensed by another sense amplifier and driven out as another data signal with a state of "0". Note that the transistors of the cells in the unselected row are off, regardless of their programmed state, because of their high word line voltage. Therefore, they have no effect on the bit lines.

[0079] In the array, the designated memory cell can also be erased. Erasure can be performed in a conventional manner, such as Fowler-Nordheim tunneling. During the erase operation, electrons are removed from the floating gate of the selected cell, causing the threshold voltage of the PMOS transistor to increase, making it more difficult to turn on, and causing the read current during a read operation to decrease.

[0080] For example, memory cell 200 can be erased by driving WL0 to -5v, both BLO and COMO to 5v, and the potential of the N-well and deep N-well to 5v. Under this bias condition, the lower plate of NMOS capacitor 201 forms an inversion layer, and the floating gate is coupled to a potential of about -4.7v. In the case where the source and drain of the transistor are driven to 5v, an inversion layer is also formed in the channel region of PMOS transistor 202. The inversion channel connects the source and drain, which are at 5v. Thus, the total voltage applied to the gate oxide of PMOS transistor 202 is about 9.7v, which forms a high electric field sufficient to cause the electrons trapped in the floating gate to tunnel to the inversion channel, which is full of positive carriers. The high electric field can exceed about 10 MeV, and the tunneling mechanism is Fowler-Nordheim tunneling.

[0081] In this embodiment, WL0 and P-well 253B, which are shared by cells 200 and 210, can be driven to a negative potential that is less than the substrate bias (0v) because P-well 253B is isolated from the substrate by deep N-well 254. Deep N-well 254 is driven to 5v during erase.

[0082] Memory cell 210 also receives the word line voltage of -5v, but the source and drain of its PMOS transistor 212 receive a bias of 0v. As a result, the voltage across the gate oxide of transistor 212 is only 4.7v, which is not sufficient to trigger Fowler-Nordheim tunneling even though the channels of both read transistor 212 and NMOS capacitor 211 form inversion layers. Thus, memory cell 210 is not affected during erase.

[0083] In memory cell 220, the source and drain of transistor 222 are driven to 5v, but the word line connected to WL1 receives a bias of 0v. As a result, the voltage across the gate oxide of transistor 222 is only 4.7v. This electric field is not sufficient to trigger Fowler-Nordheim tunneling even though the channels of both read transistor 222 and NMOS capacitor 221 form inversion layers. Thus, memory cell 220 is not affected during erase.

[0084] In memory cell 230, the word line and the source and drain of transistor 232 are all biased to 0v. The electric field across the gate oxide of read transistor 232 is thus negligible, and the cell is not affected during erase.

[0085] The read operation after erasure is the same as the read operation after programming. In the read operation, the data in a row of memory cells can be read out simultaneously. The first PMOS transistor in the erased cell has a threshold voltage of approximately -1.5V.

[0086] In another embodiment, a second PMOS transistor 330 is added in series with the first PMOS transistor 310, such as Figure 6 As shown, another memory cell 300 is formed. The first PMOS transistor 310 is similar to the first PMOS transistor 110 of the nonvolatile memory cell 100 in FIG. 1 . Figure 6 3 shows a top view of a non-volatile memory cell 300 with a second PMOS transistor 330. According to various embodiments, Figure 6 The cross-sectional views along the section lines AA, BB, and CC are as follows: Figure 7 、 8 , and 9 as shown.

[0087] Nonvolatile memory cell 300 comprises an NMOS coupling capacitor 320, a first PMOS transistor 310, and a second PMOS transistor 330. First PMOS transistor 310 includes a P-type drain region 312, which comprises a lightly doped region 312A and a P+ contact region 312B. The drain P+ contact region 312B of transistor 310 is shared with the source P+ contact region of transistor 330, thereby connecting the two PMOS transistors in series. The source of transistor 310 is connected to a common line (COM). Cell 300 also includes a thick field oxide 314. A channel region 313 is located between the source and drain of transistor 310.

[0088] The bit line (BL) is connected to the drain of transistor 330. The charge injector 322 of NMOS coupling capacitor 320 is connected to a control gate signal CG, which controls the floating gate voltage during a store operation. Charge injector 322 includes a lightly doped N region 322A and a heavily doped N+ region 322B. The gate of transistor 330 is connected to a word line (WL). By controlling the gate voltage via WL, transistor 330 can be turned on or off, thereby connecting or disconnecting it from the bit line BL. The source of transistor 310 is connected to a common signal (COM), as in memory cell 100. Similar to memory cell 100, NMOS coupling capacitor 320 is located in P-well 303, while PMOS transistors 310 and 330 are located in N-well 302, adjacent to the P-well. Both wells are located in a deep N-well (DNW) 304, which is located in a P-type substrate 301.

[0089] The storage cell 300 is programmed in a similar manner as the storage cell 100. The source of the first PMOS transistor is involved in the programming, while the drain is not involved. In addition, the drain of the second PMOS transistor is floating, and this transistor is not involved in the programming. During programming, the potential of the N-well and the deep N-well are first driven to VPP, the COM is driven to OV, and the BL is floating. Then the CG and the WL are driven to VPP, and the programming is performed. VPP is 10.5V. The programming process and mechanism are the same as the storage cell 100.

[0090] Figure 10 A storage array 450 is shown, which includes four storage cells 300 arranged in two rows and two columns. Thus, the cells 420 and 430 form a storage row, and their WL and CG lines are connected to WLl and CGl, respectively. Similarly, the cells 400 and 410 form another storage row, and their WL and CG lines are connected to WL0 and CG0, respectively. The cells 400 and 420 form a column, and their common and bit lines are connected to COMO and BLO, respectively. The cells 410 and 430 form another column, and their common and bit lines are connected to COMl and BLl, respectively.

[0091] The storage array 450 is built in a P-type substrate. The deep N-wells of the storage cells are merged together to form a single deep N-well 304. The N-wells and P-wells of the storage cells in a storage row are merged together, respectively. Thus, each storage row contains an N-well (e.g., NW452A, NW452B) and a P-well (e.g., PW453A, PW453B).

[0092] Each N-well is connected to a deep N-well, which is in turn connected to a DNW 454. The P-well of the "m"th storage row is connected to the word line CGm, where "m" represents the row number. By merging the wells in a row together, the storage cells in the array can be packed more tightly, because the space between the wells is eliminated. The storage array is built in the same substrate as other logic circuits on the chip, which require the substrate to be grounded or at OV.

[0093] Figure 11 The bias voltages of the array 450 in the programming and readout modes are shown. Each storage cell in the array 450 can be erased or programmed independently. Thus, the storage array 450 can be used to form a large electrically programmable and erasable memory (EEPROM). The cells in the storage array 450 can also be erased or programmed together in blocks, similar to a FLASH memory.

[0094] A designated memory cell in array 450 can be programmed. During programming, electrons are injected into the floating gate of the selected cell, causing the threshold voltage of the sense transistor to decrease, making it easier to turn on, resulting in an increase in the sense current during a sense operation. During programming, the deep N-well is driven to VPP, ensuring that all PN junctions within the array are reverse biased.

[0095] Assuming that memory cell 400 in memory cell array 450 is selected, memory cell 400 is programmed by driving the N-well to VPP, COMO to OV, and driving CGO and WLO to VPP, and leaving BLO floating. The programming of memory cell 400 is identical to that of memory cell 300 described above.

[0096] COMI of memory cell 410 is floating, so that in its first PMOS transistor 412, there is no reverse bias voltage across the PN junction between the N-well and the transistor source, and no electrons can tunnel into the PN junction, nor can a strong electric field be created between the floating gate and the source to cause tunneling of the excited electrons, and thus, cell 410 cannot be programmed. CGI of cell 420 is OV, and the floating gate of its first PMOS transistor 422 cannot create a strong electric field between the floating gate and the source to cause tunneling of the excited electrons, and thus, cell 420 cannot be programmed. COMI of cell 430 is floating, and CGI is OV, and thus, cell 430 cannot be programmed.

[0097] After programming, data in a row of memory cells in array 450 can be sensed simultaneously. The PMOS sense transistors in programmed and unprogrammed cells have threshold voltages of approximately OV and -1.5V, respectively. In one embodiment, when cell 400 is in a programmed state, cell 410 is in an unprogrammed state, and row 0 is selected for a sense operation, the sense operation can be performed. Thus, all common lines (COM) are driven to 1.2V, all bit lines (BL) are precharged to OV, the coupled gate line (CGO) is driven to OV, the N-well and the DNW are driven to 1.5V. The unselected word lines are driven to 1.5V, but the selected word line WLO is driven to OV. As a result, both the second transistor 403 and the first transistor 402 in cell 400 are turned on, and BLO is pulled up to 1.2V.

[0098] In cell 410, the second transistor 413 is turned on, but the first transistor 412 is off because transistor 412 is in an unprogrammed state, and the negative threshold voltage is lower than the floating gate voltage. Thus, BLl remains at OV. The high voltage in BLO is then sensed by a sense amplifier and driven to output a data signal of state "1". Similarly, the low state of BLl is sensed by another sense amplifier and driven to output another data signal of state "0". Note that the transistors of the cells in the unselected row are in the off state, and the cells are disconnected from the bit lines.

[0099] In the array, a designated memory cell can also be erased. Erasure can be performed in a conventional manner, such as Fowler-Nordheim tunneling. During the erase operation, electrons are removed from the floating gate of the selected cell, causing the threshold voltage of the PMOS transistor to increase, making it more difficult to turn on, and causing the read current during a read operation to decrease.

[0100] For example, memory cell 400 can be erased as follows. CGO is driven to -5v, WLO is driven to 5v, BLO is driven to 3.3v, COMO is driven to 5v, and the potential of the N-well and deep N-well is 5v. As a result, the second transistor 403 is turned off, disconnecting the first transistor 402 from BLO. The NMOS capacitor 401 is in strong inversion, with an inversion layer formed in the lower plate. The floating gate is coupled to approximately -4.7v. In the case where the source of the first PMOS transistor 402 is driven to 5v, an inversion layer is also formed in the channel region of the transistor 402. In the case where the drain of the transistor 402 is isolated from BLO, the transistor 402 is in the linear region. The inversion channel connects the source and drain, which are at 5v. As a result, the total voltage applied to the gate and / or tunnel oxide is approximately 9.7v, creating a high electric field that can exceed approximately 10 MeV, tunneling through the tunnel oxide. This allows the majority of the electrons trapped in the floating gate to gain sufficient energy to tunnel to the inverted channel and recombine with holes. The mechanism is Fowler-Nordheim tunneling.

[0101] In this embodiment, the CGO and P-well shared by cells 400 and 410 can be driven to a negative potential that is less than the substrate bias (0v) because the P-well is isolated from the substrate by the deep N-well. The deep N-well is driven to 5v during erase. Memory cell 410 also receives the CGO voltage of -5v, but the source of the first PMOS transistor 412 receives a bias of 0v. As a result, the voltage across the gate oxide is only 4.7v, and even though inversion layers are formed in the channels of both the transistor 412 and the NMOS capacitor 411, the electric field is not sufficient to trigger Fowler-Nordheim tunneling. Thus, memory cell 410 is not affected during erase.

[0102] In memory cell 420, the source of the first PMOS transistor is driven to 5v, but the coupled gate connected to CGl receives a bias of 0v. As a result, the voltage across the gate oxide of the first PMOS transistor is only 4.7v. Even though inversion layers are formed in the channels of both the first PMOS transistor 422 and the NMOS capacitor 421, the electric field is not sufficient to trigger Fowler-Nordheim tunneling. Thus, the erase disturbance on memory cell 420 is negligible.

[0103] In the storage cell 430, the CG and source of the first PMOS transistor 432 are both biased at 0 volts. The electric field across the gate oxide of the transistor 432 is thus negligible, and the tunneling current within the transistor 432 is negligible. Erase disturbance within the cell 430 is thus insignificant.

[0104] The read operation after erasing is the same as the read operation after programming of the array. In the read operation, the data within a row of storage cells can be read simultaneously. The first PMOS transistor in the erased cell has a threshold voltage of approximately -1.5 volts.

[0105] It will be appreciated that various operations, processes, and methods described herein can be embodied in a machine- readable medium and / or machine-accessible medium associated with a data processing system, e.g., a computer system, and can be implemented in any of a variety of orders (e.g., including employing the methods to implement various different operations). Accordingly, the description and drawings are to be regarded as illustrative in nature and not as restrictive.

Claims

1. A programming method for a nonvolatile memory, the memory comprising at least one nonvolatile memory cell constructed on a P-type substrate, wherein each nonvolatile memory cell comprises a deep N-well located in the P-type substrate, wherein a P-well and an N-well are located in the deep N-well, and a first PMOS transistor located in the N-well. An NMOS capacitor is located in the P-well, the NMOS capacitor includes an N+ coupling region located in the P-well; and a floating gate, which is located over the PMOS transistor and the NMOS capacitor; The programming method is to program the first PMOS transistor in the non-volatile memory cell by band-to-band tunneling, which includes the following steps: (a) making the potential of the N-well greater than the potential of one terminal of the first PMOS transistor, and the potential difference between the two forms a reverse bias voltage at the PN junction of the interface between the N-well and the terminal, which causes the electrons of the PN junction to concentrate on the side close to the N-well; (b) making the potential on the floating gate of the first PMOS transistor greater than the potential of the above-mentioned terminal, and the potential difference between the two can form an electric field with an intensity greater than 8 MV / cm between the floating gate and the terminal; (c) under the action of the above-mentioned strong electric field, the electrons on the side close to the N-well in the PN junction of the interface between the N-well and the terminal are injected into the floating gate of the first PMOS transistor to achieve programming. The potential difference between the N-well and the terminal is 0.1-1.0 V less than the avalanche breakdown voltage of the PN junction at the interface.

2. The programming method of claim 1, wherein the potential on the floating gate of the first PMOS transistor is coupled by the potential applied to the N+ coupling region of the NMOS capacitor, and the potential applied to the N+ coupling region is less than or equal to the potential of the N-well.

3. The programming method of claim 2, wherein the potential applied to the N+ coupling region is equal to the potential of the N-well.

4. The programming method of claim 1 or 2, wherein the terminal of the first PMOS transistor is the source electrode, and the potential during programming is 0 V; the other terminal of the first PMOS transistor is the drain electrode, which is in a suspended state during programming.

5. The programming method of claim 1, wherein the capacitance of the NMOS is greater than the gate capacitance of the PMOS.

6. The programming method of claim 1 or 2, wherein the non-volatile memory cell further includes a second PMOS transistor located in the N-well, wherein the drain electrode of the first PMOS transistor is coupled to the source electrode of the second PMOS transistor, and the drain electrode of the second PMOS transistor does not participate in programming.

7. The programming method of claim 6, wherein the drain electrode of the second PMOS transistor is in a suspended state during programming.

8. The programming method of claim 7, wherein the potential of the gate electrode of the second PMOS transistor is the same as the potential of the N-well during programming.

9. The programming method of claim 6, wherein the channel of the second PMOS transistor is not conductive during programming.

10. The programming method of claim 1, wherein the floating gate in the memory cell is a single-layer polysilicon gate.

11. The programming method of claim 1, wherein the non-volatile memory is electrically programmable and erasable non-volatile memory.

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