A cascaded gallium nitride module with a stacked structure

Abstract

The present invention relates to a cascaded gallium nitride module with a stacked structure, comprising: a first substrate, a second substrate and a double-sided printed circuit board which are stacked and opposite to each other in sequence; the first substrate is connected with a plurality of upper bridge arm depletion-type gallium nitride chips and upper bridge arm enhancement-type MOSFET chips; the plurality of upper bridge arm depletion-type gallium nitride chips are symmetrically distributed along the symmetry axis and are connected in parallel with each other; the upper bridge arm enhancement-type MOSFET chip is interconnected with a plurality of upper bridge arm depletion-type gallium nitride chips respectively; the second substrate is connected with a plurality of upper bridge arm depletion-type gallium nitride chips and upper bridge arm enhancement-type MOSFET chips; the plurality of upper bridge arm depletion-type gallium nitride chips of the first substrate and the plurality of lower bridge arm depletion-type gallium nitride chips of the second substrate are arranged one by one oppositely, and the plurality of lower bridge arm depletion-type gallium nitride chips of the second substrate are also connected in parallel with each other; the lower bridge arm enhancement-type MOSFET chip is interconnected with a plurality of lower bridge arm depletion-type gallium nitride chips respectively. The current directions of any two adjacent layers of the power circuit of the module are opposite, which reduces the parasitic inductance of the internal interconnection of the module; the parasitic parameters of the parallel gallium nitride chips are matched consistently, which further improves the performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of gallium nitride power devices, and in particular relates to a cascaded gallium nitride module with a stacked structure. Background Art

[0002] In recent years, gallium nitride (GaN) devices have been widely used in high-frequency, high-power density power electronics scenarios due to their advantages such as high electron mobility and high switching speed. GaN cascode devices are compatible with the driving mode of traditional silicon-based MOSFET devices and can directly replace silicon-based power devices, showing broader application potential. However, despite the excellent performance of GaN cascode devices, the power handling capacity of existing gallium nitride devices is still limited. To this end, by connecting multiple chips in parallel, the current handling capacity of the device can be greatly improved, thereby expanding the applicability of gallium nitride devices in high-power applications.

[0003] However, in GaN cascade modules with multiple chips in parallel, parasitic parameter matching between depletion-mode HEMT devices and low-voltage MOSFET devices is a key issue. In particular, multiple GaN chips in parallel are required to have consistent external parasitic parameters. Any inconsistency in parasitic parameters may lead to serious performance problems, such as turn-off overshoot, asynchronous turn-off between parallel chips, voltage spikes and oscillations, and increased device losses, and may even cause avalanche breakdown of low-voltage Si MOSFETs, thereby affecting the performance and reliability of the entire module. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a cascaded gallium nitride module with a stacked structure. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] An embodiment of the present invention provides a cascaded gallium nitride module with a stacked structure, comprising: a first substrate, a second substrate and a double-sided printed circuit board, wherein the first substrate, the double-sided printed circuit board and the second substrate are stacked in sequence and arranged opposite to each other;

[0006] A surface of the first substrate facing the double-sided printed circuit board is connected to a plurality of upper bridge arm depletion-type gallium nitride chips and upper bridge arm enhancement-type MOSFET chips through pads; the plurality of upper bridge arm depletion-type gallium nitride chips are symmetrically distributed along the symmetry axis and are connected in parallel with each other; the upper bridge arm enhancement-type MOSFET chip is located between the plurality of upper bridge arm depletion-type gallium nitride chips and is interconnected with the plurality of upper bridge arm depletion-type gallium nitride chips respectively;

[0007] The surface of the second substrate facing the double-sided printed circuit board is connected with a plurality of lower bridge arm depletion-type gallium nitride chips and lower bridge arm enhancement-type MOSFET chips through pads; the plurality of lower bridge arm depletion-type gallium nitride chips are arranged opposite to the plurality of upper bridge arm depletion-type gallium nitride chips one by one and are connected in parallel with each other; the lower bridge arm enhancement-type MOSFET chip is arranged opposite to the upper bridge arm enhancement-type MOSFET chip and is interconnected with the plurality of lower bridge arm depletion-type gallium nitride chips respectively;

[0008] The upper bridge arm enhancement mode MOSFET chip and the plurality of lower bridge arm depletion mode gallium nitride chips are connected via pads on the surface of the double-sided printed circuit board;

[0009] The current direction of the power circuit in the first substrate is opposite to the current direction of the power circuit in the first surface of the double-sided printed circuit board, the current direction of the power circuit in the first surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second surface of the double-sided printed circuit board, the current direction of the power circuit in the second surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second substrate, the first surface faces the first substrate, and the second surface faces the second substrate.

[0010] In one embodiment of the present invention, the pads on the surface of the first substrate include a first pad, a second pad, a third pad, a fourth pad, a fifth pad, a sixth pad, a seventh pad, an eighth pad and a ninth pad, wherein:

[0011] The first pad, the second pad, the third pad, the fourth pad, the fifth pad, the sixth pad, the seventh pad, the eighth pad and the ninth pad are matched with each other in concave and convex manners;

[0012] The plurality of upper bridge arm depletion-type gallium nitride chips are axially symmetrically distributed on the fifth pad; substrates and gates of the plurality of upper bridge arm depletion-type gallium nitride chips are connected to the fifth pad, drains are connected to the sixth pad, and sources are connected to the first pad, the second pad, the third pad, and the fourth pad, respectively, one by one, so as to realize parallel connection of the plurality of upper bridge arm depletion-type gallium nitride chips;

[0013] The source electrode of the upper bridge arm enhancement MOSFET chip is connected to the fifth pad, the gate electrode is connected to the ninth pad, and the drain electrode is connected to both the seventh pad and the eighth pad;

[0014] The sixth pad is connected to the first power terminal, the fifth pad is connected to the first Kelvin source pin, and the ninth pad is connected to the first gate pin;

[0015] The first pad, the second pad, the third pad, the fourth pad, the fifth pad, the seventh pad, and the eighth pad are correspondingly connected to a plurality of pads on the first surface of the double-sided printed circuit board to interconnect the plurality of upper bridge arm depletion-mode gallium nitride chips with the upper bridge arm enhancement-mode MOSFET chip, respectively.

[0016] In one embodiment of the present invention, the plurality of upper bridge arm depletion-type gallium nitride chips include a first upper bridge arm depletion-type gallium nitride chip, a second upper bridge arm depletion-type gallium nitride chip, a third upper bridge arm depletion-type gallium nitride chip and a fourth upper bridge arm depletion-type gallium nitride chip, wherein:

[0017] The first upper bridge arm depletion-type gallium nitride chip, the second upper bridge arm depletion-type gallium nitride chip, the third upper bridge arm depletion-type gallium nitride chip and the fourth upper bridge arm depletion-type gallium nitride chip are axially symmetrically distributed;

[0018] The substrate and gate of the first upper bridge arm depletion-type gallium nitride chip are both connected to the fifth pad, the source is connected to the first pad, and the drain is connected to the sixth pad;

[0019] The substrate and gate of the second upper bridge arm depletion-type gallium nitride chip are both connected to the fifth pad, the source is connected to the second pad, and the drain is connected to the sixth pad;

[0020] The substrate and gate of the third upper bridge arm depletion-type gallium nitride chip are both connected to the fifth pad, the source is connected to the third pad, and the drain is connected to the sixth pad;

[0021] The substrate and gate of the fourth upper bridge arm depletion-type gallium nitride chip are both connected to the fifth pad, the source is connected to the fourth pad, and the drain is connected to the sixth pad.

[0022] In one embodiment of the present invention, the pads on the first surface of the double-sided printed circuit board include a tenth pad, an eleventh pad and a twelfth pad, wherein:

[0023] The eleventh pad is located on one side of the symmetry axis, connected to the first pad, the third pad and the seventh pad, and covers a plurality of upper bridge arm depletion-type gallium nitride chips on one side of the symmetry axis;

[0024] The twelfth pad is located on the other side of the symmetry axis, connected to the second pad, the fourth pad and the eighth pad, and covers a plurality of upper bridge arm depletion-type gallium nitride chips on the other side of the symmetry axis;

[0025] The tenth soldering pad is located between the eleventh soldering pad and the twelfth soldering pad, and is connected to the soldering pad on the second surface of the double-sided printed circuit board.

[0026] In one embodiment of the present invention, a first connecting element, a second connecting element, a third connecting element, a fourth connecting element, a fifth connecting element, a sixth connecting element and a seventh connecting element are connected between the first substrate and the double-sided printed circuit board, wherein:

[0027] The first connecting element connects the first pad and the eleventh pad, the second connecting element connects the second pad and the twelfth pad, the third connecting element connects the third pad and the eleventh pad, the fourth connecting element connects the fourth pad and the twelfth pad, the fifth connecting element connects the seventh pad and the eleventh pad, the sixth connecting element connects the eighth pad and the twelfth pad, and the seventh connecting element connects the fifth pad and the tenth pad.

[0028] In one embodiment of the present invention, the pads on the surface of the second substrate include a fourteenth pad, a fifteenth pad, a sixteenth pad, a seventeenth pad, an eighteenth pad, a nineteenth pad, a twentieth pad and a twenty-first pad, wherein:

[0029] The fourteenth pad, the fifteenth pad, the sixteenth pad, the seventeenth pad, the eighteenth pad, the nineteenth pad, the twentieth pad, and the twenty-first pad are matched with each other in a concave-convex manner;

[0030] The substrates and gates of the plurality of lower bridge arm depletion-type gallium nitride chips are connected to the fourteenth pad, the drains are connected to the fifteenth pad, the sixteenth pad, the seventeenth pad, and the eighteenth pad respectively, the sources of the lower bridge arm depletion-type gallium nitride chips on one side of the symmetry axis are connected to the nineteenth pad, and the sources of the lower bridge arm depletion-type gallium nitride chips on the other side of the symmetry axis are connected to the twentieth pad, so as to realize the parallel connection of the plurality of lower bridge arm depletion-type gallium nitride chips;

[0031] The source of the lower bridge arm enhancement MOSFET chip is connected to the fourteenth pad, the gate is connected to the twenty-first pad, and the drain is connected to both the nineteenth pad and the twenty-third pad, so as to interconnect the lower bridge arm enhancement MOSFET chip and the plurality of lower bridge arm depletion-type gallium nitride chips respectively;

[0032] The fourteenth pad is connected to the second power terminal and the second Kelvin source pin, and the twenty-first pad is connected to the second gate pin;

[0033] The fifteenth pad, the sixteenth pad, the seventeenth pad, and the eighteenth pad are connected to the pads on the second surface of the double-sided printed circuit board.

[0034] In one embodiment of the present invention, the plurality of lower bridge arm depletion-type gallium nitride chips include a first lower bridge arm depletion-type gallium nitride chip, a second lower bridge arm depletion-type gallium nitride chip, a third lower bridge arm depletion-type gallium nitride chip and a fourth lower bridge arm depletion-type gallium nitride chip, wherein:

[0035] The first lower bridge arm depletion-type gallium nitride chip, the second lower bridge arm depletion-type gallium nitride chip, the third lower bridge arm depletion-type gallium nitride chip and the fourth lower bridge arm depletion-type gallium nitride chip are axially symmetrically distributed and are opposite to the plurality of upper bridge arm depletion-type gallium nitride chips one by one;

[0036] The gate and substrate of the first lower bridge arm depletion-type gallium nitride chip are both connected to the fourteenth pad, the drain is connected to the fifteenth pad, and the source is connected to the nineteenth pad;

[0037] The gate and substrate of the second lower bridge arm depletion-type gallium nitride chip are both connected to the fourteenth pad, the drain is connected to the sixteenth pad, and the source is connected to the 20th pad;

[0038] The gate and substrate of the third lower bridge arm depletion-type gallium nitride chip are both connected to the fourteenth pad, the drain is connected to the seventeenth pad, and the source is connected to the nineteenth pad;

[0039] The gate and substrate of the fourth lower bridge arm depletion-type gallium nitride chip are both connected to the fourteenth pad, the drain is connected to the eighteenth pad, and the source is connected to the twentieth pad.

[0040] In one embodiment of the present invention, the pads on the second surface of the double-sided printed circuit board include a thirteenth pad, wherein:

[0041] The thirteenth pad covers the plurality of lower bridge arm depletion-mode gallium nitride chips and the lower bridge arm enhancement-mode MOSFET chip, is connected to the pad on the first surface of the double-sided printed circuit board, and is connected to the fifteenth pad, the sixteenth pad, the seventeenth pad, and the eighteenth pad;

[0042] The thirteenth pad is connected to the third power terminal.

[0043] In one embodiment of the present invention, an eighth connecting element, a ninth connecting element, a tenth connecting element and an eleventh connecting element are connected between the second substrate and the double-sided printed circuit board, wherein:

[0044] The eighth connecting element connects the fifteenth pad and the thirteenth pad, the ninth connecting element connects the sixteenth pad and the thirteenth pad, the tenth connecting element connects the seventeenth pad and the thirteenth pad, and the eleventh connecting element connects the eighteenth pad and the thirteenth pad.

[0045] In one embodiment of the present invention, the substrates of the plurality of upper bridge arm depletion-mode gallium nitride chips and the source of the upper bridge arm enhancement-mode MOSFET chip are at the same potential;

[0046] The substrates of the plurality of lower-bridge-arm depletion-mode gallium nitride chips and the source of the lower-bridge-arm enhancement-mode MOSFET chip have the same potential.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] 1. In the cascaded gallium nitride module of the present invention, a plurality of parallel upper bridge arm depletion-type gallium nitride chips are symmetrically distributed along the symmetry axis, and a plurality of parallel lower bridge arm depletion-type gallium nitride chips are arranged one by one relative to a plurality of upper bridge arm depletion-type gallium nitride chips, thereby realizing a symmetrical layout of the upper bridge arm depletion-type gallium nitride chip and the lower bridge arm depletion-type gallium nitride chip, ensuring the consistency of the interconnection circuit structure between the upper bridge arm gallium nitride chip and the upper bridge arm MOSFET chip, and between the lower bridge arm gallium nitride chip and the lower bridge arm MOSFET chip, and realizing the interconnection of the upper bridge arm cascade power circuit and the lower bridge cascade power circuit by using a double-sided printed circuit board, making the upper bridge arm cascade power circuit and the lower bridge arm cascade power circuit structure inside the module more symmetrical, improving the consistency of the gallium nitride chip and the external circuit parasitic parameters, solving the problem of the consistency of the parallel gallium nitride chips and the matching of the external parameters of the gallium nitride chip and the MOSFET chip, thereby improving the switching performance and reliability of the gallium nitride module;

[0049] 2. The present invention utilizes a first substrate, a second substrate and a double-sided printed circuit board to construct a laminated structure, and designs the gallium nitride module as a four-layer power circuit architecture. The current direction of the power circuit in the first substrate is opposite to the current direction of the power circuit in the first surface of the double-sided printed circuit board, the current direction of the power circuit in the first surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second surface of the double-sided printed circuit board, and the current direction of the power circuit in the second surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second substrate, ensuring that the current directions of any two adjacent upper and lower power circuits are opposite and the magnetic flux directions are opposite, achieving magnetic flux cancellation between adjacent layers. The four-layer power circuit form not only reduces the parasitic inductance in the module, but also improves the power density of the module, thereby improving the electromagnetic interference performance and efficiency of the entire system;

[0050] 3. In the present invention, the substrates of several upper-arm depletion-type gallium nitride chips and the source of the upper-arm enhancement-type MOSFET chip are at the same potential, and the substrates of several lower-arm depletion-type gallium nitride chips and the source of the lower-arm enhancement-type MOSFET chip are at the same potential, thereby avoiding the increase in dynamic on-resistance and the reduction in device stability that may be caused by the floating potential of the gallium nitride chip substrate; at the same time, the trapped electrons in the substrate can be reduced in the off state, and the release of trapped electrons in the substrate can be reduced in the on state, thereby ensuring that the gallium nitride device has a more stable dynamic on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic diagram of the three-dimensional structure of a cascaded gallium nitride module with a stacked structure provided by an embodiment of the present invention;

[0052] Figure 2 A schematic diagram of a circuit arrangement of a first substrate provided in an embodiment of the present invention;

[0053] Figure 3 A schematic diagram of the circuit layout on the first surface of a double-sided printed circuit board provided by an embodiment of the present invention;

[0054] Figure 4 A schematic diagram of the circuit layout on the second surface of a double-sided printed circuit board provided by an embodiment of the present invention;

[0055] Figure 5 A schematic diagram of a circuit arrangement of a second substrate provided in an embodiment of the present invention;

[0056] Figure 6 A schematic diagram of current flow in a cascaded gallium nitride module with a stacked structure provided by an embodiment of the present invention;

[0057] Figure 7 A circuit diagram of a cascaded gallium nitride module with a stacked structure provided by an embodiment of the present invention;

[0058] Figure 8 A schematic diagram of the process of packaging a cascaded gallium nitride half-bridge module provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0060] Embodiment 1

[0061] This embodiment provides a structural design of a cascaded GaN module, which can improve the consistency of parasitic parameters between the internal depletion-mode HEMT device and the low-voltage MOSFET device of the GaN, and solve the performance and reliability problems caused by the mismatch of the external parasitic parameters of the chip.

[0062] See also Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , Figure 1 A schematic diagram of the three-dimensional structure of a cascaded gallium nitride module with a stacked structure provided by an embodiment of the present invention, Figure 2 A schematic diagram of a circuit arrangement of a first substrate provided in an embodiment of the present invention, Figure 3 A schematic diagram of the circuit layout on the first surface of a double-sided printed circuit board provided by an embodiment of the present invention, Figure 4 A schematic diagram of the circuit layout on the second surface of a double-sided printed circuit board provided by an embodiment of the present invention, Figure 5 A schematic diagram of the circuit arrangement of the second substrate provided in an embodiment of the present invention.

[0063] like Figure 1 As shown, the cascaded gallium nitride module of the stacked structure of this embodiment includes a first substrate 100, a second substrate 200 and a double-sided printed circuit board 300, the first substrate 100, the double-sided printed circuit board 300 and the second substrate 200 are stacked in sequence and arranged opposite to each other, and the first substrate 100, the second substrate 200 and the double-sided printed circuit board 300 form a package.

[0064] Specifically, the first substrate 100 includes a double-sided copper-clad ceramic (DBC) substrate upper plate, and the second substrate 200 includes a double-sided copper-clad ceramic (DBC) substrate lower plate. The double-sided copper-clad ceramic substrate can be prepared by a sintering process. During the preparation process, the ceramic layer directly contacts the copper sheet, and a eutectic solution is formed on the contact surface by high-temperature sintering, thereby generating a high-strength connection with the ceramic. Then, a polyimide film is used to construct a pad shape for the prepared double-sided copper-clad ceramic substrate, and then FeCl is used. 3 The required double-sided copper-clad ceramic substrate can be obtained by etching with the solution. The double-sided printed circuit board 300 includes a PCB substrate. The material of the double-sided printed circuit board is FR-4, and the pads are printed on the double-sided printed circuit board. The first substrate 100, the double-sided printed circuit board 300, and the second substrate 200 form a cascaded gallium nitride module packaging structure of a DBC / PCB / DBC laminated structure. The packaging structure uses a full-filled plastic packaging process to plastic-encapsulate the soldered circuit module, wherein the second substrate 200 is the bottom of the packaging structure, the first substrate 100 is the top of the packaging structure, and the double-sided printed circuit board 300 is placed between the first substrate 100 and the second substrate 200, and is opposite to the first substrate 100 and the second substrate 200. The first surface of the first substrate 100 and the double-sided printed circuit board 300 is arranged with an upper bridge arm cascaded gallium nitride power circuit, and the second surface of the second substrate 200 and the double-sided printed circuit board 300 is arranged with a lower bridge arm cascaded gallium nitride power circuit.

[0065] A surface of the first substrate 100 facing the double-sided printed circuit board 300 is connected to a plurality of upper-arm depletion-type gallium nitride chips and an upper-arm enhancement-type MOSFET chip 110 through pads; the plurality of upper-arm depletion-type gallium nitride chips are symmetrically distributed along the symmetry axis and are connected in parallel with each other; the upper-arm enhancement-type MOSFET chip 110 is located between the plurality of upper-arm depletion-type gallium nitride chips and is interconnected with the plurality of upper-arm depletion-type gallium nitride chips respectively.

[0066] Specifically, several upper bridge arm depletion-type gallium nitride chips adopt the same structure and are axially symmetrically distributed. The symmetry axis can be any straight line on the surface of the first substrate 100, that is, the symmetry axis can be a straight line along any direction or a straight line at any position. Preferably, the symmetry axis is the symmetry axis of the first substrate 100 along the vertical direction or the horizontal direction. Through the axially symmetrical layout and the connection of the pads on the surface of the first substrate 100, several upper bridge arm depletion-type gallium nitride chips are connected in parallel with each other. The upper bridge arm enhancement MOSFET chip 110 is located between the symmetrically distributed upper bridge arm depletion-type gallium nitride chips, and can be set at any position on the symmetry axis or at any position on both sides of the symmetry axis. Through the corresponding connection of several pads on the surface of the first substrate 100 and several pads on the double-sided printed circuit board 300, the upper bridge arm enhancement MOSFET chip 110 and several upper bridge arm depletion-type gallium nitride chips are interconnected respectively.

[0067] The surface of the second substrate 200 facing the double-sided printed circuit board 300 is connected with a plurality of lower-arm depletion-type gallium nitride chips and a lower-arm enhancement-type MOSFET chip 210 through pads; the plurality of lower-arm depletion-type gallium nitride chips are arranged opposite to the plurality of upper-arm depletion-type gallium nitride chips one by one and are connected in parallel with each other; the lower-arm enhancement-type MOSFET chip 210 is arranged opposite to the upper-arm enhancement-type MOSFET chip 110 and is interconnected with the plurality of lower-arm depletion-type gallium nitride chips respectively.

[0068] Specifically, several lower bridge arm depletion-type gallium nitride chips adopt the same structure, and are the same chip as several upper bridge arm depletion-type gallium nitride chips, and several lower bridge arm depletion-type gallium nitride chips are arranged one by one relative to several upper bridge arm depletion-type gallium nitride chips, that is, several lower bridge arm depletion-type gallium nitride chips are axially symmetrically distributed, and their symmetry axes coincide with the symmetry axes of several upper bridge arm depletion-type gallium nitride chips. Through the axially symmetrical layout and the connection of the pads on the surface of the second substrate 200, several upper bridge arm depletion-type gallium nitride chips are connected in parallel with each other. The lower bridge arm enhancement MOSFET chip 210 is the same chip as the upper bridge arm enhancement MOSFET chip 110, and the two are facing each other. When the position of the upper bridge arm enhancement MOSFET chip 110 changes, the position of the lower bridge arm enhancement MOSFET chip 210 also changes accordingly. Through the connection of several pads on the surface of the second substrate 200, the lower bridge arm enhancement MOSFET chip 210 and several lower bridge arm depletion-type gallium nitride chips are interconnected respectively.

[0069] The upper bridge arm enhancement mode MOSFET chip 110 and the plurality of lower bridge arm depletion mode GaN chips are connected via pads on the surface of the double-sided printed circuit board 300 .

[0070] Specifically, several pads on the first surface of the double-sided printed circuit board 300 are connected to several pads on the surface of the first substrate 100 to realize the connection between the upper bridge arm enhancement MOSFET chip 110 and the loop of the first surface of the double-sided printed circuit board 300; the pads on the second surface of the double-sided printed circuit board 300 are connected to several pads on the first surface through through holes to realize the connection between the loop of the first surface of the double-sided printed circuit board 300 and the loop of the second surface of the double-sided printed circuit board 300; the pads on the second surface of the double-sided printed circuit board 300 are connected to several pads on the surface of the second substrate 200 to realize the connection between the loop of the second surface of the double-sided printed circuit board 300 and several lower bridge arm depletion-type gallium nitride chips; through the above connection, the connection between the upper bridge arm enhancement MOSFET chip 110 and several lower bridge arm depletion-type gallium nitride chips is realized.

[0071] The current direction of the power circuit in the first substrate 100 is opposite to the current direction of the power circuit in the first surface of the double-sided printed circuit board 300, the current direction of the power circuit in the first surface of the double-sided printed circuit board 300 is opposite to the current direction of the power circuit in the second surface of the double-sided printed circuit board 300, the current direction of the power circuit in the second surface of the double-sided printed circuit board 300 is opposite to the current direction of the power circuit in the second substrate 200, the first surface faces the first substrate 100, and the second surface faces the second substrate 200.

[0072] Exemplarily, the current direction of the first substrate 100 flows from the center of the module to the periphery of the module, the current direction of the first surface of the double-sided printed circuit board 300 flows from the periphery of the module to the center of the module, the current direction of the second surface of the double-sided printed circuit board 300 flows from the center of the module to the periphery of the module, and the current direction in the second substrate 200 flows from the periphery of the module to the center of the module, thereby achieving opposite current directions and opposite magnetic flux directions in any two adjacent upper and lower power circuits.

[0073] In this embodiment, the connection between the upper arm depletion-mode gallium nitride chips, the upper arm enhancement-mode MOSFET chip 110 and the first substrate surface pads can be made by silver sintering, and the connection between the lower arm depletion-mode gallium nitride chips, the lower arm enhancement-mode MOSFET chip 210 and the second substrate surface pads can be made by silver sintering.

[0074] like Figure 2 As shown, the pads on the surface of the first substrate 100 include a first pad 1 , a second pad 2 , a third pad 3 , a fourth pad 4 , a fifth pad 5 , a sixth pad 6 , a seventh pad 7 , an eighth pad 8 and a ninth pad 9 .

[0075] The first pad 1 , the second pad 2 , the third pad 3 , the fourth pad 4 , the fifth pad 5 , the sixth pad 6 , the seventh pad 7 , the eighth pad 8 and the ninth pad 9 are matched with each other in concave and convex directions.

[0076] Specifically, the first pad 1, the second pad 2, the third pad 3, and the fourth pad 4 are distributed on opposite sides of the fifth pad 5 along the symmetry axis; the sixth pad 6 is located in the first recessed area formed by the fifth pad 5, and is located between the first pad 1 and the second pad 2; the seventh pad 7 is located in the first enclosed area formed by the sixth pad 6 and the fifth pad 5; the eighth pad 8 is located in the second enclosed area formed by the sixth pad 6 and the fifth pad 5; the ninth pad 9 is located in the second recessed area formed by the fifth pad 5, and is located between the seventh pad 7 and the eighth pad 8. It should be noted that the pad distribution on the surface of the first substrate 100 is not limited to the above form, and can meet the layout requirements of several upper bridge arm depletion-type gallium nitride chips.

[0077] Several upper bridge arm depletion-type gallium nitride chips are axially symmetrically distributed on the fifth pad 5. The substrates and gates of several upper bridge arm depletion-type gallium nitride chips are connected to the fifth pad 5, the drains are connected to the sixth pad 6, and the sources are connected to the first pad 1, the second pad 2, the third pad 3, and the fourth pad 4 in a one-to-one correspondence, so as to realize the parallel connection of several upper bridge arm depletion-type gallium nitride chips.

[0078] Specifically, the substrates of several upper bridge arm depletion-type gallium nitride chips are located on the fifth pad 5 and are directly connected to the fifth pad 5; the gate, source, and drain of several upper bridge arm depletion-type gallium nitride chips are far away from the fifth pad 5, so the gate is connected to the fifth pad 5 using a copper clip, the drain is connected to the sixth pad 6 using a copper clip, and the source is connected to the corresponding pad using a copper clip.

[0079] The source of the upper bridge arm enhancement MOSFET chip 110 is connected to the fifth pad 5 , the gate is connected to the ninth pad 9 , and the drain is connected to both the seventh pad 7 and the eighth pad 8 .

[0080] Specifically, the source of the upper bridge arm enhancement MOSFET chip 110 is located on the fifth pad and directly connected to the fifth pad 5; the gate is located on the ninth pad 9 and directly connected to the ninth pad 9; the drain is away from the pad and connected to the seventh pad 7 and the eighth pad 8 using a copper clip.

[0081] The sixth pad 6 is connected to the first power terminal Vdc+, the fifth pad 5 is connected to the first Kelvin source pin Kelvin Source1, and the ninth pad 9 is connected to the first gate pin Gate1.

[0082] Specifically, the first power terminal Vdc+ is welded to the sixth welding pad 6 , the first gate pin Gate1 is welded to the ninth welding pad 9 , and the Kelvin source pin Kelvin Source1 is welded to the fifth welding pad 5 .

[0083] The first pad 1, the second pad 2, the third pad 3, the fourth pad 4, the fifth pad 5, the seventh pad 7 and the eighth pad 8 are connected to the pads on the first surface of the double-sided printed circuit board 300 to interconnect the upper arm depletion-mode gallium nitride chips with the upper arm enhancement-mode MOSFET chip 110 respectively.

[0084] like Figure 2As shown, the plurality of upper-arm depletion-type GaN chips include a first upper-arm depletion-type GaN chip 120 , a second upper-arm depletion-type GaN chip 130 , a third upper-arm depletion-type GaN chip 140 and a fourth upper-arm depletion-type GaN chip 150 . Among them, the first upper arm depletion type gallium nitride chip 120, the second upper arm depletion type gallium nitride chip 130, the third upper arm depletion type gallium nitride chip 140 and the fourth upper arm depletion type gallium nitride chip 150 are axially symmetrically distributed; the substrate and gate of the first upper arm depletion type gallium nitride chip 120 are both connected to the fifth pad 5, the source is connected to the first pad 1, and the drain is connected to the sixth pad 6; the substrate and gate of the second upper arm depletion type gallium nitride chip 130 are both connected to the fifth pad 5, the source is connected to the second pad 2, and the drain is connected to the sixth pad 6; the substrate and gate of the third upper arm depletion type gallium nitride chip 140 are both connected to the fifth pad 5, the source is connected to the third pad 3, and the drain is connected to the sixth pad 6; the substrate and gate of the fourth upper arm depletion type gallium nitride chip 150 are both connected to the fifth pad 5, the source is connected to the fourth pad 4, and the drain is connected to the sixth pad 6.

[0085] like Figure 3 As shown, the pads on the first surface of the double-sided printed circuit board 300 include the tenth pad 10, the eleventh pad 11 and the twelfth pad 12. Among them, the eleventh pad 11 is located on one side of the symmetry axis, connected to the first pad 1, the third pad 3 and the seventh pad 7, and covers a number of upper bridge arm depletion-type gallium nitride chips on one side of the symmetry axis; the twelfth pad 12 is located on the other side of the symmetry axis, connected to the second pad 2, the fourth pad 4 and the eighth pad 8, and covers a number of upper bridge arm depletion-type gallium nitride chips on the other side of the symmetry axis; the tenth pad 10 is located between the eleventh pad 11 and the twelfth pad 12, and is connected to the pads on the second surface of the double-sided printed circuit board 300.

[0086] Specifically, the eleventh pad 11 is connected to the first pad 1, the third pad 3, and the seventh pad 7 to realize the interconnection between the first upper arm depletion-type gallium nitride chip 120, the third upper arm depletion-type gallium nitride chip 140 and the upper arm enhancement-type MOSFET chip 110; the twelfth pad 12 is connected to the second pad 2, the fourth pad 4, and the eighth pad 8 to realize the interconnection between the second upper arm depletion-type gallium nitride chip 130, the fourth upper arm depletion-type gallium nitride chip 150 and the upper arm enhancement-type MOSFET chip 110. The tenth pad 10 is arranged at a position close to the upper arm enhancement-type MOSFET chip 110. Preferably, the eleventh pad 11 and the twelfth pad 12 are arranged symmetrically.

[0087] like Figure 2 and Figure 3As shown, a first connecting element a1, a second connecting element a2, a third connecting element a3, a fourth connecting element a4, a fifth connecting element b1, a sixth connecting element b2 and a seventh connecting element c1 are connected between the first substrate 100 and the double-sided printed circuit board 300. The first connecting element a1 connects the first pad 1 and the eleventh pad 11, the second connecting element a2 connects the second pad 2 and the twelfth pad 12, the third connecting element a3 connects the third pad 3 and the eleventh pad 11, the fourth connecting element a4 connects the fourth pad 4 and the twelfth pad 12, the fifth connecting element b1 connects the seventh pad 7 and the eleventh pad 11, the sixth connecting element b2 connects the eighth pad 8 and the twelfth pad 12, and the seventh connecting element c1 connects the fifth pad 5 and the tenth pad 10. Specifically, the connecting element may be a copper column, and the pads and the copper columns are connected by welding using silver sintering.

[0088] like Figure 5 As shown, the pads on the surface of the second substrate 200 include a fourteenth pad 14 , a fifteenth pad 15 , a sixteenth pad 16 , a seventeenth pad 17 , an eighteenth pad 18 , a nineteenth pad 19 , a twentieth pad 20 and a twenty-first pad 21 .

[0089] The fourteenth pad 14 , the fifteenth pad 15 , the sixteenth pad 16 , the seventeenth pad 17 , the eighteenth pad 18 , the nineteenth pad 19 , the twentieth pad 20 , and the twenty-first pad 21 are matched with each other in concave and convex directions.

[0090] Specifically, the fifteenth pad 15, the sixteenth pad 16, the seventeenth pad 17, and the eighteenth pad 18 are distributed along the symmetry axis on opposite sides of the fourteenth pad 14, the nineteenth pad 19, the twentieth pad 20, and the twenty-first pad 21 are located in the recessed area formed by the fourteenth pad 14, and the twenty-first pad 21 is adjacent to the seventeenth pad 17 and is located between the nineteenth pad 19 and the twentieth pad 20. It should be noted that the distribution of pads on the surface of the second substrate 200 is not limited to the above form, and can meet the layout requirements of several lower bridge arm depletion-type gallium nitride chips.

[0091] The substrates and gates of several lower bridge arm depletion-type gallium nitride chips are connected to the fourteenth pad 14, and the drains are connected to the fifteenth pad 15, the sixteenth pad 16, the seventeenth pad 17, and the eighteenth pad 18 respectively. The sources of the lower bridge arm depletion-type gallium nitride chips located on one side of the symmetry axis are connected to the nineteenth pad 19, and the sources of the lower bridge arm depletion-type gallium nitride chips located on the other side of the symmetry axis are connected to the twentieth pad 20, so as to realize the parallel connection of several lower bridge arm depletion-type gallium nitride chips.

[0092] Specifically, the substrates of several lower bridge arm depletion-type gallium nitride chips are located on the fourteenth pad 14 and are directly connected to the fourteenth pad 14; the gate, source, and drain of several lower bridge arm depletion-type gallium nitride chips are far away from the fourteenth pad 14, so the gate is connected to the fourteenth pad 14 using a copper clip, the source is connected to the nineteenth pad 19 and the twentieth pad 20 using a copper clip, and the drain is connected to the corresponding pad using a copper clip.

[0093] The source of the lower bridge arm enhancement MOSFET chip 210 is connected to the fourteenth pad 14, the gate is connected to the twenty-first pad 21, and the drain is connected to both the nineteenth pad 19 and the twentieth pad 20, so as to interconnect the lower bridge arm enhancement MOSFET chip 210 with several lower bridge arm depletion-type gallium nitride chips respectively.

[0094] Specifically, the source of the lower bridge arm enhancement MOSFET chip 210 is located on the fourteenth pad 14 and connected to the fourteenth pad 14; the gate is located on the twenty-first pad 21 and directly connected to the twenty-first pad 21; the drain is away from the pad and connected to the nineteenth pad 19 and the twentieth pad 20 using a copper clip. Through the connection of several lower bridge arm depletion-type gallium nitride chips, the lower bridge arm enhancement MOSFET chip 210 and the nineteenth pad 19 and the twentieth pad 20, the lower bridge arm enhancement MOSFET chip 210 and several lower bridge arm depletion-type gallium nitride chips are interconnected.

[0095] The fourteenth pad 14 is connected to the second power terminal Vdc- and the second Kelvin source pin Kelvin Source2, and the twenty-first pad 21 is connected to the second gate pin Gate2.

[0096] The fifteenth pad 15 , the sixteenth pad 16 , the seventeenth pad 17 , and the eighteenth pad 18 are connected to the pads on the second surface of the double-sided printed circuit board 300 .

[0097] like Figure 5As shown, several lower bridge arm depletion type gallium nitride chips include a first lower bridge arm depletion type gallium nitride chip 220, a second lower bridge arm depletion type gallium nitride chip 230, a third lower bridge arm depletion type gallium nitride chip 240 and a fourth lower bridge arm depletion type gallium nitride chip 250. Among them, the first lower bridge arm depletion type gallium nitride chip 220, the second lower bridge arm depletion type gallium nitride chip 230, the third lower bridge arm depletion type gallium nitride chip 240 and the fourth lower bridge arm depletion type gallium nitride chip 250 are axially symmetrically distributed and are opposite to several upper bridge arm depletion type gallium nitride chips one by one; the gate and substrate of the first lower bridge arm depletion type gallium nitride chip 220 are both connected to the fourteenth pad 14, the drain is connected to the fifteenth pad 15, and the source is connected to the nineteenth pad 19; the second lower bridge arm depletion type gallium nitride chip 220 is connected to the fourteenth pad 14, the drain is connected to the fifteenth pad 15, and the source is connected to the nineteenth pad 19; The gate and substrate of the gallium nitride chip 230 are both connected to the fourteenth pad 14, the drain is connected to the sixteenth pad 16, and the source is connected to the twentieth pad 20; the gate and substrate of the third lower bridge arm depletion-type gallium nitride chip 240 are both connected to the fourteenth pad 14, the drain is connected to the seventeenth pad 17, and the source is connected to the nineteenth pad 19; the gate and substrate of the fourth lower bridge arm depletion-type gallium nitride chip 250 are both connected to the fourteenth pad 14, the drain is connected to the eighteenth pad 18, and the source is connected to the twentieth pad 20.

[0098] like Figure 4 As shown, the pads on the second surface of the double-sided printed circuit board 300 include a thirteenth pad 13, wherein the thirteenth pad 13 covers a plurality of lower bridge arm depletion-type gallium nitride chips and a lower bridge arm enhancement-type MOSFET chip 210, is connected to the pads on the first surface of the double-sided printed circuit board 300, and is connected to the fifteenth pad 15, the sixteenth pad 16, the seventeenth pad 17, and the eighteenth pad 18, thereby realizing the connection between the lower bridge arm enhancement-type MOSFET chip 210 and the plurality of lower bridge arm depletion-type gallium nitride chips; the thirteenth pad 13 is welded and connected to the third power terminal Midpoint. Preferably, the thirteenth pad 13 is an axisymmetric structure.

[0099] like Figure 4 and Figure 5 As shown, an eighth connecting element d1, a ninth connecting element d2, a tenth connecting element d3 and an eleventh connecting element d4 are connected between the second substrate 200 and the double-sided printed circuit board 300, wherein the eighth connecting element d1 connects the fifteenth solder pad 15 and the thirteenth solder pad 13, the ninth connecting element d2 connects the sixteenth solder pad 16 and the thirteenth solder pad 13, the tenth connecting element d3 connects the seventeenth solder pad 17 and the thirteenth solder pad 13, and the eleventh connecting element d4 connects the eighteenth solder pad 18 and the thirteenth solder pad 13.

[0100] Specifically, the connection element may be a copper column, and the pad and the copper column are connected by silver sintering welding.

[0101] In this embodiment, the connection between the pin and the pad, the power terminal and the pad, and the copper column and the pad are all connected by welding.

[0102] In a specific embodiment, the substrates of several upper-arm depletion-mode gallium nitride chips and the source of the upper-arm enhancement-mode MOSFET chip 110 are connected to the fifth pad 5, and the two are at the same potential; the substrates of several lower-arm depletion-mode gallium nitride chips and the source of the lower-arm enhancement-mode MOSFET chip 210 are connected to the fourteenth pad 14, and the two are at the same potential.

[0103] In this embodiment, the substrates of several upper-arm depletion-mode gallium nitride chips and the source of the upper-arm enhancement-mode MOSFET chip are at the same potential, and the substrates of several lower-arm depletion-mode gallium nitride chips and the source of the lower-arm enhancement-mode MOSFET chip are at the same potential, thereby avoiding the increase in dynamic on-resistance and the reduction in device stability that may be caused by the floating potential of the gallium nitride chip substrate; at the same time, the trapped electrons in the substrate can be reduced in the off state, and the release of trapped electrons in the substrate can be reduced in the on state, thereby ensuring that the gallium nitride device has a more stable dynamic on-resistance.

[0104] See also Figure 6 and Figure 7 , Figure 6 A schematic diagram of current flow of a cascaded GaN module with a stacked structure provided by an embodiment of the present invention, Figure 7 A circuit diagram of a cascaded gallium nitride module with a stacked structure provided by an embodiment of the present invention.

[0105] Specifically, the current is input from the first power terminal Vdc+, flows from the center to the periphery, passes through the first upper bridge arm depletion type gallium nitride chip 120, the second upper bridge arm depletion type gallium nitride chip 130, the third upper bridge arm depletion type gallium nitride chip 140 and the fourth upper bridge arm depletion type gallium nitride chip 150 connected in parallel, and flows to the first pad 1, the second pad 2, the third pad 3 and the fourth pad 4 respectively; the current of the first pad 1 flows to the eleventh pad 11 through the first connecting element a1, and the current of the third pad 3 flows to the eleventh pad 11 through the third connecting element a1. 3 flows to the eleventh pad 11, the current of the second pad 2 flows to the twelfth pad 12 through the second connection element a2, and the current of the fourth pad 4 flows to the twelfth pad 12 through the fourth connection element a4; the current of the eleventh pad 11 and the current of the twelfth pad 12 flow from the periphery to the center, and flow to the upper bridge arm enhancement MOSFET chip 110 through the fifth connection element b1 and flow to the upper bridge arm enhancement MOSFET chip 110 through the sixth connection element b2; the upper bridge arm enhancement MOSFET chip 110 The current of the tenth pad 10 flows through the seventh connection element c1 to the tenth pad 10; the current of the tenth pad 10 flows through the through hole of the double-sided printed circuit board 300 to the thirteenth pad 13; the current of the thirteenth pad 13 flows from the center to the periphery, and flows through the eighth connection element d1, the ninth connection element d2, the tenth connection element d3 and the eleventh connection element d4 to the fifteenth pad 15, the sixteenth pad 16, the seventeenth pad 17 and the eighteenth pad 18 respectively; the current of the fifteenth pad 15 flows through the first lower bridge arm depletion-type gallium nitride chip 22 0 flows to the nineteenth pad 19, the current of the seventeenth pad 17 flows to the nineteenth pad 19 through the third lower bridge arm depletion type gallium nitride chip 240, the current of the sixteenth pad 16 flows to the twentieth pad 20 through the second lower bridge arm depletion type gallium nitride chip 230, the current of the eighteenth pad 18 flows to the twentieth pad 20 through the fourth lower bridge arm depletion type gallium nitride chip 250, and the current of the nineteenth pad 19 and the twentieth pad 20 flows into the lower bridge arm enhancement MOSFET chip 210 and is output from the second power terminal Vdc-.

[0106] See also Figure 8 , Figure 8 A schematic diagram of a process of packaging a cascaded gallium nitride half-bridge module provided in an embodiment of the present invention, the process comprising the following steps:

[0107] Step 1: Prepare a substrate. Specifically, prepare a first substrate 100 and a second substrate 200 according to Figure 2 , Figure 5 The pad structure is prepared and etched.

[0108] Step 2: attaching the chips. Specifically, nano silver solder paste is used as solder, and a silver sintering process is used to connect each chip to the pads of the first substrate 100 and the second substrate 200 .

[0109] Step 3: Install the copper clip. Specifically, the copper clip is soldered to the chip and the pad by reflow soldering to achieve interconnection between the pad and the chip.

[0110] Step 4: Install the connection element. Specifically, the solder uses nano silver solder paste, and the silver sintering process is used to connect the corresponding pads using the connection element.

[0111] Step 5: Plastic encapsulation: Specifically, in a full-fill plastic encapsulation process, the encapsulation body of step 4 is plastic encapsulated using a thermally conductive epoxy resin material.

[0112] Step 6: Laser drilling: Specifically, laser drilling is used to cut the epoxy resin material to expose the connection components for electrical connection.

[0113] Step 7: Print double-sided printed circuits. Figure 3 , Figure 4 A double-sided printed circuit board 300 is printed.

[0114] Step 7: Assembling: Specifically, the double-sided printed circuit board 300, the first substrate 100 and the second substrate 200 are assembled and connected by using a silver sintering process to obtain a cascaded gallium nitride module with a stacked structure.

[0115] In the cascaded GaN module of the present embodiment, a plurality of parallel upper arm depletion-type GaN chips are symmetrically distributed along the symmetry axis, and a plurality of parallel lower arm depletion-type GaN chips are arranged one by one relative to a plurality of upper arm depletion-type GaN chips, thereby realizing a symmetrical layout of the upper arm depletion-type GaN chip and the lower arm depletion-type GaN chip, ensuring the consistency of the interconnection circuit structure between the upper arm GaN chip and the upper arm MOSFET chip, and between the lower arm GaN chip and the lower arm MOSFET chip, and realizing the interconnection of the upper arm cascade power circuit and the lower bridge cascade power circuit by using a double-sided printed circuit board, making the upper arm cascade power circuit and the lower arm cascade power circuit structure inside the module more symmetrical, improving the consistency of the GaN chip and the external circuit parasitic parameters, solving the problem of the consistency of the parallel GaN chips and the matching of the external parameters of the GaN chip and the MOSFET chip, thereby improving the switching performance and reliability of the GaN module.

[0116] In this embodiment, a stacked structure is constructed by using a first substrate, a second substrate and a double-sided printed circuit board, and a gallium nitride module is designed as a four-layer power circuit architecture. The upper bridge arm cascade gallium nitride power circuit is arranged on the first substrate and the first surface of the double-sided printed circuit board, and the lower bridge arm cascade gallium nitride is arranged on the second substrate and the second surface of the double-sided printed circuit board; at the same time, the current direction of the power circuit in the first substrate is opposite to the current direction of the power circuit in the first surface of the double-sided printed circuit board, the current direction of the power circuit in the first surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second surface of the double-sided printed circuit board, and the current direction of the power circuit in the second surface of the double-sided printed circuit board is opposite to the current direction of the power circuit in the second substrate, ensuring that the current directions of the upper and lower power circuits of any two adjacent layers are opposite and the magnetic flux directions are opposite, thereby achieving magnetic flux cancellation between adjacent layers. The four-layer power circuit form not only reduces the parasitic inductance in the module, but also improves the power density of the module, thereby improving the electromagnetic interference (EMI) performance and efficiency of the entire system.

[0117] In summary, the current directions of the upper and lower power loops of any two adjacent layers of the cascaded gallium nitride module of the stacked structure of this embodiment are opposite, and the parasitic inductance of the internal interconnection of the module is reduced by using the magnetic flux cancellation principle; the parasitic parameters between the parallel gallium nitride chips are matched consistently through the middle layer double-sided printed circuit board, further improving the performance; through these structural designs, this embodiment can reduce the loss of the power module switch and improve the overall performance and reliability of the gallium nitride power module.

[0118] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A cascaded gallium nitride module with a stacked structure, characterized in that: include: A first substrate (100), a second substrate (200) and a double-sided printed circuit board (300), wherein the first substrate (100), the double-sided printed circuit board (300) and the second substrate (200) are stacked in sequence and arranged opposite to each other; A surface of the first substrate (100) facing the double-sided printed circuit board (300) is connected to a plurality of upper bridge arm depletion-type gallium nitride chips and an upper bridge arm enhancement-type MOSFET chip (110) via a solder pad; the plurality of upper bridge arm depletion-type gallium nitride chips are symmetrically distributed along a symmetry axis and are mutually connected in parallel; the upper bridge arm enhancement-type MOSFET chip (110) is located between the plurality of upper bridge arm depletion-type gallium nitride chips and is interconnected with the plurality of upper bridge arm depletion-type gallium nitride chips respectively; The pads on the surface of the first substrate (100) include a first pad (1), a second pad (2), a third pad (3), a fourth pad (4), a fifth pad (5), a sixth pad (6), a seventh pad (7), an eighth pad (8) and a ninth pad (9), wherein the first pad (1), the second pad (2), the third pad (3), the fourth pad (4), the fifth pad (5), the sixth pad (6), the seventh pad (7), the eighth pad (8) and the ninth pad (9) are matched in concave and convex directions; the plurality of upper bridge arm depletion-type gallium nitride chips are distributed on the fifth pad (5) in an axisymmetric manner; the plurality of upper bridge arm depletion-type gallium nitride chips are The substrate and the gate are both connected to the fifth pad (5), the drain is connected to the sixth pad (6), and the source is respectively connected to the first pad (1), the second pad (2), the third pad (3), and the fourth pad (4) in a one-to-one correspondence, so as to realize the parallel connection of the plurality of upper bridge arm depletion-type gallium nitride chips; the source of the upper bridge arm enhancement-type MOSFET chip (110) is connected to the fifth pad (5), the gate is connected to the ninth pad (9), and the drain is connected to the seventh pad (7) and the eighth pad (8); the sixth pad (6) is connected to the first power terminal (Vdc+), and the fifth pad (5) is connected to the first Kelvin source pin (Kelvin Source1), the ninth pad (9) is connected to the first gate pin (Gate1); the first pad (1), the second pad (2), the third pad (3), the fourth pad (4), the fifth pad (5), the seventh pad (7), and the eighth pad (8) are correspondingly connected to a plurality of pads on the first surface of the double-sided printed circuit board (300), so as to interconnect the plurality of upper bridge arm depletion-type gallium nitride chips with the upper bridge arm enhancement-type MOSFET chip (110) respectively; A surface of the second substrate (200) facing the double-sided printed circuit board (300) is connected to a plurality of lower bridge arm depletion-type gallium nitride chips and a lower bridge arm enhancement-type MOSFET chip (210) via a solder pad; the plurality of lower bridge arm depletion-type gallium nitride chips are arranged opposite to the plurality of upper bridge arm depletion-type gallium nitride chips one by one and are connected in parallel with each other; the lower bridge arm enhancement-type MOSFET chip (210) is arranged opposite to the upper bridge arm enhancement-type MOSFET chip (110) and is interconnected with the plurality of lower bridge arm depletion-type gallium nitride chips respectively; The pads on the surface of the second substrate (200) include a fourteenth pad (14), a fifteenth pad (15), a sixteenth pad (16), a seventeenth pad (17), an eighteenth pad (18), a nineteenth pad (19), a twentieth pad (20) and a twenty-first pad (21), wherein the fourteenth pad (14), the fifteenth pad (15), the sixteenth pad (16), the seventeenth pad (17), the eighteenth pad (18), the nineteenth pad (19), the twentieth pad (20) and the twenty-first pad (21) are matched in concave and convex manner; the substrates and gates of the plurality of lower bridge arm depletion-type gallium nitride chips are connected to the fourteenth pad (14), and the drains are respectively connected to the fifteenth pad (15), the sixteenth pad (16), the seventeenth pad (17), the eighteenth pad (18), the nineteenth pad (19), the twentieth pad (20) and the twenty-first pad (21). The lower bridge arm depletion-type gallium nitride chips are connected one by one with the pads (18), the source electrodes of the lower bridge arm depletion-type gallium nitride chips located on one side of the symmetry axis are all connected with the nineteenth pad (19), and the source electrodes of the lower bridge arm depletion-type gallium nitride chips located on the other side of the symmetry axis are all connected with the twentieth pad (20), so as to realize the parallel connection of the lower bridge arm depletion-type gallium nitride chips; the source electrode of the lower bridge arm enhancement-type MOSFET chip (210) is connected with the fourteenth pad (14), the gate electrode is connected with the twenty-first pad (21), and the drain electrode is connected with the nineteenth pad (19) and the twenty-third pad (20), so as to interconnect the lower bridge arm enhancement-type MOSFET chip (210) and the several lower bridge arm depletion-type gallium nitride chips respectively; the fourteenth pad (14) is connected with the second power terminal (Vdc-) and the second Kelvin source pin (Kelvin Source2), the twenty-first pad (21) is connected to the second gate pin (Gate2); the fifteenth pad (15), the sixteenth pad (16), the seventeenth pad (17), and the eighteenth pad (18) are connected to pads on the second surface of the double-sided printed circuit board (300); The upper bridge arm enhancement mode MOSFET chip (110) and the plurality of lower bridge arm depletion mode gallium nitride chips are connected via pads on the surface of the double-sided printed circuit board (300); The current direction of the power circuit in the first substrate (100) is opposite to the current direction of the power circuit in the first surface of the double-sided printed circuit board (300), the current direction of the power circuit in the first surface of the double-sided printed circuit board (300) is opposite to the current direction of the power circuit in the second surface of the double-sided printed circuit board (300), the current direction of the power circuit in the second surface of the double-sided printed circuit board (300) is opposite to the current direction of the power circuit in the second substrate (200), the first surface faces the first substrate (100), and the second surface faces the second substrate (200).

2. The cascaded gallium nitride module of the stacked structure according to claim 1, characterized in that: The plurality of upper bridge arm depletion-type gallium nitride chips include a first upper bridge arm depletion-type gallium nitride chip (120), a second upper bridge arm depletion-type gallium nitride chip (130), a third upper bridge arm depletion-type gallium nitride chip (140) and a fourth upper bridge arm depletion-type gallium nitride chip (150), wherein: The first upper bridge arm depletion-type gallium nitride chip (120), the second upper bridge arm depletion-type gallium nitride chip (130), the third upper bridge arm depletion-type gallium nitride chip (140) and the fourth upper bridge arm depletion-type gallium nitride chip (150) are distributed in an axisymmetric manner; The substrate and gate of the first upper bridge arm depletion-type gallium nitride chip (120) are both connected to the fifth pad (5), the source is connected to the first pad (1), and the drain is connected to the sixth pad (6); The substrate and gate of the second upper bridge arm depletion-type gallium nitride chip (130) are both connected to the fifth pad (5), the source is connected to the second pad (2), and the drain is connected to the sixth pad (6); The substrate and gate of the third upper bridge arm depletion-type gallium nitride chip (140) are both connected to the fifth pad (5), the source is connected to the third pad (3), and the drain is connected to the sixth pad (6); The substrate and gate of the fourth upper bridge arm depletion-type gallium nitride chip (150) are both connected to the fifth pad (5), the source is connected to the fourth pad (4), and the drain is connected to the sixth pad (6).

3. The cascaded gallium nitride module of the stacked structure according to claim 1, characterized in that: The pads on the first surface of the double-sided printed circuit board (300) include a tenth pad (10), an eleventh pad (11) and a twelfth pad (12), wherein: The eleventh pad (11) is located on one side of the symmetry axis, connected to the first pad (1), the third pad (3) and the seventh pad (7), and covers a plurality of upper bridge arm depletion-type gallium nitride chips on one side of the symmetry axis; The twelfth pad (12) is located on the other side of the symmetry axis, connected to the second pad (2), the fourth pad (4) and the eighth pad (8), and covers a plurality of upper bridge arm depletion-type gallium nitride chips on the other side of the symmetry axis; The tenth solder pad (10) is located between the eleventh solder pad (11) and the twelfth solder pad (12), and is connected to the solder pad on the second surface of the double-sided printed circuit board (300) through a through hole.

4. The cascaded gallium nitride module of the stacked structure according to claim 3, characterized in that: A first connecting element (a1), a second connecting element (a2), a third connecting element (a3), a fourth connecting element (a4), a fifth connecting element (b1), a sixth connecting element (b2) and a seventh connecting element (c1) are connected between the first substrate (100) and the double-sided printed circuit board (300), wherein: The first connecting element (a1) connects the first solder pad (1) and the eleventh solder pad (11), the second connecting element (a2) connects the second solder pad (2) and the twelfth solder pad (12), the third connecting element (a3) ​​connects the third solder pad (3) and the eleventh solder pad (11), the fourth connecting element (a4) connects the fourth solder pad (4) and the twelfth solder pad (12), the fifth connecting element (b1) connects the seventh solder pad (7) and the eleventh solder pad (11), the sixth connecting element (b2) connects the eighth solder pad (8) and the twelfth solder pad (12), and the seventh connecting element (c1) connects the fifth solder pad (5) and the tenth solder pad (10).

5. The cascaded gallium nitride module of the stacked structure according to claim 1, characterized in that: The plurality of lower bridge arm depletion-type gallium nitride chips include a first lower bridge arm depletion-type gallium nitride chip (220), a second lower bridge arm depletion-type gallium nitride chip (230), a third lower bridge arm depletion-type gallium nitride chip (240) and a fourth lower bridge arm depletion-type gallium nitride chip (250), wherein: The first lower bridge arm depletion-type gallium nitride chip (220), the second lower bridge arm depletion-type gallium nitride chip (230), the third lower bridge arm depletion-type gallium nitride chip (240) and the fourth lower bridge arm depletion-type gallium nitride chip (250) are axially symmetrically distributed and are opposite to the plurality of upper bridge arm depletion-type gallium nitride chips one by one; The gate electrode and substrate of the first lower bridge arm depletion-type gallium nitride chip (220) are both connected to the fourteenth pad (14), the drain electrode is connected to the fifteenth pad (15), and the source electrode is connected to the nineteenth pad (19); The gate electrode and substrate of the second lower bridge arm depletion-type gallium nitride chip (230) are both connected to the fourteenth pad (14), the drain electrode is connected to the sixteenth pad (16), and the source electrode is connected to the twentieth pad (20); The gate electrode and substrate of the third lower bridge arm depletion-type gallium nitride chip (240) are both connected to the fourteenth pad (14), the drain electrode is connected to the seventeenth pad (17), and the source electrode is connected to the nineteenth pad (19); The gate electrode and substrate of the fourth lower bridge arm depletion-type gallium nitride chip (250) are both connected to the fourteenth pad (14), the drain electrode is connected to the eighteenth pad (18), and the source electrode is connected to the twenty-first pad (20).

6. The cascaded gallium nitride module of the stacked structure according to claim 1, characterized in that: The pads on the second surface of the double-sided printed circuit board (300) include a thirteenth pad (13), wherein: The thirteenth pad (13) covers the plurality of lower bridge arm depletion-type gallium nitride chips and the lower bridge arm enhancement-type MOSFET chip (210), is connected to the pad on the first surface of the double-sided printed circuit board (300), and is connected to the fifteenth pad (15), the sixteenth pad (16), the seventeenth pad (17), and the eighteenth pad (18); The thirteenth pad (13) is connected to the third power terminal (Midpoint).

7. The cascaded gallium nitride module of the stacked structure according to claim 6, characterized in that: An eighth connecting element (d1), a ninth connecting element (d2), a tenth connecting element (d3) and an eleventh connecting element (d4) are connected between the second substrate (200) and the double-sided printed circuit board (300), wherein: The eighth connecting element (d1) connects the fifteenth solder pad (15) and the thirteenth solder pad (13), the ninth connecting element (d2) connects the sixteenth solder pad (16) and the thirteenth solder pad (13), the tenth connecting element (d3) connects the seventeenth solder pad (17) and the thirteenth solder pad (13), and the eleventh connecting element (d4) connects the eighteenth solder pad (18) and the thirteenth solder pad (13).

8. The cascaded gallium nitride module of the stacked structure according to claim 1, characterized in that: The substrates of the plurality of upper bridge arm depletion-type gallium nitride chips and the source of the upper bridge arm enhancement-type MOSFET chip (110) have the same potential; The substrates of the plurality of lower bridge arm depletion-type gallium nitride chips and the source of the lower bridge arm enhancement-type MOSFET chip (210) have the same potential.

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