A micro-power-saving and computation-free data transmission and distributed flash memory encryption and decryption system

Abstract

The present invention discloses a micro-power consumption free calculation data transmission and distributed flash memory encryption and decryption system, belonging to the field of signal conversion circuit and signal modulation. The present invention includes an antenna, an envelope detection, a synchronous clock generation circuit, an internal clock, a free calculation encryption and decryption circuit, a distributed flash memory chip, an XOR gate and a reflection circuit. When downlinking, the terminal receives the radio signal and obtains the standard computer bus data that can be recognized by the sensor through demodulation and decryption; when uplinking, the data uploaded by the sensor is encrypted, and then the encrypted data and the clock are modulated, and finally modulated to the carrier sent by the gateway through the backscattering circuit and transmitted back to the gateway. The present invention stores massive sensor data through distributed flash memory; solves the problem of sensitive data leakage through encryption and decryption circuits; and can directly output the physical bus data that the sensor chip can recognize through the energy drive of the radio signal, without the need for a processor and 4 times more efficient than the traditional demodulation method.

Description

Technical Field

[0001] The present invention relates to the field of radio signal conversion circuits and signal modulation, and in particular to a micro-power consumption and calculation-free data transmission and distributed flash memory encryption and decryption system. Background Art

[0002] At present, traditional IoT terminal devices often consume milliwatts of power, which seriously affects the performance and life of the terminal. Terminal devices require frequent battery replacement and maintenance, which increases network maintenance costs. In addition, the processor is one of the most expensive components in embedded systems. If the processor on the terminal can be removed, the hardware cost can be greatly reduced and the service life of the terminal can be extended, thereby effectively reducing the subsequent maintenance costs. However, in physical network terminals, sensor chips can only directly recognize standard computer bus signals. Therefore, removing the processor in the IoT terminal will lead to a challenge: how to convert the wireless signal received by the terminal into a standard computer bus signal that the sensor chip can recognize.

[0003] Currently, sensor chips in physical network terminals can only output standard computer bus signals. However, when passive communication backscatter is required, the traditional method is to reflect a single baseband signal. If there is no processor in the IoT terminal, there will be a challenge: how to transmit clock and data signals to the gateway at the same time.

[0004] The massive deployment of Internet of Things (IoT) terminal devices has become a key factor in promoting the development of the Internet of Everything. With the surge in the number of IoT terminal devices, the storage of massive data and the security of sensitive sensor data have become increasingly prominent. Distributed flash memory, with its high reliability and high efficiency, can ensure the integrity and recoverability of data through data redundancy and collaboration between nodes, which enables IoT terminals to process large amounts of data in real time and quickly. In addition, distributed flash memory can also protect the security of sensor data and prevent data leakage and illegal access. Therefore, distributed flash memory can provide more secure and efficient massive data storage for IoT terminals. Summary of the invention

[0005] The present invention aims to provide a micro-power consumption and computation-free data transmission and distributed flash memory encryption and decryption system, which can realize four functions: converting the downlink radio control signal sent by the gateway into a standard computer bus signal (including data signal and clock signal) that can be recognized by the SPI sensor chip to drive the sensor to operate; after the clock signal and data signal output by the sensor are compiled, they are modulated onto the carrier signal sent by the gateway through a passive communication backscattering circuit, and then transmitted back to the gateway to complete the data uplink; using hardware logic circuits to realize concise and fast communication encryption; and realizing the storage of massive sensor data through distributed flash memory chips.

[0006] The present invention solves the technical problem and adopts the following technical solution: a micro-power consumption free-computation data transmission and distributed flash memory encryption and decryption system, including an antenna, an envelope detector, a synchronous clock generation circuit, an internal clock, a free-computation encryption and decryption circuit, a distributed flash memory chip, an XOR gate and a backscattering circuit. When downlinking, the terminal receives the signal and then demodulates and decrypts it to obtain standard computer bus data that can be recognized by the sensor; when uplinking, the data uploaded by the sensor is first encrypted, and then the encrypted data and the clock are modulated, and finally modulated to the carrier sent by the gateway through a reflection circuit and transmitted back to the gateway.

[0007] Furthermore, the traditional gateway encodes data into a wireless signal by using pulse coding to compile the data signal and the clock signal together. Using this coding method, it takes 5t per unit time to compile data 1 and 3t per unit time to compile data 0. The present invention places the clock signal on the terminal, and the coding time and data are 1:1, which increases the encoding and decoding speed by 4 times compared with the past (if the usage frequency of data 1 and 0 is the same).

[0008] Furthermore, the envelope detector is composed of a radio frequency rectification circuit and a threshold determination circuit.

[0009] Furthermore, the RF rectification circuit includes a third capacitor, a third diode, a fourth diode, a fourth capacitor, a fifth resistor, a fifth capacitor and a fifth comparator, one end of the third capacitor is connected to the receiving antenna, and the other end is connected to the input end of the third diode, the input end of the fourth diode is grounded, and the output end is connected to the input end of the third diode, one end of the fourth capacitor is grounded, and the other end is connected to the output end of the third diode, the output end of the third diode is connected to the threshold judgment circuit, one end of the fifth resistor is connected to the output end of the third diode, and the other end is connected to the reverse input end of the fifth comparator; one end of the fifth capacitor is grounded, and the other end is connected to the reverse input end of the fifth comparator.

[0010] Furthermore, the synchronous clock generating circuit includes a first integration circuit, a second integration circuit and a window comparator, the input end of the first integration circuit is connected to the output end of the envelope detector, the output end is connected to the input end of the window comparator, the output end of the window comparator is connected to the input end of the second integration circuit, and the output end of the second integration circuit is connected to the internal clock.

[0011] Furthermore, the first integration circuit includes a first resistor, a second resistor, a first capacitor, and a first comparator, the input end of the first resistor is connected to the baseband signal sent by the envelope detector, and the other end is connected to the inverting input end of the first comparator, one end of the second resistor is connected to the ground wire, and the other end is connected to the non-inverting input end of the first comparator, one end of the first capacitor is connected to the reverse input end of the first comparator, and the other end is connected to the output end of the first comparator.

[0012] Furthermore, the window comparator includes a second comparator, a third comparator, a first diode, and a second diode, the reverse input terminal of the second comparator is connected to the Vref1 voltage, the forward input terminal is connected to the output terminal of the first comparator, and the output terminal is connected to the input terminal of the first diode, the reverse input terminal of the third comparator is connected to the output terminal of the first comparator, the forward input terminal is connected to the Vref2 voltage, and the output terminal is connected to the input terminal of the second diode, and the output terminals of the first diode and the second diode are connected to the input terminal of the second integration circuit.

[0013] Furthermore, the second integration circuit includes a third resistor, a fourth resistor, a second capacitor, and a fourth comparator, wherein an input end of the third resistor is connected to the output end of the window comparator, and the other end is connected to the inverting input end of the fourth comparator, one end of the fourth resistor is connected to the ground wire, and the other end is connected to the non-inverting input end of the fourth comparator, and one end of the second capacitor is connected to the reverse input end of the first comparator, and the other end is connected to the output end of the fourth comparator.

[0014] Furthermore, the computation-free encryption and decryption circuit includes eight D flip-flops, an XOR gate, and a distributed flash memory chip. The C1 ends of the eight D flip-flops are connected to the internal clock, the 1D end of the D1 flip-flop is connected to the output end of the envelope detection circuit, and the 1D ends of the other flip-flops are connected to the output end of the previous D flip-flop in sequence. The distributed flash memory chip and the D flip-flop are output in parallel to the XOR gate, and then output serially from the XOR gate.

[0015] Furthermore, the reflection circuit includes an XOR gate, a P-MOS, a ground wire and an antenna, one input end of the XOR gate is connected to the data signal output end of the sensor, the other input end is connected to the output end of the internal clock, the output end of the XOR gate is connected to the gate of the P-MOS, the drain is connected to the antenna, and the source is connected to the ground wire.

[0016] The beneficial effect of the present invention is that, through the above-mentioned micro-power-consumption-free data transmission and distributed flash memory encryption and decryption system, the calculation and control functions are moved from the processor to the gateway, and the high-power processor module on the terminal device is removed. The terminal device only needs to retain the necessary perception and wireless communication functions. Through the envelope detector, the synchronous clock generation circuit and the internal clock, the sensor chip can be directly output by the energy drive of the wireless signal to identify the physical bus data, which is 4 times more efficient than the traditional PIE encoding and decoding efficiency. Through the calculation-free encryption and decryption circuit and the distributed flash memory chip, the hardware is used to realize the low-power and high-efficiency encrypted communication between the gateway and the terminal sensor, avoiding direct plaintext transmission and realizing the storage of massive sensor data. In addition, the sensor outputs the bus data under the drive of the internal clock, and realizes the frequency shift modulation by performing the XOR operation with the subcarrier through the XOR gate. This makes the frequency of the output signal the sum of the bus data frequency, the bus clock frequency and the carrier frequency. Finally, the signal is modulated on the wireless signal through the reflection circuit and sent to the gateway, realizing the return of the wireless signal containing the clock and bus data. This effectively reduces the overall power consumption of the terminal from milliwatts to microwatts, greatly increasing the service life of the terminal while saving a lot of subsequent maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the overall structure of a micro-power consumption and computation-free data transmission and distributed flash memory encryption and decryption system according to an embodiment of the present invention;

[0018] Figure 2 Schematic diagram of a synchronous clock generating circuit in an embodiment of the present invention.

[0019] Figure 3 It is the encoding and decoding mechanism in the embodiment of the present invention (the upper part is the encoding mechanism and the lower part is the decoding mechanism).

[0020] Figure 4 This is a calculation-free encryption and decryption circuit in an embodiment of the present invention.

[0021] Among them, A1 represents the antenna receiving end, A2 represents the antenna transmitting end, R1 represents the first resistor, R2 represents the second resistor, C1 represents the first capacitor, U1A represents the first comparator, Vref1 represents the first comparator voltage, Vref2 represents the second comparator voltage, U2 represents the second comparator, U3 represents the third comparator, D1 represents the first diode, D2 represents the second diode, R3 represents the third resistor, R4 represents the fourth resistor, C2 represents the second capacitor, U4A represents the fourth comparator, C3 is the third capacitor, D3 is the third diode, D4 ​​is the fourth diode, C4 is the fourth capacitor, R5 is the fifth resistor, C5 is the fifth capacitor, and U5 is the fifth comparator. DETAILED DESCRIPTION

[0022] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0023] The present invention proposes a micro-power consumption free calculation data transmission and distributed flash memory encryption and decryption system, and a schematic diagram of its overall structure, wherein the input end of the envelope detector is connected to the antenna to receive the wireless signal sent by the gateway, and the output end is respectively connected to the input end of the decryption circuit and the input end of the synchronous clock generating circuit, the output end of the synchronous clock generating circuit is connected to the input end of the internal clock, the output end of the internal clock is connected to the sensor, the input end of the free calculation encryption and decryption circuit and one input end of the XOR gate, the output end of the decryption circuit is connected to the sensor, the output end of the sensor is connected to the input end of the encryption circuit, the output end of the encryption circuit is connected to the other input end of the XOR gate, the output end of the XOR gate is connected to the passive reflection circuit and connected to the antenna.

[0024] The above circuit is set in an IoT terminal without a processor, which can enable encrypted communication between the terminal and the gateway; the sensor chip directly output by the energy drive of the wireless signal can identify the physical bus data, without the need for a terminal processor and 4 times more efficient than the traditional demodulation method; the data output by the sensor is encrypted and modulated on the carrier sent by the gateway and transmitted back to the gateway, which is suitable for IoT terminals without a processor.

[0025] Example

[0026] In this embodiment, the gateway sends the data signal to the receiving antenna of the terminal in the form of a wireless point signal, and then obtains the data signal in the wireless signal through an envelope detector. SPI bus, the sensor needs to add a clock to effectively receive data, so a synchronous clock generation circuit and an internal clock are introduced. In addition, the terminal returns data to the gateway through an XOR gate, a backscatter circuit, and a carrier signal sent by the gateway.

[0027] For the synchronous clock generating circuit, its purpose is to receive the data signal sent by the gateway. If the input requirements of the synchronous clock generating circuit can be met, it can activate the internal clock behind it, allowing the terminal to prepare to receive data and provide a clock signal.

[0028] In this embodiment, the synchronous clock generating circuit includes a first integration circuit, a second integration circuit and a window comparator, wherein the input end of the first integration circuit is connected to the output end of the envelope detector, the output end is connected to the input end of the window comparator, the output end of the window comparator is connected to the input end of the second integration circuit, and the output end of the second integration circuit is connected to the internal clock.

[0029] The first integration circuit includes a first resistor, a second resistor, a first capacitor, and a first comparator, wherein the input end of the first resistor is connected to the baseband signal sent by the envelope detector, and the other end is connected to the inverting input end of the first comparator, one end of the second resistor is connected to the ground line, and the other end is connected to the non-inverting input end of the first comparator, one end of the first capacitor is connected to the reverse input end of the first comparator, and the other end is connected to the output end of the first comparator. The window comparator includes a second comparator, a third comparator, a first diode, and a second diode, wherein the reverse input end of the second comparator is connected to the Vref1 voltage, the forward input end is connected to the output end of the first comparator, and the output end is connected to the input end of the first diode, the reverse input end of the third comparator is connected to the output end of the first comparator, the forward input end is connected to the Vref2 voltage, and the output end is connected to the input end of the second diode, and the output ends of the first diode and the second diode are connected to the input end of the second integration circuit. The second integration circuit includes a third resistor, a fourth resistor, a second capacitor, and a fourth comparator. The input end of the third resistor is connected to the output end of the window comparator, and the other end is connected to the inverting input end of the fourth comparator. One end of the fourth resistor is connected to the ground wire, and the other end is connected to the non-inverting input end of the fourth comparator. One end of the second capacitor is connected to the input end of the first comparator, and the other end is connected to the output end of the fourth comparator. The envelope detection circuit includes a third capacitor, a third diode, a fourth diode, a fourth capacitor, a fifth resistor, a fifth capacitor, and a fifth comparator. One end of the third capacitor is connected to the receiving antenna, and the other end is connected to the input end of the third diode. The input end of the fourth diode is grounded and the output end is connected to the input end of the third diode. One end of the fourth capacitor is grounded, and the other end is connected to the output end of the third diode. The output end of the third diode is connected to the threshold discrimination circuit. One end of the fifth resistor is connected to the output end of the third diode, and the other end is connected to the inverting input end of the fifth comparator. One end of the fifth capacitor is grounded, and the other end is connected to the inverting input end of the fifth comparator.

[0030] Here, an envelope detection circuit is used to process the wireless signal sent by the gateway, and the RF rectifier circuit is used to extract the envelope information of the carrier signal. The diode uses its unidirectional voltage conductivity to convert the AC signal into a DC signal. The capacitor acts as a buffer for the signal to extract the signal envelope information. The threshold discrimination circuit generates a digital signal representing the 0 and 1 symbols based on the envelope signal.

[0031] After passing through the envelope detection circuit, the digital signal first passes through the synchronous clock generation circuit. When the gateway sends an integration signal of a specific length, the output of the first integration circuit will meet the requirements of the window comparator before it is sent to the second integration circuit. The subsequent internal clock can be activated only when a certain threshold is reached, and then the clock signal and data signal are combined to obtain a standard SPI bus signal, so that the subsequent sensor equipment can operate normally.

[0032] The role of the window comparator in the synchronous clock generation circuit here is to avoid the possibility of instability of the integral voltage in the integral circuit. If a single limit judgment is used, it may be falsely triggered, and the value of the integral voltage changes back and forth at the threshold boundary. This is why two integral circuits and the overall design are used here.

[0033] Secondly, the clock signal inside the sensor is used to drive the sensor so that it can output data that conforms to the standard computer bus. These bus data are processed by the XOR gate (XOR) and XORed with the clock signal to achieve frequency conversion. The output signal frequency of the XOR gate (XOR) is equal to the sum of the bus data frequency and the clock signal frequency. The role of the clock signal is to provide the signal required for frequency conversion.

[0034] The modulation signal in the previous step will control the on and off states of the PMOS. When the modulation signal is low, the PMOS is turned off, and when the modulation signal is high, the PMOS is turned on, thereby modulating the baseband signal sent by the antenna part and the gateway and reflecting it back to the gateway.

[0035] The main idea of ​​the calculation-free encryption and decryption circuit here is that the gateway randomly generates a binary key of the corresponding number of bits according to the actual number of bits of information data (8 bits are used as an example here). The gateway sends this key to the terminal, and the terminal saves it in the distributed flash memory chip. The subsequent encryption and decryption uses a serial-in and parallel-out shift register composed of D flip-flops. The C1 of the D flip-flop uses the internal clock CLK. Finally, the data and the key are output in parallel to perform XOR operations for encryption and decryption. The calculation-free encryption and decryption circuit here can be reused, that is, it can be used for encryption and decryption.

[0036] In summary, through the micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system of this embodiment, it is realized that the sensor chip can identify the physical bus data by the energy drive of the wireless signal, and the terminal modulates the sensor data signal and clock signal back to the gateway, and the encrypted communication between the gateway and the terminal sensor is realized as a whole, thereby realizing low power consumption, high efficiency, and high reliability of chip bottom signal encoding and decoding. In addition, the introduction of distributed flash memory chips solves the problems of storage and data security of massive sensor data.

Claims

1. A micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system, characterized in that: It includes an antenna, an envelope detection circuit composed of a radio frequency rectification circuit and a threshold discrimination circuit, a synchronous clock generation circuit composed of an integration circuit and a window comparator, an internal clock, a sensor, a calculation-free encryption and decryption circuit, and a passive reflection circuit composed of an XOR gate and a P-MOS; The computation-free encryption and decryption circuit is characterized in that it is composed of eight D flip-flops, an XOR gate and a distributed flash memory chip; the C1 end of the eight D flip-flops is connected to the internal clock, the 1D end of the D1 flip-flop is connected to the output end of the envelope detection circuit, and the 1D ends of other flip-flops are sequentially connected to the output end of the previous D flip-flop; the distributed flash memory chip and the D flip-flop are output in parallel to the XOR gate, and then output in series from the XOR gate; the distributed flash memory chip stores the key to protect the sensitive sensor data of the massive sensor nodes; in addition, the distributed flash memory chip is also mounted on the sensor to store the massive sensor data; The connection characteristics of the system are that the input end of the envelope detection circuit is connected to the antenna for receiving the radio signal sent by the gateway, and the output end is respectively connected to the input end of the decryption circuit and the input end of the synchronous clock generation circuit; the output end of the synchronous clock generation circuit is connected to the input end of the internal clock; the output end of the internal clock is respectively connected to the sensor, the input end of the calculation-free encryption and decryption circuit and one input end of the XOR gate; the output end of the decryption circuit is connected to the sensor; the output end of the sensor is connected to the input end of the encryption circuit; the output end of the encryption circuit is connected to the other input end of the XOR gate; the output end of the XOR gate is connected to the passive reflection circuit and connected to the antenna.

2. A micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system according to claim 1, characterized in that: The synchronous clock generating circuit comprises a first integration circuit, a second integration circuit and a window comparator, wherein the input end of the first integration circuit is connected to the output end of the envelope detector, the output end is connected to the input end of the window comparator, the output end of the window comparator is connected to the input end of the second integration circuit, and the output end of the second integration circuit is connected to the internal clock.

3. A micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system according to claim 2, characterized in that: The first integration circuit includes a first resistor, a second resistor, a first capacitor, and a first comparator. The input end of the first resistor is connected to the baseband signal sent by the envelope detector, and the other end is connected to the inverting input end of the first comparator. One end of the second resistor is connected to the ground wire, and the other end is connected to the non-inverting input end of the first comparator. One end of the first capacitor is connected to the inverting input end of the first comparator, and the other end is connected to the output end of the first comparator.

4. A micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system according to claim 2, characterized in that: The window comparator includes a second comparator, a third comparator, a first diode, and a second diode. The reverse input terminal of the second comparator is connected to the Vref1 voltage, the forward input terminal is connected to the output terminal of the first comparator, and the output terminal is connected to the input terminal of the first diode. The reverse input terminal of the third comparator is connected to the output terminal of the first comparator, the forward input terminal is connected to the Vref2 voltage, and the output terminal is connected to the input terminal of the second diode. The output terminals of the first diode and the second diode are connected to the input terminal of the second integration circuit.

5. The micro-power consumption-free computing data transmission and distributed flash memory encryption and decryption system according to claim 2 is characterized in that: The second integration circuit includes a third resistor, a fourth resistor, a second capacitor, and a fourth comparator. The input end of the third resistor is connected to the output end of the window comparator, and the other end is connected to the inverting input end of the fourth comparator. One end of the fourth resistor is connected to the ground wire, and the other end is connected to the non-inverting input end of the fourth comparator. One end of the second capacitor is connected to the inverting input end of the first comparator, and the other end is connected to the output end of the fourth comparator.

6. The micro-power consumption free computing data transmission and distributed flash memory encryption and decryption system according to claim 1 is characterized in that: The sensor is based on the SPI protocol, and combines the clock signal in the internal clock with the physical bus data obtained by the calculation-free decryption circuit to obtain a standard SPI bus signal, so that the sensor device can operate normally.

7. The micro-power consumption-free computing data transmission and distributed flash memory encryption and decryption system according to claim 1 is characterized in that: The passive reflection circuit includes an XOR gate, a P-MOS, a ground wire and an antenna. One input end of the XOR gate is connected to the data signal output end of the sensor, and the other input end is connected to the output end of the internal clock. The output end of the XOR gate is connected to the gate of the P-MOS, the drain is connected to the antenna, and the source is connected to the ground wire.

Images