A semiconductor structure and a manufacturing method thereof, memory

Abstract

The embodiments of the present disclosure disclose a semiconductor structure, a manufacturing method thereof and a memory. The semiconductor structure comprises a substrate, a trench in the substrate, and a stack layer in the trench and extending above the substrate, wherein the stack layer comprises at least two electrode layers and a dielectric layer between adjacent electrode layers. The semiconductor structure further comprises a contact portion electrically connected to one of the electrode layers, wherein a projection of the contact portion in a direction perpendicular to a plane in which the substrate lies is between projections of adjacent trenches.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure, a manufacturing method thereof, and a memory. Background Art

[0002] With the development of semiconductor technology, vertical interconnect stacking based on through-silicon via (TSV) technology, which allows different chip types to be packaged together via an interposer, has gradually led the trend in packaging technology development with its key technical advantages of short-distance interconnection and high-density integration. With the increasing consumer demand for smaller, faster, and more reliable electronic products, further improving the integration and performance of semiconductor devices has become a pressing issue. Summary of the Invention

[0003] In view of this, the embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory in order to solve or improve the technical problems existing in the background technology.

[0004] According to a first aspect of an embodiment of the present disclosure, there is provided a semiconductor structure, comprising:

[0005] a substrate and a groove within the substrate;

[0006] a stacked layer located in the trench and extending above the substrate; the stacked layer comprising at least two electrode layers and a dielectric layer located between adjacent electrode layers;

[0007] A contact portion is electrically connected to one of the electrode layers, wherein, in a direction perpendicular to the plane where the substrate is located, a projection of the contact portion is located between projections of adjacent grooves.

[0008] In some embodiments, there are multiple contact portions, and the multiple contact portions are arranged in at least one row.

[0009] In some embodiments, there are multiple grooves, and the multiple grooves are arranged in at least one row; wherein the row arrangement direction of the contact portions is parallel to the row arrangement direction of the grooves.

[0010] In some embodiments, a row of the contact portions is located between two adjacent rows of the trenches.

[0011] In some embodiments, along a direction away from the bottom of the groove, the stacked layers sequentially include a first electrode layer, a second electrode layer, and a third electrode layer, and the bottom of the contact portion extends to different positions in the stacked layers to connect to the corresponding electrode layers.

[0012] In some embodiments, the contact portion connected to the first electrode layer is defined as a first contact portion, the contact portion connected to the second electrode layer is defined as a second contact portion, and the contact portion connected to the third electrode layer is defined as a third contact portion, wherein:

[0013] The plurality of first contact portions are arranged into at least one first contact portion row;

[0014] The plurality of second contact portions are arranged into at least one second contact portion row;

[0015] The plurality of third contact portions are arranged into at least one third contact portion row; wherein,

[0016] The first contact row, the second contact row, and the third contact row are parallel to each other.

[0017] In some embodiments, the first contact row is disposed adjacent to the third contact row.

[0018] In some embodiments, one row of the first contacts is adjacent to two rows of the third contacts; or one row of the third contacts is adjacent to two rows of the first contacts.

[0019] In some embodiments, the semiconductor structure further comprises:

[0020] The conductive layer includes a first conductive layer and a second conductive layer; the first conductive layer electrically connects the first contact portion and the third contact portion; and the second conductive layer electrically connects the second contact portion.

[0021] In some embodiments, in a direction perpendicular to the plane of the substrate, a projection of the conductive layer completely covers projections of the first contact portion, the second contact portion, and the third contact portion.

[0022] According to a second aspect of an embodiment of the present disclosure, a memory is provided, comprising the semiconductor structure described in any one of the above embodiments.

[0023] According to a third aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0024] providing a substrate;

[0025] forming a groove in the substrate;

[0026] forming a stacked layer, the stacked layer being located in the groove and extending above the substrate; the stacked layer comprising at least two electrode layers and a dielectric layer located between adjacent electrode layers;

[0027] A contact portion is formed, the contact portion being electrically connected to one of the electrode layers, wherein, in a direction perpendicular to the plane where the substrate is located, a projection of the contact portion is located between projections of adjacent grooves.

[0028] In some embodiments, forming the stacked layers includes:

[0029] forming an isolation layer covering the inner wall of the groove and the surface of the substrate;

[0030] A first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer are sequentially formed on the isolation layer; the first electrode layer, the first dielectric layer, the second electrode layer, the second dielectric layer and the third electrode layer are defined as the stacked layer.

[0031] In some embodiments, forming the contact portion includes:

[0032] forming a first dielectric layer, wherein the first dielectric layer covers the stacked layers;

[0033] Etching the first dielectric layer, the third electrode layer, the second dielectric layer, the second electrode layer, and the first dielectric layer to form a first opening, wherein the first opening exposes an upper surface of the first electrode layer;

[0034] Etching the first dielectric layer, the third electrode layer, and the second dielectric layer to form a second opening, wherein the second opening exposes an upper surface of the second electrode layer;

[0035] The first dielectric layer is etched to form a third opening, where the third opening exposes an upper surface of the third electrode layer.

[0036] In some embodiments, forming the contact portion further includes:

[0037] forming a second dielectric layer, wherein the second dielectric layer at least fills the first opening, the second opening, and the third opening;

[0038] Etching portions of the second dielectric layer located within the first opening, the second opening, and the third opening to form a first contact hole, a second contact hole, and a third contact hole, respectively, and the remaining portion of the second dielectric layer on sidewalls of the first opening, the second opening, and the third opening is defined as a protective layer;

[0039] A first contact portion, a second contact portion, and a third contact portion are formed in the first contact hole, the second contact hole, and the third contact hole, respectively.

[0040] In some embodiments, after forming the contact portion, the method further includes:

[0041] forming a conductive material layer;

[0042] The conductive material layer is etched to form a first conductive layer and a second conductive layer, wherein the first conductive layer covers the first contact portion and the third contact portion; and the second conductive layer covers the second contact portion.

[0043] An embodiment of the present disclosure provides a semiconductor structure comprising: a substrate and a trench located within the substrate; a stacked layer located within the trench and extending above the substrate; the stacked layer comprising at least two electrode layers and a dielectric layer located between adjacent electrode layers; and a contact portion electrically connected to one of the electrode layers, wherein, in a direction perpendicular to the plane of the substrate, the projection of the contact portion is located between the projections of adjacent trenches. In the present disclosure, in a direction perpendicular to the plane of the substrate, the projection of the contact portion is located between the projections of adjacent trenches. By locating the contact portion electrically connected to the electrode layer in the array region where the trenches are located, compared to the conventional practice of locating the contact portion separately at a peripheral position away from the array region where the trenches are located, the occupied area can be reduced, thereby improving wafer area utilization and thereby increasing integration. In addition, locating the contact portion between the trenches facilitates increasing the number of contacts within the array region where the trenches are located as much as possible without increasing the occupied area, thereby increasing the contact area between the contact portion and the conductive lines interconnected therewith, thereby reducing contact resistance, thereby improving signal delay and enhancing the performance of the semiconductor device.

[0044] Additional aspects and advantages of the present disclosure will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 is a schematic top view of a semiconductor structure according to an embodiment of the present disclosure;

[0046] Figure 2 The semiconductor structure of an embodiment of the present disclosure is Figure 1 Schematic diagram of vertical section along line AA';

[0047] Figure 3 The semiconductor structure of an embodiment of the present disclosure is Figure 1 Schematic diagram of vertical section along line BB';

[0048] Figure 4 The semiconductor structure of an embodiment of the present disclosure is Figure 1 Schematic diagram of vertical section along CC' line;

[0049] Figure 5 is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0050] Figure 6is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0051] Figure 7 is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0052] Figure 8 is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0053] Figure 9 is a schematic top view of a semiconductor structure according to another embodiment of the present disclosure;

[0054] Figure 10 The flowchart of the method for manufacturing a semiconductor structure according to one embodiment of the present disclosure is shown.

[0055] Reference numerals:

[0056] 10-substrate; 101-groove; 102-isolation layer; 103-first dielectric layer; 104-second dielectric layer; 105-accommodation cavity; 11-stacked layer; 12-electrode layer; 121-first electrode layer; 122-second electrode layer; 123-third electrode layer; 13-dielectric layer; 131-first dielectric layer; 132-second dielectric layer; 14-contact portion; 141-first contact portion; 142-second contact portion; 143-third contact portion; 15-first contact portion row; 16-second contact portion row; 17-third contact portion row; 18-conductive layer; 181-first conductive layer; 182-second conductive layer; 19-first opening; 20-second opening; 21-third opening; 22-first contact hole; 23-second contact hole; 24-third contact hole; 25-protective layer. DETAILED DESCRIPTION

[0057] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0058] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0059] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0060] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0061] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0062] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0063] In vertically interconnected stacked packages based on through-silicon-via (TSV) technology, different types of chips can be packaged together through an interposer, offering the key technical advantages of short-distance interconnection and high-density integration. Deep trench capacitors (DTCs) are placed within the interposer, acting as decoupling capacitors to shield electromagnetic noise within the device, stabilize dynamic voltage, and stabilize power supply. The multiple electrode layers of a DTC are located on the inner walls of the trench and extend above the substrate. The interconnect structure of the electrode layers is typically located in the peripheral area outside the DTC trench array, thus occupying a larger area of ​​the wafer and limiting the increase in integration. Furthermore, the interconnect structure has a relatively limited number of contact points, resulting in higher contact resistance and signal delays, which in turn affect the performance of the semiconductor device.

[0064] Based on this, the present disclosure provides a semiconductor structure, see the attached Figure 1 To the attached Figure 4 , among which, Figure 2 To the attached Figure 4 Along the Figure 1 A schematic vertical cross-sectional view of lines AA', BB', and CC' in FIG. 1 shows a semiconductor structure including:

[0065] A substrate 10 and a groove 101 located in the substrate 10;

[0066] A stacked layer 11 located in the trench 101 and extending above the substrate 10; the stacked layer 11 includes at least two electrode layers 12 and a dielectric layer 13 located between adjacent electrode layers 12;

[0067] The contact portion 14 is electrically connected to one electrode layer 12 , wherein, in a direction perpendicular to the plane where the substrate 10 is located, a projection of the contact portion 14 is located between projections of adjacent trenches 101 .

[0068] In a direction perpendicular to the plane of the substrate 10, the projection of the contact portion 14 is located between the projections of adjacent trenches 101. By positioning the contact portion 14 electrically connected to the electrode layer 12 in the array region where the trenches 101 are located, the occupied area can be reduced, compared to the conventional arrangement of the contact portion 14 at a peripheral position away from the array region where the trenches 101 are located, thereby improving wafer area utilization and thereby increasing the degree of integration. In addition, positioning the contact portion 14 between the trenches 101 facilitates increasing the number of contact portions 14 within the array region where the trenches 101 are located without additionally increasing the occupied area, thereby increasing the contact area between the contact portion 14 and the conductive lines interconnected therewith, thereby reducing contact resistance, thereby improving signal delay, and enhancing the performance of the semiconductor device.

[0069] In practice, the substrate 10 may include, but is not limited to, a single-element semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon-germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, the substrate 10 comprises a doped or undoped silicon substrate. The horizontal cross-sectional shape of the trench 101 may include a circle, an ellipse, a rectangle, a rounded rectangle, or any other closed two-dimensional shape. The depth of the trench 101 may be set according to actual needs. In some specific embodiments, the depth of the trench 101 may range from 10 to 20 microns, including end values, such as 12 microns, 15 microns, 16 microns, or 18 microns. In this way, the deep trench capacitor (DTC) formed in the trench 101 can have a larger capacitance value and a higher breakdown voltage. The material of the electrode layer 12 may include, but is not limited to, doped silicon, polysilicon, or a metal material, such as one or more combinations of copper, tungsten, aluminum, titanium, titanium nitride, tantalum, or tantalum nitride. The material of the dielectric layer 13 may include, but is not limited to, a dielectric metal oxide material with a relatively high dielectric constant, such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide, or a combination thereof. The use of a material with a high dielectric constant helps reduce leakage current within the deep trench capacitor (DTC), thereby increasing the capacitance of the deep trench capacitor (DTC). The material of the contact portion 14 may include, but is not limited to, a metal material, such as any combination of one or more of tungsten, copper, aluminum, nickel, gold, and silver.

[0070] In some specific embodiments, see the attached Figure 2 To the attached Figure 4 , an isolation layer 102 is also included between the substrate 10 and the stacked layer 11.

[0071] The isolation layer 102 can isolate the substrate 10 from the electrode layer 12 in the stacked layer 11 to prevent the conductive material in the electrode layer 12 from diffusing into the substrate 10 and affecting the performance of the semiconductor structure.

[0072] In actual operation, the material of the isolation layer 102 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0073] In some embodiments, see Appendix Figure 2 To the attached Figure 4 The stacked layer 11 located in the trench 101 also includes a receiving cavity 105. The semiconductor structure also includes: a first dielectric layer 103, wherein the first dielectric layer 103 fills the receiving cavity 105 and covers at least a portion of the stacked layer 11 located above the substrate 10; and a second dielectric layer 104, wherein the second dielectric layer 104 surrounds the sidewalls of the contact portion 14 and covers the upper surface of the first dielectric layer 103.

[0074] The first dielectric layer 103 and the second dielectric layer 104 can serve as interlayer dielectric layers to achieve insulation isolation between the device located on the substrate 10 and the upper conductive layer. The second dielectric layer 104 surrounding the sidewall of the contact portion 14 can achieve electrical connection between a contact portion and a corresponding electrode layer, while being insulated from other electrode layers, thereby ensuring the reliability of the electrical performance of the semiconductor structure.

[0075] In actual operation, the materials of the first dielectric layer 103 and the second dielectric layer 104 may include but are not limited to silicon oxide, silicon oxynitride, silicon oxycarbide, doped or undoped silicate glass or organic silicate glass, etc. The materials of the first dielectric layer 103 and the second dielectric layer 104 may be the same or different.

[0076] In some embodiments, see Appendix Figure 1 There are multiple contact portions 14 , and the multiple contact portions 14 are arranged in at least one row.

[0077] The greater the number of contacts 14, the greater the contact area between the contacts 14 and the interconnected conductive traces, reducing contact resistance and thereby improving semiconductor device performance. Arranging multiple contacts 14 in at least one row reduces the difficulty of manufacturing the contacts 14 and simplifies the routing of the conductive traces interconnected with the contacts 14, further reducing the difficulty of routing the conductive traces.

[0078] In actual operation, the row direction of the plurality of contact portions 14 can be along any direction parallel to the upper surface of the substrate 10. Figure 1 In the direction indicated by the arrow in the figure, the multiple contact portions 14 can be arranged into multiple parallel rows. This can make the arrangement of the contact portions 14 more compact and neat, and further simplify the production of the contact portions 14 and the conductive circuits connected to the contact portions 14.

[0079] In the above embodiment, a plurality of contact portions 14 is a preferred embodiment because the greater the number of contact portions 14 located in the array region where the grooves 101 are located, the greater the effect of reducing the wafer occupied area and contact resistance compared to the conventional practice of placing a single contact portion 14 around the array region where the grooves 101 are located. It is understood that in some other embodiments, a single contact portion 14 located in the array region of the grooves 101 may be provided, which can also achieve a certain effect of reducing the occupied wafer area.

[0080] In some embodiments, see Appendix Figure 1 There are multiple grooves 101 , and the multiple grooves 101 are arranged in at least one row; wherein the row arrangement direction of the contact portions 14 is parallel to the row arrangement direction of the grooves 101 .

[0081] The plurality of trenches 101 are also arranged in at least one row, which simplifies the photolithography and etching processes for etching the substrate 10 to form the trenches 101. Furthermore, the row arrangement direction of the plurality of trenches 101 is parallel to the row arrangement direction of the contacts 14. This allows the trenches 101 and the contacts 14 to be arranged in a compact and neat array. This allows for the formation of as many deep trench capacitors (DTCs) as possible on the substrate 10 to provide greater capacitance, while also maximizing the number of contacts 14 to further reduce contact resistance. Furthermore, this arrangement facilitates the routing of interconnect structures, simplifying the overall fabrication process of the semiconductor structure.

[0082] In actual operation, see the attached Figure 1 , along the direction indicated by the arrow in the figure, the plurality of grooves 101 are arranged in a plurality of rows, and the plurality of contact portions 14 are also arranged in a plurality of rows, and the row arrangement directions are parallel, and the projection position of each contact portion 14 on the substrate 10 is located between two adjacent grooves 101 in the same row. In some other embodiments, see the attached Figure 5 , a row of contact portions 14 can be located between two adjacent rows of grooves 101. The row arrangement direction of the contact portions 14 and the grooves 101 is the direction indicated by the arrow in the figure. In this embodiment, the projection of each contact portion 14 on the substrate 10 is located between three adjacent grooves 101. Compared with the above embodiment where the projection of each contact portion 14 on the substrate 10 is located between two adjacent grooves 101 in the same row, in actual production, the process margin when manufacturing the contact portions 14 is larger, and the manufacturing difficulty will be reduced.

[0083] It is understood that the greater the number of trenches 101, the greater the capacitance of the formed deep trench capacitor (DTC), thereby achieving a better effect in shielding electromagnetic noise within the semiconductor device and stabilizing the power supply. In some other embodiments, the number of trenches 101 can be one, depending on actual needs, which can also achieve a certain effect in shielding electromagnetic noise within the semiconductor device and stabilizing the power supply.

[0084] In some embodiments, see Appendix Figure 2 To the attached Figure 4 , along the direction away from the bottom of the groove 101 , the stacked layer 11 includes a first electrode layer 121 , a second electrode layer 122 and a third electrode layer 123 in sequence, and the bottom of the contact portion 14 extends to different positions in the stacked layer 11 to connect to the corresponding electrode layer 12 .

[0085] The stacked layer 11 includes three electrode layers, which can make the deep trench capacitor (DTC) have a higher capacitance value, thereby ensuring the electrical performance of the semiconductor structure.

[0086] In some other embodiments, depending on actual needs, the stacked layer 11 may include two, four, or more electrode layers 12. Different electrode layers may include the same material and the same thickness, the same material and different thicknesses, different materials and the same thickness, or different materials and different thicknesses. Because the dielectric layer 13 is located between adjacent electrode layers 12, the total number of dielectric layers 13 is generally one less than the total number of electrode layers 12.

[0087] The bottom of the contact portion 14 extends to different positions in the stacked layer 11 to connect to the corresponding first electrode layer 121, the second electrode layer 122 and the third electrode layer 123, thereby leading the electrode layer of the deep trench capacitor (DTC) to connect to the interconnected conductive line, thereby realizing the charge and discharge control of the electrode plate of the deep trench capacitor (DTC). Figure 2 To the attached Figure 4 Along the Figure 1 Schematic diagram of vertical cross-section of AA', BB' and CC' lines in FIG. Figure 2 The figure shows an example in which the contact portion 14 extends to the upper surface of the first electrode layer 121 to connect to the first electrode layer 121. Figure 3 The figure shows an example in which the contact portion 14 extends to the upper surface of the second electrode layer 122 to connect to the second electrode layer 122. Figure 4 The figure shows an example in which the contact portion 14 extends to the upper surface of the third electrode layer 123 to connect to the third electrode layer 123. Here, the bottom of the contact portion 14 extends to the upper surfaces of the first electrode layer 121, the second electrode layer 122, and the third electrode layer 123 respectively. In some other embodiments, the bottom of the contact portion 14 may also extend to the inside of the first electrode layer 121, the second electrode layer 122, and the third electrode layer 123 to ensure better electrical connection.

[0088] In some embodiments, see Appendix Figure 1 The contact portion 14 connected to the first electrode layer 121 is defined as the first contact portion 141, the contact portion 14 connected to the second electrode layer 122 is defined as the second contact portion 142, and the contact portion 14 connected to the third electrode layer 123 is defined as the third contact portion 143. Figure 2 In the direction indicated by the middle arrow, the plurality of first contact portions 141 are arranged into at least one first contact portion row 15 (shown in the dotted box in the figure); the plurality of second contact portions 142 are arranged into at least one second contact portion row 16 (shown in the dotted box in the figure); and the plurality of third contact portions 143 are arranged into at least one third contact portion row 17 (shown in the dotted box in the figure); wherein the first contact portion row 15, the second contact portion row 16 and the third contact portion row 17 are parallel to each other.

[0089] The first, second, and third contact portions 141, 142, and 143 are used to respectively lead out the first, second, and third electrode layers 121, 122, and 123 to interconnected conductive traces, thereby controlling deep trench capacitance (DTC). The parallel arrangement of the first, second, and third contact rows 15, 16, and 17 simplifies the routing of interconnected conductive traces and simplifies the manufacturing process.

[0090] In some embodiments, see Appendix Figure 1 , the first contact portion row 15 and the third contact portion row 17 are arranged adjacent to each other.

[0091] First contact row 15 is electrically connected to first electrode layer 121, and third contact row 17 is electrically connected to third electrode layer 123. Since first electrode layer 121 and third electrode layer 123 in the deep trench capacitor (DTC) are electrically connected, i.e., first electrode layer 121 and third electrode layer 123 are connected via the same conductive layer and can serve as the anode plate of the deep trench capacitor (DTC), and second electrode layer 122 is connected to another conductive layer and can serve as the cathode plate of the deep trench capacitor (DTC), arranging first contact row 15 and third contact row 17 adjacent to each other facilitates the electrical connection between first contact portion 141 and third contact portion 143, simplifies the wiring of the interconnection lines above contact portion 14, and thus avoids circuit problems such as short circuits or open circuits that may result from overly complex wiring, thereby reducing wiring difficulty.

[0092] In actual operation, see the attached Figure 1 , the first contact portion row 15 and the third contact portion row 17 are adjacently arranged, and the second contact portion row 16 may be located on a side of the third contact portion row 17 away from the first contact portion row 15. In some other embodiments, see the attached Figure 5 The first contact portion row 15 and the third contact portion row 17 are adjacently arranged, and the second contact portion row 16 may be located on a side of the first contact portion row 15 away from the third contact portion row 17 .

[0093] In some embodiments, see Appendix Figure 6 and attached Figure 7 , a first contact portion row 15 is adjacent to two third contact portion rows 17 (see attached Figure 6 ); or, a third contact row 17 is adjacent to two first contact rows 15 (see attached Figure 7 ).

[0094] A first contact portion row 15 can be adjacent to two third contact portion rows 17, or a third contact portion row 17 can be adjacent to two first contact portion rows 15, that is, a first contact portion row 15 is arranged between two third contact portion rows 17, or a third contact portion row 17 is arranged between two first contact portion rows 15. In this way, the three adjacent contact portion rows can be electrically connected together through the first conductive layer 181, which can further simplify the wiring of the upper conductive layer and further reduce the manufacturing difficulty.

[0095] In some embodiments, see Appendix Figure 1 The semiconductor structure further includes: a conductive layer 18 , the conductive layer 18 includes a first conductive layer 181 and a second conductive layer 182 ; the first conductive layer 181 electrically connects the first contact portion 141 and the third contact portion 143 ; the second conductive layer 182 electrically connects the second contact portion 142 .

[0096] The first conductive layer 181 electrically connects the first contact portion 141 and the third contact portion 143 to facilitate connection to other interconnected circuits, for example, voltage control can be applied to the first electrode layer 121 and the third electrode layer 123 serving as anode plates, and the second conductive layer 182 electrically connects the second contact portion 142 to facilitate connection to other interconnected circuits, for example, voltage control can be applied to the second electrode layer serving as a cathode plate.

[0097] In actual operation, the material of the conductive layer 18 may include but is not limited to metal materials, such as any combination of one or more of tungsten, aluminum, nickel, gold, and silver.

[0098] In some embodiments, see Appendix Figure 1 In a direction perpendicular to the plane of the substrate 10 , the projection of the conductive layer 18 completely covers the projections of the first contact portion 141 , the second contact portion 142 , and the third contact portion 143 .

[0099] The projection of the conductive layer 18 completely covers the projections of the first contact portion 141, the second contact portion 142 and the third contact portion 143, that is, the conductive layer 18 can completely cover the contact portion 14, so as to maximize the contact area between the conductive layer 18 and the contact portion 14 and reduce the contact resistance; in addition, the conductive layer 18 can completely cover the contact portion 14, which can also help increase the alignment tolerance of the conductive layer 18 and the contact portion 14 and reduce the difficulty of manufacturing.

[0100] It is understandable that the technical features in the technical solutions described in the above embodiments can be combined arbitrarily without conflict. Figure 8In the direction perpendicular to the plane of the substrate 10, the projections of the first contact portion 141 and the third contact portion 143 are located between the projections of two adjacent grooves 101. Along the direction indicated by the arrow in the figure, the first contact portion row 15 and the third contact portion row 17 at least partially overlap with the row in which the grooves 101 are arranged, while the second contact portion row 16 is located between two adjacent rows of grooves 101. The first contact portion row 15, the second contact portion row 16 and the third contact portion row 17 are parallel to each other. In some other embodiments, see the attached Figure 9 Along the direction indicated by the arrows in the figure, the first contact portion row 15 and the second contact portion row 16 are located between two adjacent rows of grooves 101, and the projection of the third contact portion 143 is located between the projections of two adjacent grooves 101. That is, the third contact portion row 17 and the row in which the grooves 101 are arranged at least partially overlap, and the first contact portion row 15, the second contact portion row 16, and the third contact portion row 17 are parallel to each other. In addition, there are many other combinations of the technical features in the technical solutions described in the above embodiments, which are not listed here one by one. All combinations are intended to be included within the scope of protection of this disclosure.

[0101] An embodiment of the present disclosure further provides a memory, which includes the semiconductor structure in any one of the above embodiments.

[0102] In some embodiments, the memory may include but is not limited to random access memory (RAM), such as dynamic random access memory (DRAM).

[0103] The present disclosure also provides a method for manufacturing a semiconductor structure. Figure 10 , as shown in the figure, the method includes:

[0104] Step 101: providing a substrate;

[0105] Step 102: forming a groove in the substrate;

[0106] Step 103: forming a stacked layer, the stacked layer being located in the trench and extending above the substrate; the stacked layer comprising at least two electrode layers and a dielectric layer located between adjacent electrode layers;

[0107] Step 104 : forming a contact portion, the contact portion electrically connecting one electrode layer, wherein in a direction perpendicular to the plane where the substrate is located, a projection of the contact portion is located between projections of adjacent trenches.

[0108] The manufacturing method of the semiconductor structure provided by the present disclosure is further described in detail below with reference to specific embodiments.

[0109] Attachment Figure 1 A schematic top view of a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. Figure 2 To the attached Figure 4 Along the Figure 1 Schematic diagram of the vertical cross-section of line AA', line BB' and line CC'.

[0110] First, execute step 101, see the attached Figure 2 To the attached Figure 4 , providing a substrate 10.

[0111] Here, the substrate 10 may include, but is not limited to, a single semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. In some specific embodiments, the substrate 10 includes a doped or undoped silicon substrate.

[0112] Next, execute step 102. Figure 2 To the attached Figure 4 , a groove 101 is formed in the substrate 10 .

[0113] In actual operation, an anisotropic etching process, such as a plasma etching process, can be used to etch the substrate 10 to form a groove 101, wherein the horizontal cross-sectional shape of the groove 101 may include a circle, an ellipse, a rectangle, a rounded rectangle or any other closed two-dimensional shape, and the depth of the groove 101 can be set according to actual needs. In some specific embodiments, the depth of the groove 101 can range from 10 to 20 microns, including endpoint values, for example, 12 microns, 15 microns, 16 microns or 18 microns. The deep trench capacitor (DTC) formed in this way has a larger capacitance value and a higher breakdown voltage.

[0114] Next, execute step 103, see the attached Figure 2 To the attached Figure 4 , forming a stacked layer 11, which is located in the groove 101 and extends above the substrate 10; the stacked layer 11 includes at least two electrode layers 12 and a dielectric layer 13 located between adjacent electrode layers 12.

[0115] The stacked layer 11 formed in the trench 101 may constitute a deep trench capacitor (DTC) as a decoupling capacitor to shield electromagnetic noise in the semiconductor device and stabilize the dynamic voltage.

[0116] In actual operation, the stacked layer 11 can be formed by one or more of high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes, wherein the material of the electrode layer 12 can include but is not limited to doped silicon, polysilicon or metal materials, such as one or more combinations of copper, tungsten, aluminum, titanium, titanium nitride, tantalum or tantalum nitride. The material of the dielectric layer 13 can include but is not limited to dielectric metal oxide materials with a relatively high dielectric constant, such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, lanthanum oxide or a combination thereof. The use of materials with a high dielectric constant helps to reduce leakage current inside the deep trench capacitor (DTC), thereby increasing the capacitance value of the deep trench capacitor (DTC).

[0117] In some embodiments, see Appendix Figure 2 To the attached Figure 4 , forming the stacked layer 11, including: forming an isolation layer 102 covering the inner wall of the groove 101 and the surface of the substrate 10; forming a first electrode layer 121, a first dielectric layer 131, a second electrode layer 122, a second dielectric layer 132 and a third electrode layer 123 in sequence on the isolation layer 102; here, the first electrode layer 121, the first dielectric layer 131, the second electrode layer 122, the second dielectric layer 132 and the third electrode layer 123 are defined as the stacked layer 11.

[0118] The isolation layer 102 can isolate the substrate 10 and the first electrode layer 121 to prevent the conductive material in the first electrode layer 121 from diffusing into the substrate 10 and affecting the performance of the device. The stacked layer 11 in this embodiment includes three electrode layers, which can ensure that the deep trench capacitor (DTC) has a high capacitance value, thereby ensuring the electrical performance of the semiconductor structure.

[0119] In actual operation, the isolation layer 102, the first electrode layer 121, the first dielectric layer 131, the second electrode layer 122, the second dielectric layer 132 and the third electrode layer 123 can be conformally deposited on the inner wall of the groove 101 and above the substrate 10 in sequence by one or more of high-density inductively coupled plasma (ICP) deposition, sputtering, physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD) processes, wherein the material of the isolation layer 102 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc.

[0120] The stacked layer 11 formed in the above embodiment includes three electrode layers. In some other embodiments, depending on actual needs, the stacked layer 11 may include two, four, or more electrode layers. Different electrode layers may include the same material and the same thickness, the same material and different thicknesses, different materials and the same thickness, or different materials and different thicknesses. Because the dielectric layer 13 is located between adjacent electrode layers 12, the total number of dielectric layers 13 is generally one less than the total number of electrode layers 12.

[0121] Next, execute step 104. Figure 2 To the attached Figure 4 , forming a contact portion 14 , the contact portion 14 electrically connected to one electrode layer 12 , wherein in a direction perpendicular to the plane where the substrate 10 is located, the projection of the contact portion 14 is located between the projections of adjacent grooves 101 .

[0122] In a direction perpendicular to the plane of the substrate 10, the projection of the contact portion 14 is located between the projections of adjacent trenches 101. By positioning the contact portion 14 electrically connected to the electrode layer 12 in the array region where the trenches 101 are located, the occupied area can be reduced, compared to the conventional arrangement of the contact portion 14 at a peripheral position away from the array region where the trenches 101 are located, thereby improving wafer area utilization and thereby increasing the degree of integration. In addition, positioning the contact portion 14 between the trenches 101 facilitates increasing the number of contact portions 14 within the array region where the trenches 101 are located without additionally increasing the occupied area, thereby increasing the contact area between the contact portion 14 and the conductive lines interconnected therewith, thereby reducing contact resistance, thereby improving signal delay, and enhancing the performance of the semiconductor device.

[0123] In some embodiments, see Appendix Figure 2 To the attached Figure 4 , forming the contact portion 14, including: forming a first dielectric layer 103, the first dielectric layer 103 covering the stacked layer 11; etching the first dielectric layer 103, the third electrode layer 123, the second dielectric layer 132, the second electrode layer 122 and the first dielectric layer 131 to form a first opening 19, the first opening 19 exposing the upper surface of the first electrode layer 121 (see Appendix Figure 2 ); etching the first dielectric layer 103, the third electrode layer 123 and the second dielectric layer 132 to form a second opening 20, the second opening 20 exposing the upper surface of the second electrode layer 122 (see Appendix Figure 3 ); Etching the first dielectric layer 103 to form a third opening 21, the third opening 21 exposes the upper surface of the third electrode layer 123 (see Appendix Figure 4 ).

[0124] The first opening 19, the second opening 20 and the third opening 21 formed by etching expose the upper surfaces of the first electrode layer 121, the second electrode layer 122 and the third electrode layer 123 respectively, so as to facilitate the subsequent deposition of insulating material in the openings and then etching part of the insulating material to form contact holes exposing the upper surfaces of the corresponding electrode layers.

[0125] In some embodiments, see Appendix Figure 2 To the attached Figure 4 , forming the contact portion 14, further comprising: forming a second dielectric layer 104, the second dielectric layer 104 at least filling the first opening 19, the second opening 20 and the third opening 21; etching the portion of the second dielectric layer 104 located in the first opening 19, the second opening 20 and the third opening 21 to form first contact holes 22 respectively (see attached Figure 2 ), the second contact hole 23 (see Appendix Figure 3 ) and the third contact hole 24 (see Appendix Figure 4 ), the remaining second dielectric layer 104 on the sidewalls of the first opening 19, the second opening 20 and the third opening 21 is defined as a protective layer 25; first contact portions 141 are formed in the first contact hole 22, the second contact hole 23 and the third contact hole 24 respectively (see the attached Figure 2 ), the second contact portion 142 (see the attached Figure 3 ) and the third contact portion 143 (see Appendix Figure 4 ).

[0126] Part of the second dielectric layer 104 located within the first opening 19, the second opening 20, and the third opening 21 is etched to form a first contact hole 22, a second contact hole 23, and a third contact hole 24, respectively exposing the upper surfaces of the first electrode layer 121, the second electrode layer 122, and the third electrode layer 123, to ensure that the contact portion 14 subsequently formed in the contact hole forms a stable electrical connection with the corresponding electrode layer 12. The remaining second dielectric layer 104 located on the sidewalls of the first opening 19, the second opening 20, and the third opening 21 serves as a protective layer 25 to achieve electrical connection between a contact portion and a corresponding electrode layer, while being insulated from other electrode layers, thereby ensuring the reliability of the electrical performance of the semiconductor structure.

[0127] In actual operation, the first dielectric layer 103 and the second dielectric layer 104 can be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The materials of the first dielectric layer 103 and the second dielectric layer 104 can include but are not limited to silicon oxide, silicon oxynitride, silicon oxycarbide, doped or undoped silicate glass or organosilicate glass, etc. The materials of the first dielectric layer 103 and the second dielectric layer 104 can be the same or different. Referring to the drawings, in some specific embodiments, see the attached drawings. Figure 2 To the attached Figure 4The stacked layer 11 within the trench 101 further includes a receiving cavity 105. The first dielectric layer 103 fills the receiving cavity 105 and covers the stacked layer 11 above the substrate 10. Etching is performed on the first dielectric layer 103, the second dielectric layer 104, and the corresponding electrode layer 12 and dielectric layer 13 in the stacked layer 11 to form corresponding openings and contact holes. This can be accomplished by dry etching or wet etching, such as plasma etching, laser etching, or chemical etching.

[0128] In some embodiments, see Appendix Figure 1 After forming the contact portion 14, the method further includes: forming a conductive material layer (not shown in the figure); etching the conductive material layer to form a first conductive layer 181 and a second conductive layer 182, wherein the first conductive layer 181 covers the first contact portion 141 and the third contact portion 143; and the second conductive layer 182 covers the second contact portion 142.

[0129] First conductive layer 181 electrically connects first contact portion 141 and third contact portion 143 to facilitate connection to other interconnected circuits, for example, applying voltage control to first electrode layer 121 and third electrode layer 123, which function as anode plates. Second conductive layer 182 electrically connects second contact portion 142 to facilitate connection to other interconnected circuits, for example, applying voltage control to the second electrode layer, which functions as a cathode plate. The projection of conductive layer 18 completely covers the projections of first contact portion 141, second contact portion 142, and third contact portion 143, maximizing the contact area between conductive layer 18 and contact portion 14 and reducing contact resistance. Furthermore, the fact that conductive layer 18 completely covers contact portion 14 increases the alignment tolerance between conductive layer 18 and contact portion 14, reducing manufacturing complexity.

[0130] In actual operation, the conductive material layer can be formed by one or more of physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) processes. The material of the conductive material layer can include, but is not limited to, metal materials, such as any combination of one or more of tungsten, aluminum, titanium, tantalum, silver, tantalum nitride, and titanium nitride. Etching the conductive material layer can adopt an anisotropic etching process, such as a plasma etching process.

[0131] In summary, in the present disclosure, in a direction perpendicular to the plane of the substrate 10, the projection of the contact portion 14 is located between the projections of adjacent grooves 101. By arranging the position of the contact portion 14 electrically connected to the electrode layer 12 in the array region where the grooves 101 are located, compared to the conventional arrangement of the contact portion 14 separately at a peripheral position away from the array region where the grooves 101 are located, the occupied area can be reduced, thereby improving the wafer area utilization rate and thus improving the integration level. In addition, arranging the position of the contact portion 14 between the grooves 101 facilitates increasing the number of contact portions 14 as much as possible within the array region where the grooves 101 are located without additionally increasing the occupied area, thereby increasing the contact area between the contact portion 14 and the conductive lines interconnected therewith, thereby reducing contact resistance, thereby improving signal delay and improving the performance of the semiconductor device.

[0132] It should be noted that the semiconductor structure, manufacturing method, and memory provided in the embodiments of the present disclosure can be applied to any integrated circuit including the structure, such as a dynamic random access memory (DRAM) including the semiconductor structure provided in the embodiments of the present disclosure. The technical features of the technical solutions described in the various embodiments can be arbitrarily combined unless they conflict.

[0133] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A semiconductor structure, characterized in that include: a substrate and a groove within the substrate; a stacked layer located in the trench and extending above the substrate; The stacked layer includes a first electrode layer, a second electrode layer, a third electrode layer and a dielectric layer located between adjacent electrode layers; A contact portion, wherein the contact portion is electrically connected to one of the electrode layers, the contact portion connected to the first electrode layer is a first contact portion, the contact portion connected to the second electrode layer is a second contact portion, and the contact portion connected to the three electrode layers is a third contact portion. A plurality of the first contact portions are arranged into at least one first contact portion row, a plurality of the second contact portions are arranged into at least one second contact portion row, and a plurality of the third contact portions are arranged into at least one third contact portion row. A first contact portion row is adjacent to two third contact portion rows or a third contact portion row is adjacent to two first contact portion rows. In a direction perpendicular to the plane of the substrate, the projection of the contact portion is located between the projections of adjacent grooves.

2. The semiconductor structure according to claim 1, wherein: There are multiple grooves, and the multiple grooves are arranged in at least one row; wherein the row arrangement direction of the contact portions is parallel to the row arrangement direction of the grooves.

3. The semiconductor structure according to claim 2, wherein: The contact portions in one row are located between two adjacent rows of grooves.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that The bottom of the contact portion extends to different positions in the stacked layers to connect to the corresponding electrode layers.

5. The semiconductor structure according to claim 4, wherein: The first contact row, the second contact row, and the third contact row are parallel to each other.

6. The semiconductor structure according to claim 5, wherein: Also includes: a conductive layer, the conductive layer comprising a first conductive layer and a second conductive layer; the first conductive layer electrically connecting the first contact portion and the third contact portion; The second conductive layer is electrically connected to the second contact portion.

7. The semiconductor structure according to claim 6, wherein: In a direction perpendicular to the plane where the substrate is located, a projection of the conductive layer completely covers projections of the first contact portion, the second contact portion, and the third contact portion.

8. A memory, characterized in that: The method comprises the semiconductor structure according to any one of claims 1 to 7.

9. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate; forming a groove in the substrate; forming a stacked layer, wherein the stacked layer is located in the groove and extends above the substrate; The stacked layer includes a first electrode layer, a second electrode layer, a third electrode layer and a dielectric layer located between adjacent electrode layers; A contact portion is formed, wherein the contact portion is electrically connected to one of the electrode layers, the contact portion connected to the first electrode layer is a first contact portion, the contact portion connected to the second electrode layer is a second contact portion, and the contact portion connected to the three electrode layers is a third contact portion. A plurality of the first contact portions are arranged into at least one first contact portion row, a plurality of the second contact portions are arranged into at least one second contact portion row, and a plurality of the third contact portions are arranged into at least one third contact portion row. A first contact portion row is adjacent to two third contact portion rows or a third contact portion row is adjacent to two first contact portion rows. In a direction perpendicular to the plane of the substrate, the projection of the contact portion is located between the projections of adjacent grooves.

10. The method according to claim 9, characterized in that Forming the stacked layer includes: forming an isolation layer covering the inner wall of the groove and the surface of the substrate; A first electrode layer, a first dielectric layer, a second electrode layer, a second dielectric layer and a third electrode layer are sequentially formed on the isolation layer; the first electrode layer, the first dielectric layer, the second electrode layer, the second dielectric layer and the third electrode layer are defined as the stacked layer.

11. The method according to claim 10, characterized in that Forming the contact portion includes: forming a first dielectric layer, wherein the first dielectric layer covers the stacked layers; Etching the first dielectric layer, the third electrode layer, the second dielectric layer, the second electrode layer, and the first dielectric layer to form a first opening, wherein the first opening exposes an upper surface of the first electrode layer; Etching the first dielectric layer, the third electrode layer, and the second dielectric layer to form a second opening, wherein the second opening exposes an upper surface of the second electrode layer; The first dielectric layer is etched to form a third opening, where the third opening exposes an upper surface of the third electrode layer.

12. The method according to claim 11, characterized in that forming the contact portion, further comprising: forming a second dielectric layer, wherein the second dielectric layer at least fills the first opening, the second opening, and the third opening; Etching portions of the second dielectric layer located within the first opening, the second opening, and the third opening to form a first contact hole, a second contact hole, and a third contact hole, respectively, and defining the remaining portion of the second dielectric layer on sidewalls of the first opening, the second opening, and the third opening as a protective layer; A first contact portion, a second contact portion, and a third contact portion are formed in the first contact hole, the second contact hole, and the third contact hole, respectively.

13. The method according to claim 12, characterized in that After forming the contact portion, the method further includes: forming a conductive material layer; The conductive material layer is etched to form a first conductive layer and a second conductive layer, wherein the first conductive layer covers the first contact portion and the third contact portion; and the second conductive layer covers the second contact portion.

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