Clock circuit for use in an inertial measurement unit

Abstract

The application discloses a clock circuit applied in an inertial measurement unit, and solves the problem that a self-clock circuit is difficult to integrate under a low input reference frequency, and belongs to the technical field of electronic circuits.The clock circuit comprises a comparator and a phase-locked loop circuit; the phase-locked loop circuit comprises a phase-frequency detector (PFD), a switch resistance type active loop filter, a voltage control oscillator (VCO) and an adjustable multiple frequency divider M1; wherein the switch resistance type active loop filter comprises a buffer B1, a buffer B2, resistors R1-R8, capacitors C1-C4, switches S1 and S2 and an operational amplifier A1; the application solves the problem that the clock circuit is difficult to integrate by using a switch resistance type PLL circuit; and the initial clock output of the clock circuit during power-on can make the MEMS watch head start to vibrate quickly.

Description

Technical Field

[0001] This invention relates to a clock circuit used in an inertial measurement unit, belonging to the field of electronic circuit technology. Background Technology

[0002] A Miniature Inertial Measurement Unit (MIMU) is an important type of Micro-Electro-Mechanical System (MEMS). MIMUs typically include sensors such as accelerometers and gyroscopes to measure information such as an object's acceleration and angular velocity. In the complex battlefields of modern and foreseeable future high-tech environments, the intense technological confrontations urgently require miniature reconnaissance equipment such as micro-aircraft and micro-robots, as well as a large number of tactical weapons. This demand is driving the development of inertial navigation systems towards lower cost, miniaturization, and lower power consumption. Therefore, miniaturized inertial measurement units, with their small size, light weight, and low power consumption, are gradually replacing traditional large inertial measurement units and will become the mainstream of future inertial navigation systems.

[0003] In inertial measurement units (IMUs), self-clocking schemes are becoming increasingly popular. A self-clocking scheme uses a resonant accelerometer or gyroscope to generate its own reference clock during closed-loop operation. This reference clock is then processed by a PLL circuit before being used by the IMU. The advantages of using a self-clocking scheme include: 1. Eliminating the need for an external crystal oscillator, resulting in lower cost, miniaturization, and lower power consumption of the measurement system; 2. The synchronous clock signal generated by the PLL allows the ASIC to interface with a wide range of MEMS mechanical sensors.

[0004] However, self-clocking solutions currently face two challenges. One is that the resonant frequency of such MEMS mechanical meters is typically around kHz, meaning the input reference frequency of the PLL circuit is in a low range. This low input frequency limits the loop bandwidth the PLL can have, which in turn makes it difficult to implement a PLL without external components. Traditional charge pump phase-locked loops, in order to ensure phase noise performance, struggle to achieve full integration of the PLL circuit, thus negating some of the advantages of not requiring an external crystal oscillator.

[0005] Another challenge is that the MEMS mechanical meter head requires a certain amount of time to resonate. During this time, the PLL has no input reference clock and therefore no output clock signal, preventing the drive loop that requires a clock signal from operating and thus preventing resonance. One solution is to use clock switching technology: when the measurement system is not resonating, the corresponding switch is closed, using the clock generated by the oscillation circuit; once the measurement system resonates, the switch is opened, and the clock generated by the PLL circuit is used instead of the oscillation circuit's clock. However, this solution requires a relatively complex control circuit to control the opening and closing of the corresponding switch, increasing the complexity of the circuit design. Furthermore, it requires the PLL to have a relatively fixed output frequency to switch, which takes time, thus extending the time it takes for the measurement system to stabilize and start oscillating. Summary of the Invention

[0006] To address the problem of difficulty in integrating self-clocking circuits at low input reference frequencies, this invention provides a clocking circuit applicable to inertial measurement units.

[0007] A clock circuit for use in an inertial measurement unit according to the present invention includes a comparator 109 and a phase-locked loop circuit 110;

[0008] Phase-locked loop circuit 110 includes a phase-frequency detector (PFD), a switched-resistor active loop filter, a voltage-controlled oscillator (VCO), and an adjustable multiplier divider (M1).

[0009] The switched resistor type active loop filter includes buffer B1, buffer B2, resistors R1-R8, capacitors C1-C4, switch S1, switch S2 and operational amplifier A1.

[0010] The two outputs of the frequency and phase detector PFD are connected to the input terminals of buffers B1 and B2, respectively. The output terminal of buffer B1 is connected to one end of resistor R5, and the output terminal of buffer B2 is connected to one end of resistor R6.

[0011] The other end of resistor R5 is connected to one end of resistor R7, one end of switch S1, and one end of resistor R3.

[0012] The other end of resistor R6 is connected to one end of resistor R8, one end of switch S2, and one end of resistor R4.

[0013] The other ends of resistors R7 and R8 are connected to the power supply ground.

[0014] The other end of resistor R3 is connected to one end of capacitor C3;

[0015] The other end of resistor R4 is connected to one end of capacitor C4;

[0016] The negative input terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C3, one end of capacitor C1, and the other end of resistor R1;

[0017] The positive input terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C4, one end of capacitor C2, and the other end of resistor R2;

[0018] The other end of capacitor C2 is connected to the power supply ground;

[0019] The output of operational amplifier A1 is connected to both the other end of capacitor C1 and the input of voltage-controlled oscillator VCO.

[0020] The output of the voltage-controlled oscillator (VCO) is connected to the input of the adjustable frequency divider (M1), and the output of the VCO is the clock signal output of the phase-locked loop (PLL) circuit (110). The output of the adjustable frequency divider (M1) is connected to one input of the frequency and phase detector (PFD), and the other input of the PFD is connected to the output of the comparator (109).

[0021] Preferably, the voltage-controlled oscillator (VCO) includes an inverter group, PMOS transistors MP1, MP2, and NMOS transistor MN1, resistors R9, R10, and R11, capacitors C12, C13, C14, C15, and C16, and a current source I1; the inverter group includes a first inverter to a fifth inverter cascaded in sequence.

[0022] The gate terminal of the NMOS transistor MN1 is connected to the output terminal of the operational amplifier A1.

[0023] The source terminal of NMOS transistor MN1 is connected to one end of resistor R9, and the drain terminal of NMOS transistor MN1 is simultaneously connected to the drain terminal of PMOS transistor MP1, the gate terminal of PMOS transistor MP1, and the gate terminal of PMOS transistor MP2.

[0024] The other end of resistor R9 is connected to the power supply ground;

[0025] The source terminal of PMOS transistor MP1 is connected to one end of resistor R10;

[0026] The other end of resistor R10 is connected to the power supply VDD;

[0027] The source terminal of PMOS transistor MP2 is connected to one end of resistor R11, and the other end of resistor R11 is connected to the power supply VDD.

[0028] The drain of PMOS transistor MP2 is also connected to the source of the inverter group;

[0029] The positive terminal of current source I1 is connected to the drain terminal of MN1, and the negative terminal of current source I1 is connected to the power supply ground.

[0030] The output of the fifth inverter in the inverter group is connected to one end of capacitor C16 and the input of the first inverter. The output of the fifth inverter is the output of the voltage-controlled oscillator (VCO).

[0031] One end of capacitor C12, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and the other end of capacitor C16 are all connected to the power supply ground.

[0032] The other end of capacitor C12 is connected to the output of the first inverter;

[0033] The other end of capacitor C13 is connected to the output terminal of the second inverter;

[0034] The other end of capacitor C14 is connected to the output terminal of the third inverter;

[0035] The other end of capacitor C15 is connected to the output terminal of the fourth inverter.

[0036] Using a gyroscope as a carrier, this application also provides a gyroscope integrated circuit, including a driving loop, a detection loop, and the clock circuit as described in claim 1;

[0037] The driving loop includes a first charge amplifier 101, a first Σ-Δ analog-to-digital converter 102, a phase shifting module 103, an amplitude detection module 104, a PI control module 105, an adjustable gain module 106, a digital-to-analog converter 107, and a driving module 108.

[0038] The detection loop includes a second charge amplifier 113, a second Σ-Δ analog-to-digital converter 114, a temperature sensor 115, a digital modulation and demodulation module 116, and a temperature compensation module 117;

[0039] The input terminal of the first charge amplifier 101 is connected to the MEMS mechanical meter. The output terminal of the first charge amplifier 101 is simultaneously connected to the input terminal of the first Σ-Δ analog-to-digital converter 102 and the input terminal of the comparator 109. The output terminal of the first Σ-Δ analog-to-digital converter 102 is connected to the input terminal of the comparator 109. The output terminal of the first Σ-Δ analog-to-digital converter 102 is simultaneously connected to the input terminal of the phase shifter 103 and one input terminal of the digital modulation and demodulation module 116. The output terminal of the phase shifter 103 is simultaneously connected to the input terminal of the amplitude detection module 104 and the input terminal of the adjustable gain module 106. The output terminal of the amplitude detection module 104 is connected to the input terminal of the PI controller 105. The output terminal of the PI controller 105 is connected to the input terminal of the adjustable gain module 106. The output terminal of the adjustable gain module 106 is connected to the digital-to-analog converter 107. The output terminal of the digital-to-analog converter 107 is connected to the input terminal of the drive module 108. The output terminal of the drive module 108 is connected to the MEMS mechanical meter, forming a drive closed loop.

[0040] The input terminal of the second charge amplifier 113 is connected to the MEMS mechanical meter head, and the output terminal of the second charge amplifier 113 is connected to the input terminal of the second Σ-Δ analog-to-digital converter 114; the output terminal of the second Σ-Δ analog-to-digital converter 114 is connected to the other input terminal of the digital modulation and demodulation module 116; the output terminal of the digital modulation and demodulation module 116 is connected to the measurement angle signal input terminal of the temperature compensation module 117, and the output terminal of the temperature sensor 115 is connected to the temperature signal input terminal of the temperature compensation module 117.

[0041] The output of the temperature compensation module 117 is the digital output of the inertial measurement unit;

[0042] The clock signal output of the phase-locked loop circuit 110 is simultaneously connected to the clock signal inputs of the first Σ-Δ analog-to-digital converter 102, the second Σ-Δ analog-to-digital converter 114, the phase shift module 103, the amplitude detection module 104, the PI control module 105, the adjustable gain module 106, the digital modulation and demodulation module 116, and the temperature compensation module 117.

[0043] The beneficial effects of this invention are that the clock circuit of this invention can solve two difficulties simply and effectively. First, by using a switched resistor type PLL circuit, the problem of difficult integration of clock circuit at low input reference frequency is solved. Second, by setting the initial clock output when the clock circuit is powered on, the MEMS meter can start oscillating quickly. Attached Figure Description

[0044] Figure 1 This is a circuit diagram of the phase-locked loop in this invention;

[0045] Figure 2 This is a circuit diagram of the voltage-controlled oscillator in the phase-locked loop of this invention;

[0046] Figure 3 This is a system structure diagram of the gyroscope in this invention;

[0047] Figure 4 This is the control timing diagram of the phase-locked loop in this invention;

[0048] Figure 5 This is a diagram showing the oscillation result of the gyroscope in this invention. Detailed Implementation

[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0051] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0052] like Figure 1 As shown, the clock circuit proposed in this embodiment includes a comparator 109 and a phase-locked loop circuit 110, wherein the phase-locked loop circuit 110 includes a frequency and phase detector PFD, a switched resistor active loop filter, a voltage controlled oscillator VCO, and an adjustable multiplier divider M1.

[0053] The switched resistor type active loop filter includes buffer B1, buffer B2, resistors R1-R8, capacitors C1-C4, switch S1, switch S2 and operational amplifier A1.

[0054] The two outputs of the frequency and phase detector PFD are connected to the inputs of buffers B1 and B2, respectively. The output of buffer B1 is connected to one end of resistor R5, and the output of buffer B2 is connected to one end of resistor R6. The other end of resistor R5 is simultaneously connected to one end of resistor R7, one end of switch S1, and one end of resistor R3. The other end of resistor R6 is simultaneously connected to one end of resistor R8, one end of switch S2, and one end of resistor R4. The other ends of resistors R7 and R8 are simultaneously connected to power ground. The other end of resistor R3 is connected to one end of capacitor C3. The other end of resistor R4 is connected to one end of capacitor C4. The negative input of operational amplifier A1 is simultaneously connected to the other end of capacitor C3, one end of capacitor C1, and... The other end of resistor R1; the positive input terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C4, one end of capacitor C2, and the other end of resistor R2; the other end of capacitor C2 is connected to power ground; the output terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C1 and the input terminal of voltage-controlled oscillator VCO; the output terminal of voltage-controlled oscillator VCO is connected to the input terminal of adjustable frequency divider M1, and the output terminal of voltage-controlled oscillator VCO is the clock signal output terminal of phase-locked loop circuit 110; the output terminal of adjustable frequency divider M1 is connected to one input terminal of frequency-phase detector PFD, and the other input terminal of frequency-phase detector PFD is connected to the output terminal of comparator 109; for the phase-locked loop system, its open-loop system transfer function is:

[0055]

[0056] The loop gain of the system is:

[0057]

[0058] Therefore, the closed-loop transfer function of the system is:

[0059]

[0060] In the above formula, V DD For power supply voltage, K VCO The gain of the voltage-controlled oscillator (VCO) is given by N, the division ratio of the adjustable frequency divider M1 is given by N, and the other resistor and capacitor values ​​are as follows: Figure 1 The resistance and capacitance values ​​in the figure.

[0061] For large resistors R1 and R2 controlled by the "Window" switch, if the switch remains closed throughout the entire phase-locked loop (PLL) locking process, the thermal noise of the resistors dominates the contribution to the system's phase noise. Therefore, by keeping resistors R1 and R2 connected in the loop to perform signal filtering for a short period before and after the error signal output by the phase-frequency detector (PFD), and keeping them disconnected at other times, the impact of the resistor thermal noise on the entire system can be controlled to a small portion within one cycle.

[0062] like Figure 2 As shown, the voltage-controlled oscillator (VCO) includes an inverter group, PMOS transistors MP1 and MP2, NMOS transistor MN1, resistors R9, R10, and R11, capacitors C12, C13, C14, C15, and C16, and a current source I1. The inverter group includes a first inverter 410 to a fifth inverter 414 cascaded in sequence. Specifically, the output terminal of the first inverter 410 is electrically connected to the input terminal of the second inverter 411, the output terminal of the second inverter 411 is connected to the input terminal of the third inverter 412, the output terminal of the third inverter 412 is connected to the input terminal of the fourth inverter 413, and the output terminal of the fourth inverter 413 is connected to the input terminal of the fifth inverter 414.

[0063] The gate terminal of NMOS transistor MN1 is connected to the output terminal of operational amplifier A1.

[0064] The source terminal of NMOS transistor MN1 is connected to one end of resistor R9, and the drain terminal of NMOS transistor MN1 is simultaneously connected to the drain terminal of PMOS transistor MP1, the gate terminal of PMOS transistor MP1, and the gate terminal of PMOS transistor MP2.

[0065] The other end of resistor R9 is connected to the power supply ground;

[0066] The source terminal of PMOS transistor MP1 is connected to one end of resistor R10;

[0067] The other end of resistor R10 is connected to the power supply VDD;

[0068] The source terminal of PMOS transistor MP2 is connected to one end of resistor R11, and the other end of resistor R11 is connected to the power supply VDD.

[0069] The drain of PMOS transistor MP2 is also connected to the source of the inverter group;

[0070] The positive terminal of current source I1 is connected to the drain terminal of MN1, and the negative terminal of current source I1 is connected to the power supply ground.

[0071] The output of the fifth inverter in the inverter group is connected to one end of capacitor C16 and the input of the first inverter 410. The output of the fifth inverter 414 is the output of the voltage controlled oscillator (VCO).

[0072] One end of capacitor C12, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and the other end of capacitor C16 are all connected to the power supply ground.

[0073] The other end of capacitor C12 is connected to the output terminal of the first inverter 410;

[0074] The other end of capacitor C13 is connected to the output terminal of the second inverter 411;

[0075] The other end of capacitor C14 is connected to the output of the third inverter 412;

[0076] The other end of capacitor C15 is connected to the output of the fourth inverter 413.

[0077] The first inverter 410, the second inverter 411, the third inverter 412, the fourth inverter 413, and the fifth inverter 414, along with capacitors C12, C13, C14, C15, and C16, form a current-controlled ring oscillator. NMOS transistor MN1 and resistor R9 convert the input control voltage into current. This current passes through PMOS transistors MP1 and MP2, resistors R10 and R11, and is replicated to the current-controlled ring oscillator, thus achieving the voltage-to-frequency conversion function. The current source I1 ensures that when the MEMS mechanical meter of the inertial measurement unit is not oscillating, the phase-locked loop circuit outputs an initial fixed frequency, thereby driving the closed-loop circuit to operate normally and enabling the inertial measurement unit to oscillate.

[0078] The clock circuit proposed in this embodiment is applied in an inertial measurement unit. This embodiment uses a gyroscope as a carrier and provides a specific example: a gyroscope integrated circuit, which includes a drive loop, a detection loop and the aforementioned clock circuit.

[0079] The driving loop includes a first charge amplifier 101, a first Σ-Δ analog-to-digital converter 102, a phase shifting module 103, an amplitude detection module 104, a PI control module 105, an adjustable gain module 106, a digital-to-analog converter 107, and a driving module 108.

[0080] The detection loop includes a second charge amplifier 113, a second Σ-Δ analog-to-digital converter 114, a temperature sensor 115, a digital modulation and demodulation module 116, and a temperature compensation module 117;

[0081] The input terminal of the first charge amplifier 101 is connected to the MEMS mechanical meter. The output terminal of the first charge amplifier 101 is simultaneously connected to the input terminal of the first Σ-Δ analog-to-digital converter 102 and the input terminal of the comparator 109. The output terminal of the first Σ-Δ analog-to-digital converter 102 is connected to the input terminal of the comparator 109. The output terminal of the first Σ-Δ analog-to-digital converter 102 is simultaneously connected to the input terminal of the phase shifter 103 and one input terminal of the digital modulation and demodulation module 116. The output terminal of the phase shifter 103 is simultaneously connected to the input terminal of the amplitude detection module 104 and the input terminal of the adjustable gain module 106. The output terminal of the amplitude detection module 104 is connected to the input terminal of the PI controller 105. The output terminal of the PI controller 105 is connected to the input terminal of the adjustable gain module 106. The output terminal of the adjustable gain module 106 is connected to the digital-to-analog converter 107. The output terminal of the digital-to-analog converter 107 is connected to the input terminal of the drive module 108. The output terminal of the drive module 108 is connected to the MEMS mechanical meter, forming a drive closed loop.

[0082] The input terminal of the second charge amplifier 113 is connected to the MEMS mechanical meter head, and the output terminal of the second charge amplifier 113 is connected to the input terminal of the second Σ-Δ analog-to-digital converter 114; the output terminal of the second Σ-Δ analog-to-digital converter 114 is connected to the other input terminal of the digital modulation and demodulation module 116; the output terminal of the digital modulation and demodulation module 116 is connected to the measurement angle signal input terminal of the temperature compensation module 117, and the output terminal of the temperature sensor 115 is connected to the temperature signal input terminal of the temperature compensation module 117.

[0083] The output of the temperature compensation module 117 is the digital output of the inertial measurement unit;

[0084] The clock signal output of the phase-locked loop circuit 110 is simultaneously connected to the clock signal inputs of the first Σ-Δ analog-to-digital converter 102, the second Σ-Δ analog-to-digital converter 114, the phase shift module 103, the amplitude detection module 104, the PI control module 105, the adjustable gain module 106, the digital modulation and demodulation module 116, and the temperature compensation module 116.

[0085] The gyroscope integrated circuit of this embodiment also includes a power management section, which includes a reference module 111 and a voltage regulator 112. The output terminal of the reference module 111 is connected to the input terminal of the voltage regulator 112, and the output terminal of the voltage regulator provides a reference level or power supply to the clock circuit of the drive loop and the detection loop.

[0086] The gyroscope integrated circuit in this embodiment operates on the principle of a MEMS resonant gyroscope. Its drive loop uses an automatic gain control closed loop to form positive feedback, causing the MEMS meter head to oscillate self-excitedly and eventually reach a stable amplitude oscillation. Based on the Coriolis force principle, when an external angular velocity is input, the detection axis will undergo a displacement that is in phase with the drive axis velocity, thereby causing a change in the detection capacitance.

[0087] The drive shaft obtains a digital signal of drive displacement by detecting the change in capacitance and performing analog-to-digital conversion by the first Σ-Δ analog-to-digital converter 102. Then, the signal is passed through the phase shift module 103 to obtain a signal in phase with the speed of the drive shaft. After being amplified by the adjustable gain module 106, the signal is modulated into a 1-bit code stream by the digital-to-analog converter 107. Finally, the signal is fed back to the MEMS meter head through the drive module 108.

[0088] In the drive loop, the gain of the adjustable gain module 106 is determined by the PI control module 105. The digital signal from the phase shift module 103 passes through the amplitude detection module 104 and is then sent to the PI control module 105, thereby controlling the gain of the adjustable gain module 106.

[0089] The detection axis detects changes in capacitance and performs analog-to-digital conversion to obtain an amplitude-modulated digital signal with the drive axis speed as the carrier and modulated by the external input angular velocity. During normal system operation, the digital signal output from the first Σ-Δ analog-to-digital converter 102 of the drive axis is used to demodulate the amplitude-modulated digital signal, resulting in a digital output of the measured input angular velocity.

[0090] The temperature signal obtained from the temperature sensor is fed into the temperature compensation module 117, which performs temperature compensation on the digital output of the measured value of the input angular velocity to obtain the final digital output signal of the gyroscope integrated circuit.

[0091] In a self-clocked MEMS gyroscope, the phase-locked loop module performs a frequency multiplication operation on the drive shaft displacement signal frequency to provide a precise clock for the mode conversion and digital module. The digital module includes a phase shift module 103, an amplitude detection module 104, a PI control module 105, an adjustable gain module 106, a digital modulation and demodulation module 116, and a temperature compensation module 117.

[0092] like Figure 4As shown, before the UP and DOWN signals arrive, the Window first reaches a high level. For a short period after the UP and DOWN signals end, the Window remains at a high level before turning low.

[0093] like Figure 5 As shown in the figure, this is the time-domain simulation result of the gyroscope drive shaft displacement. The horizontal axis represents time (seconds), and the vertical axis represents displacement (meters). The system is powered on at time 0. Before oscillation starts, an initial clock signal is provided by the phase-locked loop circuit, and the automatic gain controller provides a large drive loop gain. Noise gradually accumulates in the drive loop. Around 0.1s, the drive shaft begins to oscillate noticeably and exhibits amplified oscillations. As the oscillation amplitude increases, the gain provided by the automatic gain controller gradually decreases. Around 0.17s, the loop gain has significantly decreased. After about 0.2s, the drive shaft achieves stable amplitude oscillation. At this time, the output frequency signal of the phase-locked loop circuit synchronously tracks the gyroscope oscillation signal, providing a stable clock for the entire system.

[0094] While the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely examples of the principles and applications of the invention. Therefore, it should be understood that many modifications can be made to the exemplary embodiments, and other arrangements can be designed without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that different dependent claims and features herein can be combined in ways different from those described in the original claims. It is also understood that features described in conjunction with individual embodiments can be used in other embodiments.

Claims

1. A clock circuit used in an inertial measurement unit, characterized in that, It includes a comparator (109) and a phase-locked loop circuit (110); The phase-locked loop circuit (110) includes a frequency and phase detector (PFD), a switched resistor active loop filter, a voltage-controlled oscillator (VCO), and an adjustable multiplier frequency divider (M1). The switched resistor type active loop filter includes buffer B1, buffer B2, resistors R1-R8, capacitors C1-C4, switch S1, switch S2 and operational amplifier A1. The two outputs of the frequency and phase detector PFD are connected to the input terminals of buffers B1 and B2, respectively. The output terminal of buffer B1 is connected to one end of resistor R5, and the output terminal of buffer B2 is connected to one end of resistor R6. The other end of resistor R5 is connected to one end of resistor R7, one end of switch S1, and one end of resistor R3. The other end of resistor R6 is connected to one end of resistor R8, one end of switch S2, and one end of resistor R4. The other ends of resistors R7 and R8 are connected to the power supply ground. The other end of resistor R3 is connected to one end of capacitor C3; The other end of resistor R4 is connected to one end of capacitor C4; The negative input terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C3, one end of capacitor C1, and the other end of resistor R1; The positive input terminal of operational amplifier A1 is simultaneously connected to the other end of capacitor C4, one end of capacitor C2, and the other end of resistor R2; The other end of capacitor C2 is connected to the power supply ground; The output of operational amplifier A1 is connected to both the other end of capacitor C1 and the input of voltage-controlled oscillator VCO. The output of the voltage-controlled oscillator (VCO) is connected to the input of the adjustable frequency divider (M1). The output of the VCO is the clock signal output of the phase-locked loop circuit (110). The output of the adjustable frequency divider (M1) is connected to one input of the frequency and phase detector (PFD). The other input of the PFD is connected to the output of the comparator (109).

2. The clock circuit according to claim 1, characterized in that, The voltage-controlled oscillator (VCO) includes an inverter group, PMOS transistors MP1, MP2, and NMOS transistor MN1, resistors R9, R10, and R11, capacitors C12, C13, C14, C15, and C16, and a current source I1; the inverter group includes a first inverter to a fifth inverter cascaded in sequence. The gate terminal of the NMOS transistor MN1 is connected to the output terminal of the operational amplifier A1. The source terminal of NMOS transistor MN1 is connected to one end of resistor R9, and the drain terminal of NMOS transistor MN1 is simultaneously connected to the drain terminal of PMOS transistor MP1, the gate terminal of PMOS transistor MP1, and the gate terminal of PMOS transistor MP2. The other end of resistor R9 is connected to the power supply ground; The source terminal of PMOS transistor MP1 is connected to one end of resistor R10; The other end of resistor R10 is connected to the power supply VDD; The source terminal of PMOS transistor MP2 is connected to one end of resistor R11, and the other end of resistor R11 is connected to the power supply VDD. The drain of PMOS transistor MP2 is also connected to the source of the inverter group; The positive terminal of current source I1 is connected to the drain terminal of MN1, and the negative terminal of current source I1 is connected to the power supply ground. The output of the fifth inverter in the inverter group is connected to one end of capacitor C16 and the input of the first inverter. The output of the fifth inverter is the output of the voltage-controlled oscillator (VCO). One end of capacitor C12, one end of capacitor C13, one end of capacitor C14, one end of capacitor C15, and the other end of capacitor C16 are all connected to the power supply ground. The other end of capacitor C12 is connected to the output of the first inverter; The other end of capacitor C13 is connected to the output of the second inverter; The other end of capacitor C14 is connected to the output of the third inverter; The other end of capacitor C15 is connected to the output of the fourth inverter.

3. A gyroscope integrated circuit, characterized in that, Includes a drive loop, a detection loop, and the clock circuit as described in claim 1; The driving loop includes a first charge amplifier (101), a first Σ-Δ analog-to-digital converter (102), a phase shifting module (103), an amplitude detection module (104), a PI controller (105), an adjustable gain module (106), a digital-to-analog converter (107), and a driving module (108); The detection loop includes a second charge amplifier (113), a second Σ-Δ analog-to-digital converter (114), a temperature sensor (115), a digital modulation and demodulation module (116), and a temperature compensation module (117); The input terminal of the first charge amplifier (101) is connected to the MEMS mechanical meter head. The output terminal of the first charge amplifier (101) is simultaneously connected to the input terminal of the first Σ-Δ analog-to-digital converter (102) and the input terminal of the comparator (109). The output terminal of the first Σ-Δ analog-to-digital converter (102) is connected to the input terminal of the comparator (109). The output terminal of the first Σ-Δ analog-to-digital converter (102) is simultaneously connected to the input terminal of the phase shift module (103) and one input terminal of the digital modulation and demodulation module (116). The output terminal of the phase shift module 103 is simultaneously connected to the input terminal of the phase shift module (103) and one input terminal of the digital modulation and demodulation module (116). The input terminal of the amplitude detection module (104) and the input terminal of the adjustable gain module (106) are connected; the output terminal of the amplitude detection module (104) is connected to the input terminal of the PI controller (105), the output terminal of the PI controller (105) is connected to the input terminal of the adjustable gain module (106), the output terminal of the adjustable gain module (106) is connected to the digital-to-analog converter (107), the output terminal of the digital-to-analog converter (107) is connected to the input terminal of the drive module (108), and the output terminal of the drive module (108) is connected to the MEMS mechanical meter head, forming a drive closed loop; The input terminal of the second charge amplifier (113) is connected to the MEMS mechanical meter head, and the output terminal of the second charge amplifier (113) is connected to the input terminal of the second Σ-Δ analog-to-digital converter (114); the output terminal of the second Σ-Δ analog-to-digital converter (114) is connected to the other input terminal of the digital modulation and demodulation module (116); the output terminal of the digital modulation and demodulation module (116) is connected to the measurement angle signal input terminal of the temperature compensation module (117), and the output terminal of the temperature sensor (115) is connected to the temperature signal input terminal of the temperature compensation module (117); The output of the temperature compensation module (117) is the digital output of the inertial measurement unit; The clock signal output of the phase-locked loop circuit (110) is simultaneously connected to the clock signal inputs of the first Σ-Δ analog-to-digital converter (102), the second Σ-Δ analog-to-digital converter (114), the phase shift module (103), the amplitude detection module (104), the PI controller (105), the adjustable gain module (106), the digital modulation and demodulation module (116), and the temperature compensation module (117).

4. The gyroscope integrated circuit according to claim 3, characterized in that, It also includes a reference module (111) and a voltage regulator (112); the output of the reference module (111) is connected to the input of the voltage regulator (112), and the output of the voltage regulator provides a reference level or power supply for the drive loop, the detection loop and the clock circuit of claim 1.

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