Low-temperature-drift operational amplifier-free bandgap reference voltage circuit, method for generating bandgap reference voltage, and compensation method

Abstract

The present invention discloses a low-temperature drift bandgap reference voltage circuit without an operational amplifier, a method for generating a bandgap reference voltage, and a compensation method, which relate to the technical field of integrated circuits, and solve the technical problems that in the prior art, the bandgap reference voltage circuit uses an operational amplifier for clamping, which affects the accuracy of the reference voltage and cannot generate a high power supply rejection ratio. The bandgap reference voltage circuit includes: a bandgap core circuit, a temperature compensation circuit, and a first startup circuit; the output end of the first startup circuit is connected to the input end of the bandgap core circuit; the output end of the temperature compensation circuit is connected to the input end of the bandgap core circuit. The present invention adopts a structure without an operational amplifier to avoid the introduction of noise and the influence of the offset voltage on the bandgap reference voltage V ref from being affected; and adopts a current mirror structure to supply power to the bandgap core circuit to improve the power supply rejection ratio; a temperature compensation circuit is added to perform temperature compensation on the bandgap core circuit to improve the accuracy of the bandgap and achieve low-temperature drift in a wide temperature range.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular, to a low-temperature-drift operational-amplifier-free bandgap reference voltage circuit, a method for generating a bandgap reference voltage, and a compensation method. Background Art

[0002] A reference voltage circuit is an indispensable unit module in analog circuits and mixed-signal circuits, and is widely used in the design of integrated circuits such as high-precision power management chips, AD / DA converters, and random dynamic memories. Among many reference circuit structures, the bandgap reference voltage circuit has become the most widely used reference voltage source technology at present because it can provide an accurate voltage and has high temperature stability.

[0003] The basic principle of a common existing bandgap reference voltage circuit is as follows: Two voltages with opposite temperature coefficients are added in proportion to obtain a total voltage, so that its temperature coefficient is close to zero and remains stable within a certain temperature range. In a traditional bandgap reference circuit structure, there is an operational amplifier. The schematic diagram of a bandgap reference circuit with an operational amplifier is as Figure 1 shown. In the figure, PM1, PM2, and PM3 form a current mirror, and Q1 and Q2 are transistors with emitter areas in proportion. Due to the existence of the operational amplifier and the resistor feedback network, the circuit is in a deep negative feedback state. By using the characteristic of virtual short of the operational amplifier, the voltages at the two input terminals of the operational amplifier are forced to be equal. Also, due to the virtual open characteristic of the operational amplifier, the currents flowing out of PM1 and PM2 are of the same magnitude. The same current flows through Q1 and Q2, making the difference in base-emitter voltages ΔV BE across the resistor R1, generating a PTAT (Proportional to Absolute Temperature) current, that is, a positive temperature coefficient current.

[0004] The traditional operational-amplifier bandgap reference circuit uses an operational amplifier for clamping. The offset voltage introduced by the operational amplifier will affect the accuracy of the reference voltage. At the same time, new noise is introduced, increasing the complexity of the design. Moreover, the traditional operational-amplifier bandgap reference voltage circuit is easily affected by the power supply and it is difficult to have a high power supply rejection ratio.

[0005] In the process of implementing the present invention, the inventors found that there are at least the following problems in the prior art:

[0006] The existing operational-amplifier bandgap reference voltage circuit uses an operational amplifier for clamping, which will affect the accuracy of the reference voltage and cannot generate a high power supply rejection ratio. Summary of the Invention

[0007] The object of the present invention is to provide a low-temperature drift operational amplifier-free bandgap reference voltage circuit, a method for generating a bandgap reference voltage, and a compensation method, so as to solve the technical problems existing in the prior art that the bandgap reference voltage circuit uses an operational amplifier for clamping, which will affect the accuracy of the reference voltage and cannot generate a high power supply rejection ratio.

[0008] The preferred technical solutions among the many technical solutions provided by the present invention can produce many technical effects, which will be elaborated in detail below.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] In the first aspect, an embodiment of the present invention provides a low-temperature drift operational amplifier-free bandgap reference voltage circuit, including: a bandgap core circuit, a temperature compensation circuit, and a first startup circuit; the output end of the first startup circuit is connected to the input end of the bandgap core circuit; the output end of the temperature compensation circuit is connected to the input end of the bandgap core circuit.

[0011] Optionally, the bandgap core circuit includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1, and an NMOS transistor NM2; the PMOS transistor PM1, the PMOS transistor PM2, the NMOS transistor NM1, and the NMOS transistor NM2 form a current mirror structure;

[0012] The sources of the PMOS transistor PM1 and the PMOS transistor PM2 are both connected to the power supply. The gate of the PMOS transistor PM2 is connected to the gate and drain of the PMOS transistor PM1. The gate and drain of the PMOS transistor PM1 are connected to the drain of the NMOS transistor NM1 and the first startup circuit. The drain of the PMOS transistor PM2 is connected to the gate and drain of the NMOS transistor NM2. The gate of the NMOS transistor NM2 is connected to the gate of the NMOS transistor NM1. The source of the NMOS transistor NM1 is connected to the bandgap core circuit, and the source of the NMOS transistor NM2 is connected to the bandgap core circuit. The gate and drain of the PMOS transistor PM1, and the drain of the NMOS transistor NM1 are all connected to the first startup circuit;

[0013] The bandgap core circuit further includes a triode Q1, a triode Q2, a triode Q3, a resistor R1, a resistor R2, a resistor R3, a resistor R4, and a resistor R5;

[0014] The base and collector of the triode Q1 are connected to the base of the triode Q2 through the resistor R2. The base and collector of the triode Q1 are connected to one end of the resistor R3. The other end of the resistor R3 is respectively connected to the temperature compensation circuit, one end of the resistor R5, and one end of the resistor R4. The other end of the resistor R5 is respectively connected to the source of the NMOS transistor NM1 and the first startup circuit;

[0015] The collector of the triode Q2 is connected to the other end of the resistor R4 and the base of the triode Q3;

[0016] The collector of the triode Q3 is connected to the source of the MOS transistor NM2 through the resistor R6;

[0017] The emitters of the triodes Q1 and Q3 are directly grounded; the triode Q2 is grounded through the resistor R1.

[0018] Optionally, the first startup circuit includes a PMOS transistor PM8, an NMOS transistor NM6, and an NMOS transistor NM5;

[0019] The source of the PMOS transistor PM8 is connected to the power supply, the gate and drain of the PMOS transistor PM8 are connected to the gate of the NMOS transistor NM6 and the gate and drain of the NMOS transistor NM5, and the source of the NMOS transistor NM5 is grounded;

[0020] The gate of the NMOS transistor NM6 is connected to the gate and drain of the PMOS transistor PM8 and the gate and drain of the NMOS transistor NM5; the drain of the NMOS transistor NM6 is connected to the gate and drain of the PMOS transistor PM1, the gate of the PMOS transistor PM2, and the drain of the NMOS transistor NM1; the source of the NMOS transistor NM6 is connected to the source of the NMOS transistor NM1 and the bandgap core circuit.

[0021] Optionally, the temperature compensation circuit includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, an NMOS transistor NM3, and an NMOS transistor NM4; the PMOS transistors PM3, PM4, PM6, and PM7 form a current mirror structure; the sources of the PMOS transistors PM3, PM4, PM5, PM6, and PM7 are all connected to the power supply;

[0022] The gate of the PMOS transistor PM3 is connected to the gate of the PMOS transistor PM4, and the drain of the PMOS transistor PM3 is connected to the bandgap core circuit; the gate and drain of the PMOS transistor PM4 are connected and then connected to the collector of the triode Q4;

[0023] The gate of the PMOS transistor PM5 is connected to the gates of the PMOS transistors PM6 and PM7, and the drain is connected to the base of the triode Q4 and the resistor R8;

[0024] The gate of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM7. The drain of the PMOS transistor PM6 is connected to the drain of the NMOS transistor NM3. The drain of the PMOS transistor PM7 is connected to the gate and drain of the NMOS transistor NM4. The gate of the NMOS transistor NM3 is connected to the gate and drain of the NMOS transistor NM4. The source of the NMOS transistor NM3 is connected to the resistor R9. The source of the NMOS transistor NM4 is connected to the emitter of the triode Q5.

[0025] Optionally, the bandgap reference voltage circuit further includes a second startup circuit, and the second startup circuit is connected to the temperature compensation circuit;

[0026] The second startup circuit includes a PMOS transistor PM10, a PMOS transistor PM9, and a capacitor C2. The sources of the PMOS transistor PM10 and the PMOS transistor PM9 are both connected to the power supply. The gate of the PMOS transistor PM10 is connected to the gate of the PMOS transistor PM7. The drain of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM7, the gate and drain of the NMOS transistor NM4. The drain of the PMOS transistor PM10, the gate of the PMOS transistor PM9, and the upper plate of the capacitor C2 are connected. The lower plate of the capacitor C2 is grounded.

[0027] Based on the same inventive concept, in a second aspect, an embodiment of the present invention further provides a method for generating a bandgap reference voltage, which is applied to the above-mentioned bandgap reference voltage circuit. The generating method includes:

[0028] Inject a startup current into the bandgap core circuit of the bandgap reference voltage circuit through the first startup circuit of the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and further enables the bandgap core circuit to quickly enter the working state;

[0029] Generate a first temperature coefficient voltage V 负 and a second temperature coefficient voltage V 正 through the bandgap core circuit; and obtain a bandgap reference voltage V 负 and a second temperature coefficient voltage V 正 , and obtain a bandgap reference voltage V ref ;

[0030] Generate a negative temperature coefficient current through the temperature compensation circuit to compensate the bandgap reference voltage V ref , and realize a bandgap reference voltage V ref with a zero temperature coefficient voltage.

[0031] Optionally, generating a first temperature coefficient voltage V 负 through the bandgap core circuit includes:

[0032] In the bandgap core circuit, based on the fact that the resistance values of resistor R3 and resistor R4 are the same, and resistor R4 is connected to the base of transistor Q3, and resistor R3 is connected to the base and collector of transistor Q1, the voltage of resistor R4 is the forward voltage drop VBE3 of transistor Q3, and the voltage of resistor R3 is the forward voltage drop VBE1 of transistor Q1;

[0033] Based on the fact that PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2 in the bandgap core circuit are in a current mirror structure, and the sizes of PMOS transistor PM1 and PMOS transistor PM2 are the same, and the sizes of NMOS transistor NM1 and NMOS transistor NM2 are the same, it is obtained that: VBE1 = VBE3.

[0034] Optionally, a second temperature coefficient voltage V is generated through the bandgap core circuit 正 , including:

[0035] In the bandgap core circuit, based on the fact that the currents of resistor R3 and resistor R4 are the same, and the ratio of the emitter areas of transistor Q1 and transistor Q2 is 1:N, the difference in VBE between transistor Q1 and transistor Q2, ΔVBE, is obtained 1-2 , and the specific formula is:

[0036]

[0037] ΔVBE 1-2 = VB1 - VE1 - VB2 + VE2 = VB1 - VB2 - (VE1 - VE2);

[0038] Among them, VE1 - VE2 is the emitter voltage difference between transistor Q1 and transistor Q2, VB1 - VB2 is the base voltage difference between transistor Q1 and transistor Q2, VT is the thermal voltage, I C is the collector current of the transistor, and I S is the reverse saturation current;

[0039] According to ΔVBE 1-2 , VB1 - VB2, and VE1 - VE2, the collector currents of transistor Q1 and transistor Q2 are obtained. The specific formulas for ΔABE 1-2 , VB1 - VB2, and VE1 - VE2 are:

[0040]

[0041] Among them, β is the amplification factor of the collector current of the transistor, R1 is the resistance value of resistor R1 in the bandgap core circuit, and R2 is the resistance value of resistor R2 in the bandgap core circuit;

[0042] The collector current formulas of the obtained triodes Q1 and Q2 are as follows:

[0043]

[0044] Based on the collector currents of the triodes Q1 and Q2, the second temperature coefficient voltage V 正 is obtained, and the specific formula is:

[0045]

[0046] where R3 is the resistance value of the resistor R3 in the bandgap core circuit, and R5 is the resistance value of the resistor R5 in the bandgap core circuit.

[0047] Optionally, obtaining the bandgap reference voltage V 负 from the first temperature coefficient voltage V 正 and the second temperature coefficient voltage V ref includes:

[0048]

[0049] where V ref is the bandgap reference voltage, R3 is the resistance value of the resistor R3, R5 is the resistance value of the resistor R5, VBE1 is the forward voltage drop of Q1, which is also the first temperature coefficient voltage V 负 and is negatively correlated with temperature, is the second temperature coefficient voltage V 正 , and VT is positively correlated with temperature.

[0050] Based on the same inventive concept, in a second aspect, an embodiment of the present invention further provides a compensation method for a bandgap reference voltage, which is applied to the above-mentioned bandgap reference voltage circuit, and the compensation method includes:

[0051] Inject a startup current into the bandgap core circuit of the bandgap reference voltage circuit through the first startup circuit of the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and further enables the bandgap core circuit to quickly enter the working state;

[0052] Generate the first temperature coefficient voltage V 负 and the second temperature coefficient voltage V 正 through the bandgap core circuit, and obtain the bandgap reference voltage V 负 and the second temperature coefficient voltage V 正 based on the first temperature coefficient voltage V ref ;

[0053] Generate a negative temperature coefficient current through the temperature compensation circuit, and the specific formula is:

[0054]

[0055] Among them, IR9 is the negative temperature coefficient current, R9 is the resistance value of the resistor R9 in the temperature compensation circuit, and VBE5 is the voltage difference between the base and emitter of Q5; the temperature compensation circuit compensates the bandgap reference voltage through the IR9 to achieve a bandgap reference voltage V with zero temperature coefficient. ref 。

[0056] Implementing one of the above technical solutions of the present invention has the following advantages or beneficial effects:

[0057] The bandgap reference voltage circuit in this embodiment adopts a structure without an operational amplifier, avoiding the introduction of noise and the influence of offset voltage on the bandgap reference voltage V. ref And it uses a current mirror structure to supply power to the bandgap core circuit, improving the power supply rejection ratio; adding a temperature compensation circuit to perform temperature compensation on the bandgap core circuit, improving the accuracy of the bandgap, and achieving low temperature drift within a wide temperature range. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings. In the drawings:

[0059] Figure 1 is the circuit schematic diagram of the existing bandgap reference circuit with an operational amplifier;

[0060] Figure 2 is the circuit schematic diagram of the bandgap reference voltage circuit of the embodiment of the present invention;

[0061] Figure 3 is the Cadence simulation diagram of the bandgap reference voltage circuit of the embodiment of the present invention;

[0062] Figure 4 is the step flow schematic diagram of the method for generating the bandgap reference voltage of the embodiment of the present invention;

[0063] Figure 5 is the step flow schematic diagram of the method for compensating the bandgap reference voltage of the embodiment of the present invention.

[0064] In the figure: 100, the first start-up circuit; 200, the bandgap core circuit; 300, the temperature compensation circuit; 400, the second start-up circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0065] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, various exemplary embodiments to be described below will refer to the corresponding drawings, which form a part of the exemplary embodiments and describe various exemplary embodiments that may be adopted to implement the present invention. Unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. It should be understood that they are merely examples of processes, methods, devices, etc. consistent with some aspects of the present invention disclosed in detail in the appended claims. Other embodiments may also be used, or structural and functional modifications may be made to the embodiments listed herein without departing from the scope and essence of the present invention.

[0066] In the description of the present invention, it should be understood that terms such as "center", "longitudinal", "lateral", etc. indicate the orientation or positional relationship based on the drawings shown, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the elements referred to must have a specific orientation, be constructed and operated in a specific orientation. Terms such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the technical features indicated. The meaning of the term "plurality" is two or more. The terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, an integral connection, a mechanical connection, an electrical connection, a communication connection, a direct connection, an indirect connection through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements. The term "and / or" includes any and all combinations of one or more of the related listed items. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0067] In order to illustrate the technical solutions described in the present invention, the following will be described by means of specific embodiments, and only the parts related to the embodiments of the present invention are shown.

[0068] Embodiment 1:

[0069] As Figure 2 shown, the present invention provides a low-temperature drift op-amp-free bandgap reference voltage circuit, including: a bandgap core circuit 200, a temperature compensation circuit 300, and a first startup circuit 100; the output end of the first startup circuit is connected to the input end of the bandgap core circuit, and the first startup circuit is used to make the bandgap core circuit 200 get rid of the degeneracy point, so that the bandgap core circuit 200 can quickly enter the working state; the output end of the temperature compensation circuit is connected to the input end of the bandgap core circuit, and the temperature compensation circuit is used to perform temperature compensation on the bandgap core circuit 200; the bandgap core circuit is used to generate a first temperature coefficient voltage V 负 (negative temperature coefficient voltage) and a second temperature coefficient voltage V正 (Positive Temperature Coefficient Voltage).

[0070] In this embodiment, the temperature compensation circuit 300 is used to perform temperature compensation on the bandgap core circuit, which can adjust the bandgap core circuit to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, so that the bandgap core circuit 200 obtains a reference voltage V with zero temperature coefficient. ref And the first startup circuit 100 is set. The first startup circuit 100 is connected to the bandgap core circuit 200, enabling the bandgap core circuit 200 to get rid of the degeneracy point and quickly enter the working state.

[0071] Next, the structure and principle of this bandgap reference voltage circuit will be elaborated in detail in combination with Figure 2 :

[0072] The bandgap reference voltage circuit in this embodiment includes a first startup circuit 100, a bandgap core circuit 200, a temperature compensation circuit 300, and a second startup circuit 400. The first startup circuit 100 and the temperature compensation circuit 300 are both connected to the bandgap core circuit 200, and the second startup circuit 400 is connected to the temperature compensation circuit 300.

[0073] As Figure 2 shown, the bandgap core circuit 200 includes a PMOS transistor PM1, a PMOS transistor PM2, an NMOS transistor NM1, and an NMOS transistor NM2; the PMOS transistor PM1, the PMOS transistor PM2, the NMOS transistor NM1, and the NMOS transistor NM2 form a current mirror structure. The sources of the PMOS transistor PM1 and the PMOS transistor PM2 are both connected to the power supply. The gate of the PMOS transistor PM2 is connected to the gate and drain of the PMOS transistor PM1. The gate and drain of the PMOS transistor PM1 are connected to the drain of the NMOS transistor NM1 and the first startup circuit 100; the drain of the PMOS transistor PM2 is connected to the gate and drain of the NMOS transistor NM2; the gate of the NMOS transistor NM2 is connected to the gate of the NMOS transistor NM1; the source of the NMOS transistor NM1 is connected to the bandgap core circuit 200, and the source of the NMOS transistor NM2 is connected to the bandgap core circuit 200; the gate and drain of the PMOS transistor PM1, and the drain of the NMOS transistor NM1 are all connected to the first startup circuit 100.

[0074] Specifically, the PMOS transistor PM1, the PMOS transistor PM2, the NMOS transistor NM1, and the NMOS transistor NM2 form a current mirror structure, and using the current mirror structure to supply power to the bandgap improves the power supply rejection ratio. It should be noted that the PMOS transistor PM1 and the PMOS transistor PM2 have the same size, and the NMOS transistor NM1 and the NMOS transistor NM2 have the same size.

[0075] As Figure 2As shown, the bandgap core circuit 200 further includes transistor Q1, transistor Q2, transistor Q3, resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5; the base and collector of transistor Q1 are connected to the base of transistor Q2 through resistor R2, the base and collector of transistor Q1 are connected to one end of resistor R3, the other end of resistor R3 is respectively connected to the temperature compensation circuit 300, one end of resistor R5, and one end of resistor R4, and the other end of resistor R5 is respectively connected to the source of NMOS transistor NM1 and the first startup circuit 100.

[0076] The collector of transistor Q2 is connected to the other end of resistor R4 and the base of transistor Q3; the base of transistor Q3 is connected to the other end of resistor R4 and the collector of transistor Q2, and the collector of transistor Q3 is connected to the source of MOS transistor NM2 through resistor R6; the emitters of transistor Q1 and transistor Q3 are directly grounded; transistor Q2 is grounded through resistor R1.

[0077] The bandgap core circuit 200 further includes a capacitor C1. One end of the capacitor C1 is connected to the gates of NMOS transistor NM1 and NMOS transistor NM2 and the drain of NMOS transistor NM2, and the other end is connected to the base of transistor Q3, the collector of transistor Q2, and resistor R4. The function of the capacitor C1 is to stabilize the feedback loop formed by transistor Q3, resistor R4, resistor R5, resistor R6, NMOS transistor NM1, and NMOS transistor NM2, and improve stability.

[0078] In this embodiment, transistor Q1, transistor Q2, and transistor Q3 are NPN-type transistors of the same type. In the bandgap core circuit 200, transistors are used to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, so as to obtain a reference voltage V with zero temperature coefficient. ref .

[0079] In addition, the resistance values of resistor R3 and resistor R4 are equal; and since one end of resistor R4 is connected to the base of transistor Q3, the voltage of transistor Q3 is VBE3, and since one end of resistor R3 is connected to the base and collector of transistor Q1, the voltage of transistor Q1 is VBE1.

[0080] The VBE formula for the voltage difference between the base and emitter of a transistor is:

[0081]

[0082] where VT is the thermal voltage, which is 26 mV at room temperature, I C is the collector current of the transistor, and I S is the reverse saturation current.

[0083] At this time, appropriate values are set for the triodes Q1, Q2, Q3, resistor R3, and resistor R4. Moreover, PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2 form a current mirror structure. The sizes of PMOS transistor PM1 and PMOS transistor PM2 are the same, and the sizes of NMOS transistor NM1 and NMOS transistor NM2 are the same. Therefore, the currents flowing through triodes Q1 and Q3 are the same, making VBE1 = VBE3.

[0084] Since VBE1 = VBE3, the currents flowing through both ends of resistor R3 and resistor R4 are the same, that is, the collector currents of triodes Q1 and Q2 are also approximately the same (ignoring the influence of the base current of triode Q1). At the same time, resistor R1 limits the base current of triode Q1, reducing the error. The ratio of the emitter areas of triodes Q1 and Q2 is 1:N. Then the difference in VBE between triodes Q1 and Q2, ΔVBE 1-2 is:

[0085]

[0086] ΔVBE 1-2 = VB1 - VE1 - VB2 + VE2 = VB1 - VB2 - (VE1 - VE2);

[0087] where, VE1 - VE2 is the difference in emitter voltages between triodes Q1 and Q2, VB1 - VB2 is the difference in base voltages between triodes Q1 and Q2, VT is the thermal voltage, I C is the collector current of the triode, I S is the reverse saturation current. N is any non-zero positive integer.

[0088] The difference in base voltages between triodes Q1 and Q2, VB1 - VB2, is:

[0089]

[0090] The difference in emitter voltages between triodes Q1 and Q2, VE1 - VE2, is:

[0091] VE1 - VE2 = -VR1 ≈ -I C *R1;

[0092] According to the above formula, the collector currents of triodes Q1 and Q2 can be obtained. The collector currents of triodes Q1 and Q2 are:

[0093]

[0094] Among them, β is the amplification factor of the collector current of the triode, R1 is the resistance value of resistor R1, R2 is the resistance value of resistor R2, and VR1 is the operating voltage of resistor R1.

[0095] Through the above formula, the reference voltage V ref is:

[0096]

[0097] Among them, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, VBE1 is the forward voltage drop of Q1, which is also a negative temperature coefficient voltage and is negatively correlated with temperature. is a positive temperature coefficient voltage, and VT is positively correlated with temperature.

[0098] Specifically, the positive temperature coefficient voltage increases with the increase of temperature, and the negative temperature coefficient voltage decreases with the increase of temperature. In this embodiment, the negative temperature coefficient voltage is generated by VBE of the triode Q1, that is, VBE1; the positive temperature coefficient voltage is generated by subtracting VBE1 and VBE2 of the triode Q1 and the triode Q2 and falling on the resistor R1, that is, the thermal voltage VT. As long as the resistance values of the appropriate resistors R3, R5, R1, and R2 and the value of N are set, a zero temperature coefficient voltage can be obtained.

[0099] In this embodiment, a current mirror structure is provided in the bandgap core circuit 200. The bandgap core circuit 200 uses triodes to generate a positive temperature coefficient voltage and a negative temperature coefficient voltage, thereby obtaining a zero temperature coefficient voltage. And the use of a structure without an operational amplifier can also achieve the clamping effect, without the need to design a complex operational amplifier, avoiding the influence of the offset voltage on the bandgap reference voltage, and at the same time avoiding the introduction of noise, which will not affect the accuracy of the reference voltage, and the overall structure is relatively simple.

[0100] As Figure 2 shown, the bandgap reference voltage circuit of this embodiment further includes a first startup circuit 100, and the first startup circuit 100 is connected to the bandgap core circuit 200. Since the PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2 in the bandgap core circuit 200 are of a current mirror structure and there is a degeneracy point. In order to avoid abnormal conditions in the bandgap core circuit 200 during the power-on process, the first startup circuit 100 is added to enable the bandgap core circuit 200 to start normally.

[0101] The first startup circuit 100 includes a PMOS transistor PM8, an NMOS transistor NM6, and an NMOS transistor NM5; the source of the PMOS transistor PM8 is connected to the power supply, the gate and drain of the PMOS transistor PM8 are connected to the gate of the NMOS transistor NM6 and the gate and drain of the NMOS transistor NM5, and the source of the NMOS transistor NM5 is grounded; the gate of the NMOS transistor NM6 is connected to the gate and drain of the PMOS transistor PM8 and the gate and drain of the NMOS transistor NM5; the drain of the NMOS transistor NM6 is connected to the gate and drain of the PMOS transistor PM1, the gate of the PMOS transistor PM2, and the drain of the NMOS transistor NM1; the source of the NMOS transistor NM6 is connected to the source of the NMOS transistor NM1.

[0102] As Figure 3 shown, when just powered on, the PMOS transistor PM8 and the NMOS transistor NM5 are MOS transistors in diode connection and are in the conducting state. At this time, the gate voltage of the NMOS transistor NM6 is equal to the difference between the gate voltage and the source voltage of the NMOS transistor NM5. At this time, the reference voltage V ref is in the zero state. Therefore, the NMOS transistor NM6 conducts and injects current into the bandgap core circuit 200 to get rid of the degeneracy point. After the circuit stabilizes, the reference voltage V ref is about 1.22V, that is, the source voltage of the NMOS transistor NM6 rises to 1.22V. Before that, the NMOS transistor NM6 will turn off and will not affect the normal operation of the bandgap core circuit 200. The function of the first startup circuit 100 is to enable the bandgap core circuit 200 to get rid of the degeneracy point and enable the bandgap core circuit 200 to work normally and stably.

[0103] As Figure 2As shown, the bandgap reference voltage circuit of this embodiment includes a temperature compensation circuit 300, which is connected to the bandgap core circuit 200 and is used to perform temperature compensation for the bandgap core circuit 200. The temperature compensation circuit 300 includes PMOS transistor PM3, PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM3, NMOS transistor NM4, resistor R9, and triode Q5; PMOS transistors PM3, PM4, PM6, and PM7 form a current mirror structure; the sources of PMOS transistors PM3, PM4, PM5, PM6, and PM7 are all connected to the power supply; the gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4, and the drain of PMOS transistor PM3 is connected to the bandgap core circuit 200; the gate and drain of PMOS transistor PM4 are connected and are connected to the collector of triode Q4; the emitter of triode Q4 is connected to one end of R7, and the other end of R7 is grounded; the gate of PMOS transistor PM5 is connected to the gates of PMOS transistors PM6 and PM7, and the drain is connected to the base of triode Q4 and one end of resistor R8, and the other end of resistor R8 is grounded; PMOS transistors PM6, PM7, NMOS transistor NM3, and NMOS transistor NM4 form a current mirror structure; the gate of PMOS transistor PM6 is connected to the gate of PMOS transistor PM7, the drain of PMOS transistor PM6 is connected to the drain of NMOS transistor NM3, and the drain of PMOS transistor PM7 is connected to the gate and drain of NMOS transistor NM4; the gate of NMOS transistor NM3 is connected to the gate and drain of NMOS transistor NM4, the source of NMOS transistor NM3 is connected to one end of resistor R9, and the other end of resistor R9 is grounded; the source of NMOS transistor NM4 is connected to the emitter of triode Q5, and the base and collector of triode Q5 are both grounded; the current IR9 flowing through R9 is:

[0104]

[0105] wherein, R9 is the resistance value of resistor R9, and VBE5 is the voltage difference between the base and emitter of Q5.

[0106] In this embodiment, triode Q4 is an NPN type triode, and triode Q5 is a PNP type triode.

[0107] Specifically, the function of the temperature compensation circuit 300 is to be able to perform temperature compensation in the bandgap core circuit 200. PMOS transistors PM6, PM7, NMOS transistor NM3, and NMOS transistor NM4 form a current mirror structure, and the current flowing through resistor R9 is: is a negative temperature coefficient current, VBE5 is the voltage difference between the base and emitter of Q5, the PMOS transistor PM5 mirrors the current of IR9 flowing through the resistor R8, and through reasonable settings, the triode Q4 is turned on at high temperatures. Then, through the mirroring of the PMOS transistor PM4 and the PMOS transistor PM5, the output current reaches one end of the resistor R3 and the resistor R4. When the temperature is relatively high during the operation of this embodiment, the reference voltage V generated by the bandgap core circuit 200 ref has a relatively large positive temperature coefficient. After using the temperature compensation circuit 300 to compensate the bandgap core circuit 200, low temperature drift can be achieved within a relatively wide temperature range. At the same time, a current mirror is used to supply power to the bandgap core circuit 200, improving the power supply rejection ratio.

[0108] The bandgap reference voltage circuit further includes a second startup circuit 400. The second startup circuit 400 is connected to the temperature compensation circuit 300 to enable the temperature compensation circuit 300 to get rid of the degeneracy point, thereby enabling the temperature compensation circuit 300 to work properly; the second startup circuit 400 includes a PMOS transistor PM10, a PMOS transistor PM9, and a capacitor C2; the sources of the PMOS transistor PM10 and the PMOS transistor PM9 are both connected to the power supply; the gate of the PMOS transistor PM10 is connected to the gate of the PMOS transistor PM7, the drain of the PMOS transistor PM9 is connected to the drain of the PMOS transistor PM7, the gate and drain of the NMOS transistor NM4, the drain of the PMOS transistor PM10 and the gate of the PMOS transistor PM9, and the upper plate of the capacitor C2 are connected, and the lower plate of the capacitor C2 is grounded.

[0109] Specifically, the second startup circuit 400 is connected to the temperature compensation circuit 300, which can enable the temperature compensation circuit 300 to start up properly. When the power supply is just powered on, the upper plate of the capacitor C2 is in a zero state, the PMOS transistor PM9 is turned on, injecting current into the gate and drain of the NMOS transistor NM4. After enabling the temperature compensation circuit 300 to work properly, the upper plate of the capacitor C2 will become high level. At this time, the PMOS transistor PM9 will be turned off, without affecting the normal operation of the temperature compensation circuit 300.

[0110] Figure 3 is the Cadence simulation diagram of the bandgap reference voltage circuit. From Figure 3 it can be seen that the bandgap reference voltage circuit described in this embodiment realizes a bandgap voltage with a low temperature coefficient within -55° to 150°, reducing the temperature coefficient of the bandgap reference within a wide temperature range.

[0111] The bandgap reference voltage circuit in this embodiment adopts a structure without an operational amplifier, avoiding the introduction of noise and the offset voltage to the bandgap reference voltage V refHave an impact; and use a current mirror structure to supply power to the bandgap core circuit, improving the power supply rejection ratio; add a temperature compensation circuit to perform temperature compensation on the bandgap core circuit, improving the accuracy of the bandgap, and achieving low temperature drift within a wide temperature range.

[0112] Embodiment 2:

[0113] Based on the same inventive concept, the second embodiment of the present invention also provides a method for generating a bandgap reference voltage, which is applied to the bandgap reference voltage circuit described in Embodiment 1, as Figure 4 shown, the generation method includes:

[0114] S10. Inject a startup current into the bandgap core circuit in the bandgap reference voltage circuit through the first startup circuit of the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and then the bandgap core circuit quickly enters the working state;

[0115] S20. Generate a first temperature coefficient voltage V 负 and a second temperature coefficient voltage V 正 through the bandgap core circuit; and obtain the bandgap reference voltage V 负 and the second temperature coefficient voltage V 正 , and obtain the bandgap reference voltage V ref ;

[0116] S30. Generate a negative temperature coefficient current through the temperature compensation circuit to compensate the bandgap reference voltage V ref , and realize the bandgap reference voltage V ref with a zero temperature coefficient voltage.

[0117] As an optional implementation manner, generating the first temperature coefficient voltage V 负 through the bandgap core circuit includes:

[0118] In the bandgap core circuit, based on the same resistance values of resistor R3 and resistor R4, and resistor R4 is connected to the base of transistor Q3, and resistor R3 is connected to the base and collector of transistor Q1, the voltage of resistor R4 is the forward voltage drop VBE3 of transistor Q3 and the voltage of resistor R3 is the forward voltage drop VBE1 of transistor Q1;

[0119] Based on the current mirror structure of PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2 in the bandgap core circuit, and the same sizes of PMOS transistor PM1 and PMOS transistor PM2, and the same sizes of NMOS transistor NM1 and NMOS transistor NM2, it is obtained that: VBE1 = VBE3.

[0120] As an optional implementation manner, generating the second temperature coefficient voltage V 正, including:

[0121] In the bandgap core circuit, based on the fact that the currents through resistor R3 and resistor R4 are the same, and the ratio of the emitter areas of transistor Q1 and transistor Q2 is 1:N, the difference in VBE between transistor Q1 and transistor Q2, ΔVBE, is obtained. 1-2 , and the specific formula is:

[0122]

[0123] ΔVBE 1-2 = VB1 - VE1 - VB2 + VE2 = VB1 - VB2 - (VE1 - VE2);

[0124] Where, VE1 - VE2 is the difference in emitter voltages between transistor Q1 and transistor Q2, VB1 - VB2 is the difference in base voltages between transistor Q1 and transistor Q2, VT is the thermal voltage, I C is the collector current of the transistor, and I S is the reverse saturation current;

[0125] According to ΔABE 1-2 , VB1 - VB2, and VE1 - VE2, the collector currents of transistor Q1 and transistor Q2 are obtained. The specific formulas for ΔABE 1-2 , VB1 - VB2, and VE1 - VE2 are:

[0126]

[0127] Where, β is the amplification factor of the collector current of the transistor, R1 is the resistance value of resistor R1 in the bandgap core circuit, and R2 is the resistance value of resistor R2 in the bandgap core circuit;

[0128] The obtained formulas for the collector currents of transistor Q1 and transistor Q2 are:

[0129]

[0130] According to the collector currents of transistor Q1 and transistor Q2, the second temperature coefficient voltage V 正 is obtained, and the specific formula is:

[0131]

[0132] Where, R3 is the resistance value of resistor R3 in the bandgap core circuit, and R5 is the resistance value of resistor R5 in the bandgap core circuit.

[0133] As an alternative implementation, according to the first temperature coefficient voltage V 负 and the second temperature coefficient voltage V 正 , the bandgap reference voltage V ref, including:

[0134]

[0135] Among them, V ref is the bandgap reference voltage, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, VBE1 is the forward voltage drop of Q1, and is also the first temperature coefficient voltage V 负 , and is negatively correlated with temperature. is the second temperature coefficient voltage V 正 , and VT is positively correlated with temperature.

[0136] Embodiment 3:

[0137] Based on the same inventive concept, the third embodiment of the present invention also provides a compensation method for the bandgap reference voltage, which is applied to the bandgap reference voltage circuit described in Embodiment 1, as Figure 5 shown. The compensation method includes:

[0138] S100, through the first startup circuit of the bandgap reference voltage circuit, inject a startup current into the bandgap core circuit in the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and then makes the bandgap core circuit quickly enter the working state;

[0139] S200, generate the first temperature coefficient voltage V 负 and the second temperature coefficient voltage V 正 through the bandgap core circuit, and obtain the bandgap reference voltage V 负 and the second temperature coefficient voltage V 正 , and obtain the bandgap reference voltage V ref ;

[0140] S300, generate a negative temperature coefficient current through the temperature compensation circuit. The temperature compensation circuit compensates the bandgap reference voltage V ref through IR9 to achieve a bandgap reference voltage V ref with zero temperature coefficient.

[0141] Generate a negative temperature coefficient current through the temperature compensation circuit. The specific formula is:

[0142]

[0143] Among them, IR9 is the negative temperature coefficient current, R9 is the resistance value of resistor R9 in the temperature compensation circuit, and VBE5 is the voltage difference between the base and emitter of Q5. In this embodiment, the temperature compensation circuit compensates the bandgap reference voltage through IR9 to achieve a bandgap reference voltage V ref with zero temperature coefficient.

[0144] In the compensation method of this embodiment, a second startup circuit is provided, and the second startup circuit is connected to the temperature compensation circuit. The second startup circuit can enable the temperature compensation circuit to get rid of the degeneracy point, thereby enabling the temperature compensation circuit to work normally, ensuring the normal startup of the temperature compensation circuit, and enabling the temperature compensation circuit to perform temperature compensation on the bandgap reference circuit.

[0145] The embodiment is only a special case and does not indicate that the present invention has only such an implementation manner.

[0146] The above are only the preferred embodiments of the present invention. Those skilled in the art know that without departing from the spirit and scope of the present invention, various changes or equivalent replacements can be made to these features and embodiments. Additionally, under the teaching of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application belong to the protection scope of the present invention.

Claims

1. A low-temperature-drift bandgap reference voltage circuit without an operational amplifier, characterized in that, Comprising: A bandgap core circuit, a temperature compensation circuit, and a first startup circuit; The output terminal of the first startup circuit is connected to the input terminal of the bandgap core circuit; The output terminal of the temperature compensation circuit is connected to the input terminal of the bandgap core circuit; The bandgap core circuit includes a current mirror structure and a bandgap core structure; The current mirror structure includes PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2; The sources of PMOS transistor PM1 and PMOS transistor PM2 are both connected to the power supply. The gate of PMOS transistor PM2 is connected to the gate and drain of PMOS transistor PM1. The gate and drain of PMOS transistor PM1 are connected to the drain of NMOS transistor NM1 and the first startup circuit. The drain of PMOS transistor PM2 is connected to the gate and drain of NMOS transistor NM2. The gate of NMOS transistor NM2 is connected to the gate of NMOS transistor NM1. The source of NMOS transistor NM1 is connected to the bandgap core structure, and the source of NMOS transistor NM2 is connected to the bandgap core structure. The drain of NMOS transistor NM1 is connected to the first startup circuit; The bandgap core structure includes transistor Q1, transistor Q2, transistor Q3, resistor R1, resistor R2, resistor R3, resistor R4, and resistor R5; The base and collector of transistor Q1 are connected to the base of transistor Q2 through resistor R2. The base and collector of transistor Q1 are connected to one end of resistor R3. The other end of resistor R3 is respectively connected to the temperature compensation circuit, one end of resistor R5, and one end of resistor R4. The other end of resistor R5 is respectively connected to the source of NMOS transistor NM1 and the first startup circuit; The collector of transistor Q2 is connected to the other end of resistor R4 and the base of transistor Q3; The collector of transistor Q3 is connected to the source of MOS transistor NM2 through resistor R6; The emitters of transistor Q1 and transistor Q3 are directly grounded. Transistor Q2 is grounded through resistor R1.

2. The low-temperature-drift and op-amp-free bandgap reference voltage circuit according to claim 1, wherein The first startup circuit includes PMOS transistor PM8, NMOS transistor NM6, and NMOS transistor NM5; The source of PMOS transistor PM8 is connected to the power supply. The gate and drain of PMOS transistor PM8 are connected to the gate of NMOS transistor NM6 and the gate and drain of NMOS transistor NM5. The source of NMOS transistor NM5 is grounded; The drain of NMOS transistor NM6 is connected to the gate and drain of PMOS transistor PM1, the gate of PMOS transistor PM2, and the drain of NMOS transistor NM1. The source of NMOS transistor NM6 is connected to the source of NMOS transistor NM1 and the bandgap core structure.

3. The low-temperature-drift and op-amp-free bandgap reference voltage circuit according to claim 1, wherein The temperature compensation circuit includes PMOS transistor PM3, PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM3 and NMOS transistor NM4; PMOS transistors PM3, PM4, PM6 and PM7 form a current mirror structure; the sources of PMOS transistors PM3, PM4, PM5, PM6 and PM7 are all connected to the power supply; The gate of PMOS transistor PM3 is connected to the gate of PMOS transistor PM4, and the drain of PMOS transistor PM3 is connected to the bandgap core circuit; the gate and drain of PMOS transistor PM4 are connected and then connected to the collector of transistor Q4; The gate of PMOS transistor PM5 is connected to the gates of PMOS transistor PM6 and PMOS transistor PM7, and the drain is connected to the base of transistor Q4 and resistor R8; The gate of PMOS transistor PM6 is connected to the gate of PMOS transistor PM7, the drain of PMOS transistor PM6 is connected to the drain of NMOS transistor NM3, and the drain of PMOS transistor PM7 is connected to the gate and drain of NMOS transistor NM4; the gate of NMOS transistor NM3 is connected to the gate and drain of NMOS transistor NM4, the source of NMOS transistor NM3 is connected to resistor R9; the source of NMOS transistor NM4 is connected to the emitter of transistor Q5.

4. The bandgap reference voltage circuit without an operational amplifier with low temperature drift according to claim 3, wherein The bandgap reference voltage circuit further includes a second startup circuit, and the second startup circuit is connected to the temperature compensation circuit; The second startup circuit includes PMOS transistor PM10, PMOS transistor PM9 and capacitor C2; the sources of PMOS transistors PM10 and PM9 are both connected to the power supply; the gate of PMOS transistor PM10 is connected to the gate of PMOS transistor PM7, the drain of PMOS transistor PM9 is connected to the drain of PMOS transistor PM7, the gate and drain of NMOS transistor NM4, the drain of PMOS transistor PM10 and the gate of PMOS transistor PM9, and the upper plate of capacitor C2 are connected, and the lower plate of capacitor C2 is grounded.

5. A method for generating a bandgap reference voltage, characterized in that, Applied to the bandgap reference voltage circuit according to any one of claims 1-4, the generation method includes: Through the first startup circuit of the bandgap reference voltage circuit, inject a startup current into the bandgap core circuit in the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and then makes the bandgap core circuit quickly enter the working state; Generate a first temperature coefficient voltage V 负 and a second temperature coefficient voltage V 正 through the bandgap core circuit; and obtain a bandgap reference voltage V 负 and the second temperature coefficient voltage V 正 , and obtain a bandgap reference voltage V ref ; Generate a negative temperature coefficient current through a temperature compensation circuit to compensate the bandgap reference voltage V ref to achieve a bandgap reference voltage V with zero temperature coefficient voltage ref .

6. The method for generating a bandgap reference voltage according to claim 5, wherein Generate a first temperature coefficient voltage V through the bandgap core circuit 负 , including: In the bandgap core circuit, based on the fact that the resistance values of resistor R3 and resistor R4 are the same, and resistor R4 is connected to the base of transistor Q3, and resistor R3 is connected to the base and collector of transistor Q1, the voltage of resistor R4 is obtained as the forward voltage drop VBE3 of transistor Q3, and the voltage of resistor R3 is the forward voltage drop VBE1 of transistor Q1; Based on the fact that PMOS transistor PM1, PMOS transistor PM2, NMOS transistor NM1, and NMOS transistor NM2 in the bandgap core circuit form a current mirror structure, and the sizes of PMOS transistor PM1 and PMOS transistor PM2 are the same, and the sizes of NMOS transistor NM1 and NMOS transistor NM2 are the same, such that: VBE1 = VBE3.

7. The method for generating a bandgap reference voltage according to claim 5, wherein, Generating a second temperature coefficient voltage V through the bandgap core circuit 正 , including: In the bandgap core circuit, based on the fact that the currents through resistor R3 and resistor R4 are the same, and the ratio of the emitter areas of transistor Q1 and transistor Q2 is 1:N, the difference in VBE, ΔVBE, between transistor Q1 and transistor Q2 is obtained 1-2 , and the specific formula is as follows: ΔVBE 1-2 = VB1 - VE1 - VB2 + VE2 = VB1 - VB2 - (VE1 - VE2); Among them, VE1 - VE2 is the emitter voltage difference between the triodes Q1 and Q2, VB1 - VB2 is the base voltage difference between the triodes Q1 and Q2, VT is the thermal voltage, I C is the collector current of the triode, and I S is the reverse saturation current; According to ΔVBE 1-2 , VB1 - VB2, and VE1 - VE2, the collector currents of the triode Q1 and the triode Q2 are obtained. The specific formulas for the ΔVBE 1-2 , VB1 - VB2, and VE1 - VE2 are as follows: Where, β is the amplification factor of the collector current of the triode, R1 is the resistance value of resistor R1 in the bandgap core circuit, R2 is the resistance value of resistor R2 in the bandgap core circuit, and VR1 is the operating voltage of resistor R1; The obtained collector current formulas of triode Q1 and triode Q2 are: Obtain the second temperature coefficient voltage V according to the collector currents of the triodes Q1 and Q2 正 , and the specific formula is as follows: Where, R3 is the resistance value of resistor R3 in the bandgap core circuit, and R5 is the resistance value of resistor R5 in the bandgap core circuit.

8. The generation method of the bandgap reference voltage according to claim 7, characterized in that, The obtained bandgap reference voltage V 负 is based on the first temperature coefficient voltage V 正 and the second temperature coefficient voltage V ref . Including: Among them, V ref is the bandgap reference voltage, R3 is the resistance value of resistor R3, R5 is the resistance value of resistor R5, VBE1 is the forward voltage drop of Q1, and is also the first temperature coefficient voltage V 负 , and is negatively correlated with temperature, is the second temperature coefficient voltage V 正 , and VT is positively correlated with temperature.

9. A compensation method for a bandgap reference voltage, characterized in that, Applied to the bandgap reference voltage circuit according to any one of claims 3 or 4, the compensation method includes: Injecting a startup current into the bandgap core circuit in the bandgap reference voltage circuit through the first startup circuit of the bandgap reference voltage circuit, so that the bandgap core circuit gets rid of the degeneracy point, and further enables the bandgap core circuit to quickly enter the working state; Generate a first temperature coefficient voltage V 负 and a second temperature coefficient voltage V 正 through the bandgap core circuit, and obtain a bandgap reference voltage V 负 and the second temperature coefficient voltage V 正 based on the first temperature coefficient voltage V ref ; Generating a negative temperature coefficient current through the temperature compensation circuit, and the specific formula is: Wherein, IR9 is the negative temperature coefficient current, R9 is the resistance value of the resistor R9 of the temperature compensation circuit, and VBE5 is the voltage difference between the base and emitter of Q5; the temperature compensation circuit compensates the bandgap reference voltage through the IR9 to achieve a bandgap reference voltage V with zero temperature coefficient ref .

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