A power consumption detection system and control method based on an FPGA on-chip encryption circuit

Abstract

The application discloses an on-chip encryption circuit power consumption detection system and a control method based on FPGA. The encryption circuit power consumption detection system comprises an FPGA chip, an Arm processor, a DDR controller and a peripheral interface. The control method comprises the following steps: obtaining power consumption data information; performing configuration preprocessing on the FPGA chip to obtain a configured FPGA chip; performing data acquisition and conversion processing through the configured FPGA chip to obtain converted binary sequence power consumption data information; obtaining the converted binary sequence power consumption data information and performing data preprocessing to obtain power consumption data information analysis results; and transmitting the power consumption data information analysis results to an upper computer through the peripheral interface for visual display. The embodiment of the application can monitor the instantaneous power consumption of the encryption circuit in real time, reduce the high bandwidth and resources required for transmitting and processing a large amount of real-time power consumption data, and improve the transmission efficiency of the power consumption information of the system. The application can be widely applied to the technical field of encryption circuit power consumption data analysis.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of encryption circuit power consumption data analysis, and particularly relates to an FPGA on-chip encryption circuit power consumption detection system and a control method. BACKGROUND

[0002] Field programmable gate arrays (FPGAs) deployed on commercial cloud services are increasingly popular due to the cost and computing advantages they provide. In cloud FPGAs, the multi-tenant scenario in which multiple users share a physical FPGA chip can pose a security threat. Attackers can infer secret information about the existence of encryption circuits on a remote FPGA by deploying on-chip sensors on the FPGA logic structure, which is known as a remote power analysis (RPA) attack. Power consumption changes are mainly caused by voltage fluctuations within the FPGA chip.

[0003] An advanced sensor for measuring FPGA voltage fluctuations is a time-to-digital converter (TDC). TDC allows detection of voltage fluctuations on the order of several nanoseconds, and its key building block is a delay line, which is typically implemented on an FPGA using a chain of carry logic and multiplexers. The time-to-digital converter detects voltage changes in the cloud FPGA by detecting changes in the delay of the buffer chain propagation signal; the information captured by the on-chip sensor is transmitted out of the cloud FPGA chip for analysis, but the related on-chip sensor has a wide output bit width, which requires a large amount of bandwidth to transmit the collected data. This not only increases the complexity of data transmission, but also limits the real-time performance and efficiency of the system. In addition, remote power analysis requires encryption circuits to run under different plaintext information, and a large number of power traces need to be collected to extract the secret information in the circuit, which puts high demands on the data processing and storage capabilities of the system, and has become one of the bottlenecks of power analysis attacks. Due to the high bandwidth and resources required to transmit and process large amounts of data, related technologies have low real-time performance and efficiency when performing remote power analysis, and are unable to quickly and effectively extract the required secret information.

[0004] In summary, the technical problems in the related art need to be improved. SUMMARY

[0005] The main purpose of the embodiments of the present application is to provide an FPGA on-chip encryption circuit power consumption detection system and control method, which can monitor the instantaneous power consumption of the encryption circuit in real time, reduce the high bandwidth and resources required to transmit and process large amounts of real-time power consumption data, and improve the transmission efficiency of power consumption information of the system.

[0006] To achieve the above object, one aspect of the embodiment of the present application proposes a power consumption detection system based on an on-chip encryption circuit of FPGA, which comprises an FPGA chip, an Arm processor, a DDR controller and a peripheral interface. The FPGA chip is the PL end of the power consumption detection system based on the on-chip encryption circuit of FPGA. The Arm processor is the PS end of the power consumption detection system based on the on-chip encryption circuit of FPGA. The first output end of the FPGA chip is connected with the first input end of the Arm processor. The second output end of the FPGA chip is connected with the input end of the DDR controller. The first output end of the Arm processor is connected with the input end of the FPGA chip. The second output end of the Arm processor is connected with the input end of the peripheral interface. The output end of the DDR controller is connected with the second input end of the Arm processor. Wherein:

[0007] The FPGA chip is used for acquiring power consumption data information of the encryption circuit.

[0008] The Arm processor is used for pre-processing the FPGA chip and operating and analyzing the power consumption data information to obtain power consumption data information analysis results.

[0009] The DDR controller is used for controlling data transmission between the FPGA chip and the Arm processor.

[0010] The peripheral interface is used for transmitting the power consumption data information analysis results to an upper computer.

[0011] In some embodiments, the FPGA chip comprises a power consumption acquisition module, a Hamming weight calculation module, a FIFO buffer module, an AXIDatamover IP module, a control module, an encryption circuit and a hybrid clock manager module. The output end of the hybrid clock manager module is connected with the first input end of the encryption circuit. The output end of the encryption circuit is connected with the input end of the control module. The first output end of the control module is connected with the second input end of the encryption circuit. The second output end of the control module is connected with the input end of the power consumption acquisition module. The third output end of the control module is connected with the first input end of the Hamming weight calculation module. The fourth output end of the control module is connected with the first input end of the FIFO buffer module. The fifth output end of the control module is connected with the first input end of the AXIDatamover IP module. The output end of the power consumption acquisition module is connected with the second input end of the Hamming weight calculation module. The output end of the Hamming weight calculation module is connected with the second input end of the FIFO buffer module. The output end of the FIFO buffer module is connected with the second input end of the AXIDatamover IP module. Wherein:

[0012] The power consumption collection module is configured to collect power consumption data information of the encryption circuit and perform conversion processing to output a binary sequence of the power consumption data information.

[0013] The Hamming weight calculation module is configured to convert a preset number of bits of the binary sequence of the power consumption data information to obtain converted binary sequence power consumption data information.

[0014] The FIFO cache module is configured to temporarily store the converted binary sequence power consumption data information.

[0015] The AXIDatamover IP module is configured to read the converted binary sequence power consumption data information and write the converted binary sequence power consumption data information to the DDR controller.

[0016] The control module is configured to control the operation of the encryption circuit, the power consumption collection module, the Hamming weight calculation module, the FIFO cache module, and the AXIDatamover IP module.

[0017] The encryption circuit is configured to generate an encryption operation trigger signal, and the encryption operation trigger signal includes an encryption operation start trigger signal and an encryption operation end trigger signal.

[0018] The hybrid clock manager module is configured to obtain configuration information of the Arm processor and generate a clock frequency signal and transmit the clock frequency signal to the encryption circuit.

[0019] In some embodiments, the power consumption collection module includes a plurality of on-chip voltage sensors with time-to-digital converters as cores, and the power consumption collection module specifies the number of time-to-digital converters at compile time and outputs a plurality of binary sequences of power consumption data information.

[0020] In some embodiments, the Arm processor includes an Arm processing module, a UART controller, and an SD card controller, a first output end of the Arm processing module is connected to an input end of the UART controller, and a second output end of the Arm processing module is connected to an input end of the SD card controller, wherein:

[0021] The Arm processing module is configured to perform configuration preprocessing on the FPGA chip and obtain the converted binary sequence power consumption data information.

[0022] The UART controller and the SD card controller are configured to transmit the power consumption data information to the peripheral interface.

[0023] In some embodiments, the Arm processing module includes a data processing and analysis module, an interrupt service module, and an encryption circuit configuration module, wherein:

[0024] The data processing and analysis module is configured to perform data preprocessing on the converted binary sequence power consumption data information to obtain preprocessed binary sequence power consumption data information.

[0025] The interrupt service module is configured to read transmission data of the DDR controller.

[0026] The encryption circuit configuration module is configured to perform data configuration on the encryption circuit.

[0027] In some embodiments, the peripheral interface includes a UART interface and an SD card module, wherein the UART interface and the SD card module are configured to transmit the power consumption data information analysis result to an upper computer.

[0028] To achieve the above-mentioned purpose, another aspect of the embodiment of the present application proposes a control method of a FPGA on-chip encryption circuit power consumption detection system, which comprises:

[0029] Obtaining power consumption data information;

[0030] Based on the PS end of the encryption circuit power consumption detection system, the FPGA chip is configured and preprocessed to obtain a configured FPGA chip.

[0031] Based on the PL end of the encryption circuit power consumption detection system, data acquisition and conversion processing are performed through the configured FPGA chip to obtain converted binary sequence power consumption data information.

[0032] Based on the PS end of the encryption circuit power consumption detection system, the converted binary sequence power consumption data information is obtained and data preprocessing is performed to obtain power consumption data information analysis result.

[0033] The power consumption data information analysis result is transmitted to an upper computer through a peripheral interface for visual display.

[0034] In some embodiments, based on the PS end of the encryption circuit power consumption detection system, the FPGA chip is configured and preprocessed to obtain a configured FPGA chip, which comprises:

[0035] Based on the PS end of the encryption circuit power consumption detection system;

[0036] A mixed clock manager module is configured to generate configuration information and transmit it to the FPGA chip, to dynamically adjust the clock frequency of the encryption circuit of the FPGA chip to obtain an adjusted encryption circuit.

[0037] Obtaining plaintext to be encrypted and transmitting it to the adjusted encryption circuit for encryption processing, and outputting an encryption work start trigger signal and an encryption work end trigger signal.

[0038] In some embodiments, the PL end of the encryption circuit power consumption detection system, through the configured FPGA chip, performs data acquisition and conversion processing to obtain converted binary sequence power consumption data information, including:

[0039] The PL end of the encryption circuit power consumption detection system;

[0040] According to the encryption work start trigger signal, the power consumption data information of the adjusted encryption circuit is obtained through the power consumption acquisition module;

[0041] The power consumption data information is subjected to numerical conversion processing to obtain preliminary converted binary sequence power consumption data information and is written to the FIFO buffer module;

[0042] According to the encryption work end trigger signal, the AXIDatamover IP module is configured to write the start address and data length information of the DDR controller, and according to the data packet format, the data in the FIFO buffer module is spliced into a data stream, and the converted binary sequence power consumption data information is output.

[0043] In some embodiments, the PS end of the encryption circuit power consumption detection system obtains the converted binary sequence power consumption data information and performs data preprocessing to obtain power consumption data information analysis results, including:

[0044] The PS end of the encryption circuit power consumption detection system;

[0045] An interrupt service program is executed to read the converted binary sequence power consumption data information;

[0046] A data processing program is executed to perform mean value calculation and filtering processing on the converted binary sequence power consumption data information to obtain filtered binary sequence power consumption data information;

[0047] A data analysis program is executed to perform fast Fourier transform processing on the filtered binary sequence power consumption data information to obtain the power consumption data information analysis results.

[0048] The embodiment of the application at least has the following beneficial effects: the application provides a power consumption detection system and control method based on an on-chip encryption circuit of an FPGA, the FPGA chip is set as the PL end of the power consumption detection system of the encryption circuit, and is close to the measurement source, so that higher measurement accuracy and frequency are achieved compared with off-chip power supply voltage measurement, and the voltage fluctuation can be more accurately reflected, the Arm processor is set as the PS end of the power consumption detection system of the encryption circuit, the Arm core is used to complete data preprocessing and analysis, and the data does not need to be transmitted to the host computer for analysis, so that the bandwidth of data transmission to the PS end is reduced, the instantaneous power consumption of the encryption circuit can be monitored in real time, the high bandwidth and resources required for transmission and processing of a large amount of real-time power consumption data are reduced, and the transmission efficiency of power consumption information of the system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0049] Figure 1 is a structural principle schematic diagram of a power consumption detection system based on an on-chip encryption circuit of an FPGA provided by the embodiment of the application;

[0050] Figure 2 is a step flow schematic diagram of a control method of a power consumption detection system based on an on-chip encryption circuit of an FPGA provided by the embodiment of the application;

[0051] Figure 3 is a schematic diagram of a data packet format when the power consumption acquisition module is configured as four time-to-digital sensors provided by the embodiment of the application;

[0052] Figure 4 is a schematic diagram of a data packet format when the power consumption acquisition module is configured as three time-to-digital sensors provided by the embodiment of the application;

[0053] Figure 5 is a schematic diagram of a data packet format when the power consumption acquisition module is configured as two time-to-digital sensors provided by the embodiment of the application;

[0054] Figure 6 is a schematic diagram of a data packet format when the power consumption acquisition module is configured as one time-to-digital sensor provided by the embodiment of the application. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical scheme and advantages of the application more clear, the application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the application. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the application, but are only examples of systems and methods consistent with some aspects of the embodiments of the application as described in the appended claims.

[0056] It can be understood that the terms "first", "second", and the like as used in the present application can be used herein to describe various concepts, but unless specifically stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the word "if" as used herein can be interpreted as "when" or "upon determining" or "in response to determining".

[0057] The terms "at least one", "multiple", "each", "any" and the like used in the present application include one, two or more than two, multiple includes two or more than two, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as understood by a person skilled in the art to which the present application belongs. The terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application.

[0059] Referring to Figure 1 , Figure 1 A structure principle diagram of an on-chip encryption circuit power consumption detection system based on FPGA is provided for the embodiments of the present application, referring to Figure 1 The encryption circuit power consumption detection system includes an FPGA chip, an Arm processor, a DDR controller and a peripheral interface, the FPGA chip is the PL end of the encryption circuit power consumption detection system, the Arm processor is the PS end of the encryption circuit power consumption detection system, the first output end of the FPGA chip is connected with the first input end of the Arm processor, the second output end of the FPGA chip is connected with the input end of the DDR controller, the first output end of the Arm processor is connected with the input end of the FPGA chip, the second output end of the Arm processor is connected with the input end of the peripheral interface, and the output end of the DDR controller is connected with the second input end of the Arm processor.

[0060] First of all, it should be noted that the on-chip transient power consumption analysis system based on FPGA is deployed on Xilinx ZYNQ chip to realize, the ZYNQ chip includes a PL end and a PS end, wherein the PL end is an FPGA chip, and the PS end is an Arm processor system, the PL end of the encryption circuit power consumption detection system is used to realize the encryption circuit and collect and transmit the power consumption of the encryption circuit.

[0061] The FPGA chip is used to acquire power consumption data information of the encryption circuit;

[0062] In the embodiment, the FPGA chip comprises a power consumption acquisition module, a Hamming weight calculation module, a FIFO cache module, an AXIDatamover IP module, a control module, an encryption circuit and a hybrid clock manager module, an output end of the hybrid clock manager module is connected with a first input end of the encryption circuit, an output end of the encryption circuit is connected with an input end of the control module, a first output end of the control module is connected with a second input end of the encryption circuit, a second output end of the control module is connected with an input end of the power consumption acquisition module, a third output end of the control module is connected with a first input end of the Hamming weight calculation module, a fourth output end of the control module is connected with a first input end of the FIFO cache module, a fifth output end of the control module is connected with a first input end of the AXIDatamover IP module, an output end of the power consumption acquisition module is connected with a second input end of the Hamming weight calculation module, an output end of the Hamming weight calculation module is connected with a second input end of the FIFO cache module, and an output end of the FIFO cache module is connected with a second input end of the AXIDatamover IP module, wherein the power consumption acquisition module is configured to acquire power consumption data information of the encryption circuit and perform conversion processing to output a binary sequence of the power consumption data information; the Hamming weight calculation module is configured to convert a preset bit number of the binary sequence of the power consumption data information to obtain converted binary sequence power consumption data information; the FIFO cache module is configured to temporarily store the converted binary sequence power consumption data information; the AXIDatamover IP module is configured to read the converted binary sequence power consumption data information and write the converted binary sequence power consumption data information to a DDR controller; the control module is configured to control the work of the encryption circuit, the power consumption acquisition module, the Hamming weight calculation module, the FIFO cache module and the AXIDatamover IP module; and the encryption circuit is configured to generate an encryption work trigger signal, the encryption work trigger signal comprising an encryption work start trigger signal and an encryption work end trigger signal; and the hybrid clock manager module is configured to acquire configuration information of an Arm processor and generate a clock frequency signal and transmit the clock frequency signal to the encryption circuit.

[0063] The power consumption acquisition module comprises a plurality of on-chip voltage sensors with time-to-digital converters as cores, the number of the time-to-digital converters is specified during compilation, and a plurality of binary sequences of power consumption data information are output, that is, the power consumption acquisition module comprises a plurality of on-chip voltage sensors with time-to-digital converters as cores, the number N of the time-to-digital converters can be specified during compilation, and N ranges from 1 to 4.

[0064] Specifically, the power consumption acquisition module is implemented by using a time-to-digital converter, and the time-to-digital converter is formed by cascading CARRY4 units on an FPGA chip. The clock frequency of the power consumption acquisition module is 200 MHz, which can meet the high sampling rate of instantaneous power consumption. The number of the time-to-digital converters used by the power consumption acquisition module can be configured during compilation.

[0065] The Hamming weight calculation module calculates the number of bits "1" in the plurality of binary sequences, and outputs the converted data to the FIFO buffer for temporary storage.

[0066] Specifically, the binary sequence data obtained by the power consumption acquisition module is converted into a numerical value by the Hamming weight calculation module, and is temporarily stored in the on-chip FIFO buffer of the FPGA.

[0067] The FIFO buffer is used to temporarily store the collected power consumption data, and has a width of one byte and a depth that can be configured at compile time according to the length of the collection time. The AXIDatamover IP module is used to realize direct memory access and complete the transmission of a large amount of power consumption data. After one-time transient power consumption collection is completed, the AXIDatamover IP writes the data in the FIFO buffer to the PS end DDR through the GP port.

[0068] Specifically, the FIFO buffer is connected to the AXIDatamover IP, and the AXIDatamover IP is connected to the PS through the GP port. After the transient power consumption collection is completed, the power consumption data in the FIFO buffer is transmitted to the PS end DDR through the AXIDatamover IP.

[0069] The control module is used to control the start / end of the power consumption acquisition module, the writing and reading of the FIFO buffer, and the configuration of the AXIDatamover IP to write the start address, data length information and data block content to the DDR, and to trigger the interrupt of the PS end after the collection is completed.

[0070] Specifically, the control module transmits the configuration of the first address and the power consumption data length information to the AXIDatamover IP core, and after the transmission of the PL end AXIDatamover IP core is completed, the PS is notified by interrupt that the current transient power consumption data collection is completed.

[0071] The encryption circuit is an encryption circuit running on the FPGA chip. The encryption circuit provides the control module with trigger signals for the start and end of encryption. Meanwhile, the control module provides the encryption circuit with plaintext that needs to be encrypted. The hybrid clock manager module is used to receive configuration information from the PS end Arm processor, and dynamically modify the clock frequency provided to the encryption circuit during runtime.

[0072] The Arm processor is used to configure and preprocess the FPGA chip and to perform operation and analysis on the power consumption data information to obtain power consumption data information analysis results.

[0073] First of all, it needs to be pointed out that the PS end of the power consumption detection system of the encryption circuit is used for complex processing and analysis of the collected power consumption data, and performs specific algorithms to obtain the required results, and configures the encryption circuit of the PL end.

[0074] The PS end reads the DDR memory, and the Arm core completes the processing and analysis of real-time power consumption data such as filtering and fast Fourier transform. The data processing and analysis algorithm is realized by programming. The PS end also implements a UART controller and an SD card controller. The results of data processing and analysis can be further transmitted to the host computer through the UART serial port or the SD card. The PS end can configure the runtime clock frequency and plaintext input of the encryption circuit through the HP port. The encryption circuit can be a hardware accelerator dedicated to encryption algorithms or a soft-core processor running encryption algorithms, and is located on the same FPGA chip as the power consumption measurement module.

[0075] In the embodiment, the Arm processor includes an Arm processing end module, a UART controller and an SD card controller. The first output end of the Arm processing end module is connected with the input end of the UART controller, and the second output end of the Arm processing end module is connected with the input end of the SD card controller. The Arm processing end module is used for configuration preprocessing of the FPGA chip and obtaining converted binary sequence power consumption data information. The UART controller and the SD card controller are used for transmitting the power consumption data information to the peripheral interface.

[0076] It should be noted that the UART controller is used for controlling the serial port of the peripheral, and outputting the progress of power consumption data collection, power consumption analysis state and encryption circuit running state and other information to the host computer. The SD card controller is used for managing the data read and write of the SD card of the peripheral, and writing the collected power consumption data to the SD card for reading by the host computer.

[0077] The Arm processing end module includes a data processing and analysis module, an interrupt service module and an encryption circuit configuration module. The data processing and analysis module is used for data preprocessing of the converted binary sequence power consumption data information to obtain preprocessed binary sequence power consumption data information. The interrupt service module is used for reading the transmission data of the DDR controller. The encryption circuit configuration module is used for data configuration of the encryption circuit.

[0078] Specifically, the Arm processor contains three main programs, one is an interrupt processing function, which reads the data in the DDR after receiving the interrupt. The data packet in the DDR is in units of words, and each word contains 4 bytes. The second is a data processing and analysis algorithm, which is used for pre-processing, analysis and transmission of power consumption data. The pre-processing calculates the mean value and filters the power consumption data. The analysis performs a fast Fourier transform on the power consumption data. The third is an encryption circuit configuration program, which is used to configure the number of power consumption trace collection, the plaintext that needs to be encrypted by the encryption circuit, the clock frequency of the encryption circuit and the transmission mode of the power consumption data (UART serial port or SD card) at runtime.

[0079] The DDR controller is used to control the data transmission between the FPGA chip and the Arm processor.

[0080] In this embodiment, the DDR controller provides storage and access functions of data, and is used for transmission of a large amount of power consumption data between the PL and the PS.

[0081] The peripheral interface is used to transmit the power consumption data information analysis result to the host computer.

[0082] In this embodiment, the peripheral interface includes a UART interface and an SD card module, wherein the UART interface and the SD card module are used to transmit the power consumption data information analysis result to the host computer.

[0083] Specifically, the peripheral interface includes a UART interface and an SD card, which is used for communication and data transmission between the ZYNQ chip and the host computer, and is connected to the host computer at runtime.

[0084] Please refer to Figure 2 The application also provides a control method of the FPGA on-chip encryption circuit power consumption detection system, which can realize the FPGA on-chip encryption circuit power consumption detection system. The control method includes the following steps:

[0085] S100, obtaining power consumption data information;

[0086] S200, based on the PS end of the encryption circuit power consumption detection system, configuring and preprocessing the FPGA chip to obtain the configured FPGA chip.

[0087] It should be noted that in some embodiments, step S200 can include: S210, based on the PS end of the encryption circuit power consumption detection system; S220, generating configuration information and transmitting it to the mixed clock manager module of the FPGA chip, dynamically adjusting the clock frequency of the encryption circuit of the FPGA chip to obtain the adjusted encryption circuit; S230, obtaining the plaintext to be encrypted and transmitting it to the adjusted encryption circuit for encryption processing, and outputting the encryption work start trigger signal and the encryption work end trigger signal.

[0088] S300, based on the PL end of the encryption circuit power consumption detection system, data acquisition and conversion processing are performed through the configured FPGA chip to obtain converted binary sequence power consumption data information;

[0089] It should be noted that in some embodiments, step S300 can include: S310, based on the PL end of the encryption circuit power consumption detection system; S320, according to the encryption work start trigger signal, the power consumption data information of the adjusted encryption circuit is obtained through the power consumption acquisition module; S330, the power consumption data information is subjected to numerical conversion processing to obtain the preliminary converted binary sequence power consumption data information and is written to the FIFO cache module; S340, according to the encryption work end trigger signal, the start address and data length information of the AXIDatamover IP module written to the DDR controller are configured, and the data in the FIFO cache module is spliced into a data stream according to the data packet format, and the converted binary sequence power consumption data information is output.

[0090] S400, based on the PS end of the encryption circuit power consumption detection system, the converted binary sequence power consumption data information is obtained and data preprocessing is performed to obtain power consumption data information analysis results;

[0091] It should be noted that in some embodiments, step S400 can include: S410, based on the PS end of the encryption circuit power consumption detection system; S420, an interrupt service program is executed to read the converted binary sequence power consumption data information; S430, a data processing program is executed to perform mean value calculation and filtering processing on the converted binary sequence power consumption data information to obtain filtered binary sequence power consumption data information; S440, a data analysis program is executed to perform fast Fourier transform processing on the filtered binary sequence power consumption data information to obtain power consumption data information analysis results.

[0092] S500, the power consumption data information analysis results are transmitted to the host computer through the peripheral interface for visual display.

[0093] As described above, in the specific embodiments of the present application, the encryption circuit to be tested is connected to the power consumption acquisition and analysis system;

[0094] The PS end Arm processor configures the plaintext to be encrypted of the encryption circuit and a hybrid mode clock management module; the control module receives a trigger signal that the encryption circuit starts to encrypt, sends a control signal to the power consumption acquisition module, and acquires the instantaneous power consumption of the encryption circuit in operation, and the instantaneous power consumption data is temporarily stored in the FIFO buffer after being converted into a numerical value by the Hamming weight calculation module; the control module receives a trigger signal that the encryption circuit ends to encrypt, configures the AXIDatamover module to write the start address of the DDR and the data length information, and reads out the data in the FIFO buffer, splices the data in the FIFO buffer into a data stream according to the data packet format, and supplies the AXIDatamover IP to transmit to the PS end DDR. After the AXIDatamover IP transmission ends, the control module triggers an interrupt signal to the PS end; after the PS end receives the interrupt, the PS end enters an interrupt service program to read the power consumption data in the DDR; the PS end executes power consumption data preprocessing, analysis or storage and the like according to the upper computer command, and transmits the progress, collection state and encryption module plaintext to be encrypted and the like of the current power consumption data collection to the upper computer.

[0095] In addition, it also needs to be explained that 1-4 TDCs, i.e., time-to-digital converters, can be configured, and for different numbers of TDCs, the data packet format is: power consumption data length, power consumption data, and end symbol. For different numbers of time-to-digital converters, the format of the power consumption data in the data packet is different. In one collection, the power consumption data has t sampling points, and the power consumption data in the data packet has t words. The output of the nth time-to-digital converter corresponds to the nth byte of the word in the data packet. For the case that the power consumption module is configured with 4 time-to-digital converters (the serial numbers are 0, 1, 2, and 3), the data packet format is as shown in Figure 3 The 0th word in the data packet is fixed as the power consumption data length, the 1st-tth word is the power consumption data, and the values of the 4 time-to-digital converters (the serial numbers are 0, 1, 2, and 3) correspond to the 0th, 1st, 2nd, and 3rd bytes of each word, respectively. The t+1th word of the data packet is fixed as the end symbol, and the value is 0xdeadbeef. For the case that the power consumption module is configured with 3 time-to-digital converters (the serial numbers are 0, 1, and 2), the contents of the 0th word and the t+1th word of the data packet are unchanged, the 3rd byte of the power consumption data corresponding to the 1st-tth word is always 0x00, as shown in Figure 4 For the case that the power consumption module is configured with 2 or 1 time-to-digital converter, the data packet format is as shown in Figure 5 、 Figure 6 .

[0096] Therefore, the embodiment of the present application has the following technical effects:

[0097] 1) Using the CARRY4 logic on the FPGA chip to build a time-to-digital converter (TDC), compared with the off-chip power supply voltage measurement, it has higher measurement accuracy and frequency (200MHz), which can more accurately reflect the voltage fluctuation. In addition, the on-chip sensor can be instantiated at any location of the FPGA layout, and multiple TDCs can be configured to measure the source closely, thereby achieving more accurate power consumption monitoring.

[0098] 2) Since the Hamming distance calculation circuit is used at the PL end, the bandwidth of data transmission to the PS end is reduced, and further, the PS end can use the Arm core to complete the preprocessing and analysis of data, without the need to transmit to the host computer for analysis, which brings the advantage of real-time power consumption analysis.

[0099] 3) Since the UART and SD card controller are configured at the PS end, the way of data transmission to the host computer can be flexibly selected according to the size of the power consumption data, and this configuration not only improves the flexibility and adaptability of data transmission, but also optimizes the data transmission path according to the specific needs, further improving the overall performance of the system.

[0100] It can be understood that the contents in the above method embodiments are all applicable to the system embodiments, the system embodiments specifically realize the same functions as the above method embodiments, and achieve the same beneficial effects as the above method embodiments.

[0101] The preferred embodiments of the application are described above with reference to the accompanying drawings, but this does not limit the scope of the application. Any modifications, equivalent replacements and improvements made by those skilled in the art without departing from the scope and essence of the application should be within the scope of the application.

Claims

1. A power consumption detection system based on FPGA on-chip encryption circuit, characterized in that, The encryption circuit power consumption detection system includes an FPGA chip, an Arm processor, a DDR controller, and a peripheral interface. The FPGA chip is the PL terminal of the encryption circuit power consumption detection system, and the Arm processor is the PS terminal. The first output terminal of the FPGA chip is connected to the first input terminal of the Arm processor, and the second output terminal of the FPGA chip is connected to the input terminal of the DDR controller. The first output terminal of the Arm processor is connected to the input terminal of the FPGA chip, and the second output terminal of the Arm processor is connected to the input terminal of the peripheral interface. The output terminal of the DDR controller is connected to the second input terminal of the Arm processor. Wherein: The FPGA chip includes a power consumption acquisition module and a Hamming weight calculation module; The power consumption acquisition module employs a time-to-digital converter. This module is used to acquire power consumption data from the encryption circuit, perform conversion processing, and output a binary sequence of power consumption data. The power consumption data is instantaneous power consumption data. The Hamming weight calculation module is used to convert the binary sequence of the power consumption data information into a preset number of bits to obtain the converted binary sequence power consumption data information. The Arm processor is used to perform configuration preprocessing on the FPGA chip and to perform calculation and analysis on the power consumption data information to obtain the power consumption data information analysis results; The DDR controller is used to control the data transmission between the FPGA chip and the Arm processor; The peripheral interface is used to transmit the power consumption data information analysis results to the host computer. The Arm processor includes an Arm processing module, a UART controller, and an SD card controller. A first output of the Arm processing module is connected to an input of the UART controller, and a second output of the Arm processing module is connected to an input of the SD card controller. The Arm processing module is used for configuration preprocessing of the FPGA chip and obtaining the converted binary sequence power consumption data information; The UART controller and the SD card controller are used to transmit the power consumption data information to the peripheral interface.

2. The encryption circuit power consumption detection system according to claim 1, characterized in that, The FPGA chip includes a FIFO buffer module, an AXI Datamover IP module, a control module, an encryption circuit, and a hybrid clock manager module. The output of the hybrid clock manager module is connected to the first input of the encryption circuit. The output of the encryption circuit is connected to the input of the control module. The first output of the control module is connected to the second input of the encryption circuit. The second output of the control module is connected to the input of the power consumption acquisition module. The third output of the control module is connected to the first input of the Hamming weight calculation module. The fourth output of the control module is connected to the first input of the FIFO buffer module. The fifth output of the control module is connected to the first input of the AXI Datamover IP module. The output of the power consumption acquisition module is connected to the second input of the Hamming weight calculation module. The output of the Hamming weight calculation module is connected to the second input of the FIFO buffer module. The output of the FIFO buffer module is connected to the second input of the AXI Datamover IP module. Wherein: The FIFO cache module is used to temporarily store the converted binary sequence power consumption data information; The AXI Datamover IP module is used to read the converted binary sequence power consumption data information and write it to the DDR controller; The control module is used to control the operation of the encryption circuit, the power consumption acquisition module, the Hamming weight calculation module, the FIFO buffer module, and the AXI Datamover IP module; The encryption circuit is used to generate encryption operation trigger signals, which include an encryption operation start trigger signal and an encryption operation end trigger signal. The hybrid clock manager module is used to obtain the configuration information of the Arm processor and generate a clock frequency signal and transmit it to the encryption circuit.

3. The encryption circuit power consumption detection system according to claim 2, characterized in that, The power consumption acquisition module includes several on-chip voltage sensors with time-to-digital converters as the core. The number of time-to-digital converters is specified during compilation, and the power consumption acquisition module outputs a binary sequence of power consumption data information.

4. The encryption circuit power consumption detection system according to claim 1, characterized in that, The Arm processing module includes a data processing and analysis module, an interrupt service module, and an encryption circuit configuration module, wherein: The data processing and analysis module is used to preprocess the converted binary sequence power consumption data information to obtain preprocessed binary sequence power consumption data information. The interrupt service module is used to read the transmission data of the DDR controller; The encryption circuit configuration module is used to configure the encryption circuit with data.

5. The encryption circuit power consumption detection system according to claim 1, characterized in that, The peripheral interface includes a UART interface and an SD card module, wherein the UART interface and the SD card module are used to transmit the power consumption data information analysis results to the host computer.

6. A control method for a power consumption detection system based on an FPGA-based on-chip encryption circuit as described in any one of claims 1-5, characterized in that, The control method includes the following steps: Obtain power consumption data; Based on the PS end of the encryption circuit power consumption detection system, the FPGA chip is pre-configured to obtain the configured FPGA chip. Based on the PL terminal of the encrypted circuit power consumption detection system, data acquisition and conversion processing are performed through the configured FPGA chip to obtain the converted binary sequence power consumption data information. Based on the PS terminal of the encrypted circuit power consumption detection system, the converted binary sequence power consumption data information is acquired and preprocessed to obtain the power consumption data information analysis results. The power consumption data analysis results are transmitted to the host computer for visualization display via the peripheral interface.

7. The method according to claim 6, characterized in that, The PS terminal of the encryption circuit power consumption detection system performs configuration preprocessing on the FPGA chip to obtain the configured FPGA chip, including: PS terminal based on encrypted circuit power consumption detection system; The hybrid clock manager module generates configuration information and transmits it to the FPGA chip to dynamically adjust the clock frequency of the encryption circuit of the FPGA chip, thereby obtaining the adjusted encryption circuit. The plaintext to be encrypted is acquired and transmitted to the adjusted encryption circuit for encryption processing, and an encryption start trigger signal and an encryption end trigger signal are output.

8. The method according to claim 7, characterized in that, The PL terminal of the encrypted circuit-based power consumption detection system performs data acquisition and conversion processing through the configured FPGA chip to obtain converted binary sequence power consumption data information, including: PL terminal based on encrypted circuit power consumption detection system; Based on the encryption start trigger signal, the power consumption data of the adjusted encryption circuit is obtained through the power consumption acquisition module; The power consumption data is converted into a preliminary binary sequence power consumption data and written to the FIFO cache module. Based on the encryption completion trigger signal, the AXI Datamover IP module is configured to write the starting address and data length information of the DDR controller, and the data in the FIFO cache module is concatenated into a data stream according to the data packet format, and the converted binary sequence power consumption data information is output.

9. The method according to claim 6, characterized in that, The PS terminal of the encrypted circuit-based power consumption detection system acquires the converted binary sequence power consumption data information and performs data preprocessing to obtain power consumption data information analysis results, including: PS terminal based on encrypted circuit power consumption detection system; Execute the interrupt service routine to read the converted binary sequence power consumption data information; The data processing program is executed to perform averaging and filtering on the converted binary sequence power consumption data information to obtain the filtered binary sequence power consumption data information. The data analysis program is executed to perform a fast Fourier transform on the filtered binary sequence power consumption data information to obtain the analysis results of the power consumption data information.

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