A memory chip testing method and testing system

Abstract

The present invention provides a test method and a test system for a memory chip, and relates to the field of storage. The test method includes: installing a chip to be tested on a test board, and configuring a preset test temperature and a preset test voltage to form an initial test environment; a main control unit starts a read-write stress test program to perform a stress test on the chip to be tested; counting the number of bad blocks and the number of error bits of the chip to be tested under the initial test environment; changing the preset test temperature and the preset test voltage, and repeatedly performing stress tests on the chip to be tested until the chip to be tested completes the stress tests under all preset test environments; counting the number of bad blocks and the number of error bits of the chip to be tested under all preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weights of each preset test environment; and grading the chip to be tested according to the weighted number of bad blocks and the weighted number of error bits. The test method and the test system provided by the present invention can classify chips comprehensively, quickly and accurately.

Description

Technical Field

[0001] The present invention relates to the field of storage, and in particular to a testing method and a testing system for a storage chip. Background Art

[0002] With the widespread application of embedded multi media cards (eMMC) in terminal products such as TVs, set-top boxes, tablets and mobile phones, the performance and reliability requirements of eMMC are getting higher and higher, especially to ensure that the data stored in eMMC is stable and reliable. eMMC is composed of an advanced RISC machine (ARM) as a controller and a non-volatile storage medium (NAND Flash). Among them, ARM runs the controller software, and NAND Flash is a high-density and low-cost storage medium that is widely used in various devices.

[0003] During the production and use of NAND Flash chips, bad blocks will be generated, which will damage the overall performance and reliability of the chip. Therefore, NAND Flash chips must be tested and classified to adapt the chips to different application scenarios according to their levels. However, the current testing methods for NAND Flash chips have problems such as single test indicators, inaccurate classification, long test cycles, and being unfavorable for large-scale promotion and application. Summary of the invention

[0004] The purpose of the present invention is to provide a testing method and testing system for memory chips, which can quickly, comprehensively and accurately test and classify chips, and adapt chips of different levels to different application scenarios.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a method for testing a memory chip, which at least comprises the following steps:

[0007] Install the chip to be tested on the test board, and configure the preset test temperature and preset test voltage to form an initial test environment;

[0008] The main control unit starts a read-write stress test program to perform a stress test on the chip to be tested;

[0009] Counting the number of bad blocks and the number of error bits of the chip under test in the initial test environment;

[0010] Changing the preset test temperature and the preset test voltage, and repeatedly performing stress testing on the chip to be tested until the chip to be tested completes stress testing under all preset test environments;

[0011] Counting the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weight of each of the preset test environments; and

[0012] The chip to be tested is graded according to the weighted number of bad blocks and the weighted number of error bits.

[0013] In an embodiment of the present invention, four preset test environments are set according to the preset test temperature and the preset test voltage.

[0014] In one embodiment of the present invention, a chip to be tested is mounted on a test board, and a preset test temperature and a preset test voltage are configured to form an initial test environment, including the following steps:

[0015] Provide a new chip to be tested;

[0016] Burning the firmware program into the chip to be tested;

[0017] Install the chip to be tested on the test board and confirm that the installation position is correct and there is no contact problem; and

[0018] The test board is configured with a preset test temperature and a preset test voltage to form an initial test environment, and a power supply test is performed on the test board.

[0019] In one embodiment of the present invention, counting the number of bad blocks and the number of error bits of the chip under test in the initial test environment includes the following steps:

[0020] Under the initial test environment, counting the single block error bit number of each flash memory block in the chip to be tested, obtaining a plurality of the single block error bit numbers, and recording the values ​​in a preset position of the chip to be tested;

[0021] Determining whether the single-block error bit number of each flash memory block exceeds the processing capability of the error correction module;

[0022] When the single-block error bit number of the flash memory block exceeds the processing capacity of the error correction module, the flash memory block is determined to be a bad block, the flash memory block is added to the bad block management, and the number of bad blocks of the chip to be tested and the total number of error bits of all flash memory blocks of the chip to be tested are counted; and

[0023] When the single-block error bit number of the flash memory block does not exceed the processing capacity of the error correction module, the stress test is repeatedly performed on the next flash memory block in the chip to be tested until all the flash memory blocks in the chip to be tested have completed the stress test.

[0024] In one embodiment of the present invention, before changing the preset test temperature and the preset test voltage, the following steps are also included:

[0025] Determine whether the chip under test has completed all stress tests under the preset test environment;

[0026] When the chip under test completes the stress test under all the preset test environments, the number of bad blocks and the number of error bits of the chip under test under all the preset test environments are counted, and the weighted number of bad blocks and the weighted number of error bits are calculated according to the weight of each of the preset test environments; and

[0027] When the chip under test has not completed all stress tests under the preset test environments, the preset test temperature and the preset test voltage are changed, and the stress test is repeatedly performed on the chip under test until the chip under test completes all stress tests under the preset test environments.

[0028] In one embodiment of the present invention, counting the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weight of each of the preset test environments, includes the following steps:

[0029] According to the weight of each of the preset test environments, weighting the plurality of single block error bit numbers obtained by statistics in each of the preset test environments to obtain a weighted single block error bit number;

[0030] According to the weight of each of the preset test environments, weighting the plurality of total error bit numbers obtained by statistics in each of the preset test environments to obtain a weighted total error bit number; and

[0031] According to the weight of each of the preset test environments, the multiple bad block numbers obtained by counting in each of the preset test environments are weighted to obtain a weighted bad block number.

[0032] In one embodiment of the present invention, before grading the chip to be tested according to the number of bad blocks and the number of error bits, the following steps are also included:

[0033] Determining whether the life test of the chip to be tested is completed; and

[0034] When the life test is not completed, the chip to be tested is worn out, and the burning and stress tests are repeatedly performed on the chip to be tested.

[0035] In one embodiment of the present invention, the chip to be tested is graded according to the number of bad blocks and the number of error bits, comprising the following steps:

[0036] When the life test is completed, the chip to be tested is graded according to the weighted single block error bit number, the weighted total error bit number and the weighted bad block number.

[0037] The present invention also provides a memory chip testing system, comprising at least:

[0038] At least one test board, on which the chip to be tested is communicatively connected, and is configured with a plurality of preset test environments, wherein the preset test voltages and the preset test temperatures are different in the plurality of preset test environments;

[0039] A main control module is communicatively connected to the chip to be tested and is configured with a read-write stress test program to perform a stress test on the chip to be tested;

[0040] a bad block monitoring module, which counts the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and classifies the chip under test according to the weights of all the preset test environments; and

[0041] A power supply module supplies power to the test board, the main control module and the bad block monitoring module.

[0042] In an embodiment of the present invention, the test system further includes a temperature sensing module and a voltage monitoring module, and the temperature sensing module and the voltage monitoring module are respectively connected to the main control module.

[0043] As described above, the present invention provides a test method and a test system for a memory chip, which can comprehensively, quickly and accurately test and classify the chip, and adapt the chip to different application scenarios. Moreover, the test method and the test system provided by the present invention can monitor the test results of the chip in real time, comprehensively monitor the number of bad blocks and error bits of the chip, and improve the overall performance and reliability of the chip.

[0044] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0046] Figure 1 FIG. 4 is a schematic diagram of a test board in one embodiment of the present invention.

[0047] Figure 2 FIG. 4 is a schematic diagram of a testing system in one embodiment of the present invention.

[0048] Figure 3 The figure is a flow chart of a method for testing a memory chip according to an embodiment of the present invention.

[0049] Figure 4 for Figure 3 Flowchart of step S11 in FIG.

[0050] Figure 5 for Figure 3 Flowchart of step S13 in FIG.

[0051] Figure 6 for Figure 3 Flowchart of steps S14 and S15 in FIG.

[0052] Figure 7 for Figure 3 Flowchart of step S15 in FIG.

[0053] Figure 8 for Figure 3 Flowchart of step S16 in FIG.

[0054] Fig. 9 The figure is a trend chart of the number of error bits in 8 blocks of a chip under test under four test environments.

[0055] Description of labels:

[0056] 101. Power module; 102. Test board; 103. Communication interface; 104. Main control module; 105. Temperature sensor module; 106. Voltage monitoring module; 107. Transceiver interface; 108. Read-only storage module; 109. Random access storage module; 110. Error correction module; 111. Data transmission module; 112. Bad block monitoring module; 113. Transmission interface module; 114. Storage block; 1141. Code storage area; 1142. Field firmware update storage area; 1143. Table storage area; 1144. General data storage area. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0058] As a high-density and low-cost storage body, NAND Flash chips are widely used in various devices such as USB storage devices such as U disks, SD cards, mobile phones, and solid-state hard disks. Due to the manufacturing process and cost, the NAND Flash chip itself contains bad blocks when it leaves the factory, and bad blocks will inevitably be generated inside the NAND Flash chip during use. Due to the existence of bad blocks, when programming or erasing this block, operation errors will occur, affecting the overall performance and reliability of the NAND Flash chip. Through the test method and test system provided by the present invention, the number of bad blocks and the number of error bits of the chip can be calculated under different test temperatures, test voltages, life cycles, etc., and the chips can be graded, so that the overall health status of the chip can be monitored quickly, accurately and comprehensively, and the overall performance and reliability of the chip can be improved. The test system provided by the present invention can be used to screen out chips of various grades. In the present invention, for example, the test system and test method of the present invention are described by taking the classification of chips into three levels: consumer grade, industrial grade, and automotive grade as an example.

[0059] See also Figure 1 to Figure 2 As shown, the present invention also provides a test system for a memory chip, for example, including a power module 101, a test board 102, a main control module 104, and a bad block monitoring module 112. Among them, the test board 102 is communicatively connected to a chip to be tested, and is configured with a variety of preset test environments, the main control module 104 is configured with a read-write stress test program to perform a stress test on the chip to be tested, and the bad block monitoring module 112 counts the number of bad blocks and the number of error bits of the chip to be tested under a variety of preset test environments, and grades the chip to be tested according to the weights of each of the multiple preset test environments.

[0060] See also Figure 1 As shown, in one embodiment of the present invention, the test board 102 is used to install the chip to be tested, and the test board 102 is configured with a plurality of preset test environments. Among them, there is at least one test board 102, for example. In this embodiment, there are i*j test boards 102, for example, and each of the i*j test boards 102 can be equipped with a chip to be tested to improve the test efficiency of the chip. Moreover, in this embodiment, there are four preset test environments, for example, high temperature and high pressure, high temperature and low pressure, low temperature and high pressure, and low temperature and low pressure.

[0061] See also Figure 2 As shown, in one embodiment of the present invention, the main control module 104 is in communication connection with the chip under test and is configured with a read-write stress test program to perform a stress test on the chip under test to identify the specific locations of bad blocks and error bits in the chip under test.

[0062] See also Figure 2As shown, in one embodiment of the present invention, the bad block monitoring module 112 counts the number of bad blocks and the number of error bits of the chip under test in multiple preset test environments, and grades the chip under test according to the weights of each of the multiple preset test environments.

[0063] See also Figure 1 to Figure 2 As shown, in one embodiment of the present invention, the power module 101 supplies power to the test board 102, the main control module 104, the bad block monitoring module 112 and other modules, so that each module can work smoothly.

[0064] See also Figure 1 As shown, in one embodiment of the present invention, the test system further includes a communication interface 103, which connects the test board 102 and the host computer and is responsible for the communication between the test board 102 and the host computer. In this embodiment, the communication interface 103 is, for example, a Universal Serial Bus (USB).

[0065] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a temperature sensor module 105, which is connected to the main control module 104. By setting the temperature sensor module 105, the ambient temperature change around the chip to be tested can be monitored, and the temperature signal can be transmitted to the main control module 104.

[0066] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a voltage monitoring module 106, which is connected to the main control module 104. By setting the voltage monitoring module 106, the high and low voltage changes of the chip under test can be monitored, and the pressure signal can be transmitted to the main control module 104.

[0067] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a transceiver interface 107, which is connected to the main control module 104. The transceiver interface 107 is, for example, an asynchronous transceiver. Through the transceiver interface 107, the main control module 104 can communicate with the peripheral device in serial to exchange data.

[0068] See also Figure 2As shown, in one embodiment of the present invention, the test system further includes a read-only storage module 108, and the read-only storage module 108 is connected to the main control module 104. The read-only storage module 108 is, for example, a non-volatile memory (ROM) for long-term data storage. In this embodiment, the read-only storage module 108 stores, for example, firmware, which is, for example, a set of pre-written instructions that instruct the main control module 104 how to start and run. The instructions include, for example, device initialization, peripheral configuration, and a boot loader, etc. The boot loader can be used to load updated programs or operating systems, etc.

[0069] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a random access memory module 109, which is connected to the main control module 104. The random access memory module 109 is, for example, a volatile memory (Random Access Memory, RAM) for temporarily storing data and program codes. By setting the random access memory module 109 to temporarily store data, when the main control module 104 executes a program, the program code can be loaded from the read-only storage module 108 to the random access memory module 109 for execution.

[0070] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a transmission interface module 113, which is connected to the main control module 104 and the host computer and is responsible for the communication between the main control module 104 and the host computer. Through the transmission interface module 113, the statistical results of the bad block monitoring module 112 can be transmitted to the host computer, so that the test data can be displayed in an integrated manner, and a signal quality specification report can also be generated.

[0071] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a storage block 114, which is a physical unit in the memory chip for storing data. In this embodiment, the interior of the storage block 114 is divided into, for example, a code storage area 1141, a field firmware update (FFU) storage area 1142, a table storage area 1143, and a general data storage area 1144, etc., to store CODE, FFU data, Table, DATA, etc.

[0072] See also Figure 2As shown, in one embodiment of the present invention, the test system further includes an error correction module 110, and the error correction module 110 is connected to the main control module 104 and the bad block monitoring module 112. By setting the error correction module 110, errors that occur in the storage chip during the process of storing or transmitting data are detected and corrected, thereby improving the reliability and integrity of the data. In this embodiment, the error correction module 110 uses algorithms such as low-density parity check (LDPC) or BCH code to check the data.

[0073] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a data transmission module 111, and the data transmission module 111 is connected to the error correction module 110, the storage block 114 and the bad block monitoring module 112. By setting the data transmission module 111, the reading, transmission and writing of data can be automatically processed, allowing the main control module 104 to process data transmission in parallel while processing other tasks, thereby reducing the burden on the main control module 104.

[0074] See also Figure 2 As shown, in one embodiment of the present invention, the test system further includes a DMA channel, and the DMA channel is arranged between the data transmission module 111 and the storage block 114. Among them, the DMA channel is, for example, multiple. In this embodiment, the DMA channel is, for example, 3 types, and the 3 DMA channels are, for example, CODE DMA, Table DMA and DATA DMA. Among them, CODE DMA connects the code storage area 1141 and the data transmission module 111 for transmitting code execution data, Table DMA connects the table storage area 1143 and the data transmission module 111 for looking up table data, and DATA DMA connects the ordinary data storage area 1144 and the data transmission module 111 for ordinary data transmission. By setting up a variety of DMA channels, different types of data operations can be effectively parallelized, and the parallel capability of data processing can be improved, which is conducive to speeding up response time, improving user experience and processing complex calculations. Moreover, the introduction of different DMA channels can meet the needs of storage chips in data-intensive application scenarios while ensuring that data is quickly and accurately transmitted within the storage chip.

[0075] See also Figure 3 As shown, the test system described above is used to test the chip to be tested, and the test method at least includes steps S11-S16.

[0076] Step S11: Install the chip to be tested on the test board, and configure a preset test temperature and a preset test voltage to form an initial test environment.

[0077] Step S12: The main control unit starts a read-write stress test program to perform a stress test on the chip to be tested.

[0078] Step S13: Count the number of bad blocks and the number of error bits of the chip to be tested in the initial test environment.

[0079] Step S14, changing the preset test temperature and the preset test voltage, and repeatedly performing stress testing on the chip to be tested until the chip to be tested completes stress testing under all preset test environments.

[0080] Step S15, counting the number of bad blocks and the number of error bits of the chip under test in all preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weight of each preset test environment.

[0081] Step S16: classify the chips to be tested according to the weighted number of bad blocks and the weighted number of error bits.

[0082] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, when step S11 is executed, specifically, step S11 includes steps S111-S114, for example.

[0083] Step S111: providing a new chip to be tested.

[0084] Step S112: Burn the firmware program into the chip to be tested.

[0085] Step S113: Install the chip to be tested on the test board 102, and confirm that the installation position is correct and there is no contact problem.

[0086] Step S114 , configuring a preset test temperature and a preset test voltage for the test board 102 to form an initial test environment a, and performing a power supply test on the test board 102 .

[0087] See also Figure 1 , Figure 3 to Figure 4 As shown, in one embodiment of the present invention, in step S111, the number of erasures of the chip to be tested is, for example, 0. In step S113, there are, for example, multiple test boards 102, and each of the multiple test boards 102 is connected to the power module 101 to improve the test efficiency. Through steps S111-S114, it can be confirmed that the connection between the chip to be tested and the test board 102 and the power supply of the power module 101 to the test board 102 are normal, so as to ensure the smooth execution of subsequent steps.

[0088] See also Figure 3 As shown, in one embodiment of the present invention, after the chip to be tested and the test board 102 are correctly connected, step S12 is executed. Step S12 is for the main control unit to start the read-write stress test program and perform a stress test on the chip to be tested to identify the specific locations of bad blocks and error bits in the chip to be tested.

[0089] See also Figure 3 and Figure 5As shown, in one embodiment of the present invention, after the main control unit starts the read-write stress test program, step S13 is executed. Specifically, step S13 includes steps S131-S134.

[0090] Step S131: Under the initial test environment a, count the number of single-block error bits X of each flash memory block in the chip to be tested. a , get multiple single block error bit number X a and record the value in the preset position of the chip to be tested.

[0091] Step S132: Determine the single-block error bit number X of each flash memory block. a Whether it exceeds the processing capacity of the error correction module.

[0092] Step S133: When the number of single-block error bits of the flash memory block is X a When the processing capacity of the error correction module is exceeded, the flash memory block is determined to be a bad block, the flash memory block is added to the bad block management, and the number of bad blocks of the chip under test and the total number of error bits of all flash memory blocks of the chip under test are counted.

[0093] Step S134: When the number of single-block error bits of the flash memory block is X a When the processing capacity of the error correction module is not exceeded, the stress test is repeatedly performed on the next flash memory block in the chip to be tested until all the flash memory blocks in the chip to be tested have completed the stress test.

[0094] See also Figure 3 and Figure 5 As shown, in one embodiment of the present invention, in step S131, under the initial test environment a, the single block error bit number X of each flash memory block in the chip to be tested is counted. a , get multiple single block error bit number X a The value is recorded in a preset position of the chip to be tested, wherein the preset position is, for example, a common data storage area 1144 in the storage block 114.

[0095] See also Figure 3 and Figure 5 As shown, in one embodiment of the present invention, the number of single-block error bits X of each flash memory block is counted. a Then, in step S132, the single block error bit number X of the flash memory block is determined. a Whether it exceeds the processing capacity of the error correction module 110. Specifically, determine the single block error bit number X of a flash memory block. a When the processing capacity of the error correction module 110 is exceeded, the single block error bit number X can be compared. a and the single block error bit setting value, if the single block error bit X a If the number of single-block error bits is greater than the set value, it indicates that the number of single-block error bits of the flash memory block is X. aThe processing capacity of the error correction module 110 has been exceeded, and the flash memory block cannot be successfully repaired and corrected by the error correction module 110. Otherwise, the error correction module 110 can successfully repair the flash memory block. In this embodiment, for chips of consumer-grade standards, industrial-grade standards, and automotive-grade standards, the single-block error bit setting value is different, for example, for consumer-grade standards, the single-block error bit setting value is 200-400, for industrial-grade standards, the single-block error bit setting value is 100-200, and for automotive-grade standards, the single-block error bit setting value is 0-100.

[0096] See also Figure 3 and Figure 5 As shown, in one embodiment of the present invention, when the number of single-block error bits of the flash memory block is X a When the processing capacity of the error correction module is exceeded, step S133 is executed, that is, the flash memory block is determined to be a bad block, it is added to the bad block management, and the number of bad blocks Z of the chip to be tested is counted. a , and the total number of error bits Y in all flash memory blocks of the chip under test a In this embodiment, when the number of single-block error bits of the flash memory block does not exceed the processing capacity of the error correction module 110, step S134 is executed, that is, the stress test is repeatedly performed on the next flash memory block in the chip to be tested until all the flash memory blocks in the chip to be tested have completed the stress test. The stress test procedure is the same as the read-write stress test procedure in step S12, and will not be elaborated here. Through steps S131-S134, the number of single-block error bits X in each flash memory block in the chip to be tested under the initial test environment a can be counted. a 、The total number of error bits in all flash blocks is Y a and the number of bad blocks Z a , which will serve as the basis for subsequent grading of the chips under test.

[0097] See also Figure 3 and Figure 6 As shown, in one embodiment of the present invention, the number of single-block error bits X in each flash memory block is counted. a 、The total number of error bits in all flash blocks is Y a and the number of bad blocks Z aAfter that, step S140 is executed, i.e., determining whether the chip to be tested has completed the stress test under all preset test environments. Among them, according to the preset test temperature and the preset test voltage, for example, four preset test environments are set, and the four preset test environments are, for example, the initial test environment a, the first test environment b, the second test environment c and the third test environment d. The initial test environment a, the first test environment b, the second test environment c and the third test environment d correspond to, for example, high temperature and high pressure (HTHV), high temperature and low pressure (HTLV), low temperature and high pressure (LTHV) and low temperature and low pressure (LTLV), respectively. Among them, temperature refers to the ambient temperature of the chip to be tested, and pressure refers to the main power supply voltage VCC and the I / O port power supply voltage VCCQ of the chip to be tested. In this embodiment, for consumer-grade standards, the high temperature is, for example, 55°C to 75°C, the low temperature is, for example, -30°C to -10°C, the high voltage VCC is, for example, 3.6V to 3.9V, the high voltage VCCQ is, for example, 1.2V to 1.4V, or, for example, 1.9V to 2.1V, the low voltage VCC is, for example, 2.7V to 2.9V, the low voltage VCCQ is, for example, 0.9V to 1.1V, or, for example, 1.4V to 1.6V. For industrial-grade standards, the high temperature is, for example, 75°C to 95°C, the low temperature is, for example, -50°C to -30°C, the high voltage VCC is, for example, 3.6V to 3.9V, the high voltage VCCQ is, for example, 1.2V to 1.4V, or, for example, 1.9V to 2.1V, the low voltage VCC is, for example, 2.7V to 2.9V, the low voltage VCCQ is, for example, 0.9V to 1.1V, or, for example, 1.4V to 1.6V. For automotive-grade standards, the high temperature is, for example, 140°C~160°C, the low temperature is, for example, 30°C~50°C, the high voltage VCC is, for example, 3.6V~3.9V, the high voltage VCCQ is, for example, 1.2V~1.4V, or, for example, 1.9V~2.1V, the low voltage VCC is, for example, 2.7V~2.9V, the low voltage VCCQ is, for example, 0.9V~1.1V, or, for example, 1.4V~1.6V.

[0098] See also Figure 3 and Figure 6 As shown, in one embodiment of the present invention, when the chip under test has not completed the stress test under the four preset test environments, step S14 is executed, that is, the preset test temperature and the preset test voltage are changed, and the stress test is repeatedly performed on the chip under test until the chip under test completes the stress test under the four preset test environments. Among them, the procedure of repeatedly performing the stress test on the chip under test is the same as the read-write stress test procedure in step S12, and is not further elaborated here. Through step S12, step S140 and step S14, the number of single block error bits X in each block of the chip under test under the four preset test environments (a, b, c and d) can be counted. a , X b , X c and X d, the total number of error bits in all blocks is Y a , Y b , Y c and Y d , and the number of bad blocks Z a , Z b , Z c and Z d , which is used as the basis for subsequent classification of the chips to be tested. a , Y a and Z a Corresponding to the initial test environment a, X b , Y b and Z b Corresponding to the first test environment b, X c , Y c and Z c Corresponding to the second test environment c, X d , Y d and Z d Corresponding to the third test environment d.

[0099] See also Figure 3 and Figure 6 As shown, in one embodiment of the present invention, when the chip under test completes the stress test under four preset test environments, step S15 is executed, that is, the number of bad blocks and the number of error bits of the chip under test under the four preset test environments are counted, and the weighted number of bad blocks and the weighted number of error bits are calculated according to the weights of each of the four preset test environments. Fig. 9 As shown, in one embodiment of the present invention, the single block error bit number X of 8 blocks in a chip under test under four environments of HTHV, HTLV, LTHV and LTLV is counted. a .Depend on Fig. 9 It can be seen that the number of single-block error bits X in the same block under different environments a Therefore, it is necessary to comprehensively and integratedly evaluate the chip status under different temperatures and pressures according to the weights of different test environments, so as to accurately grade the chips.

[0100] See also Figure 3 and Figure 7 As shown, in one embodiment of the present invention, when step S15 is executed, step S15 includes steps S151-S153, for example.

[0101] Step S151 : weighting a plurality of single-block error bit numbers obtained by counting in each preset test environment according to the weight of each preset test environment to obtain a weighted single-block error bit number.

[0102] Step S152: according to the weight of each preset test environment, weight the multiple total error bit numbers obtained by statistics in each preset test environment to obtain a weighted total error bit number.

[0103] Step S153: weighting the multiple bad block numbers obtained by counting in each preset test environment according to the weight of each preset test environment to obtain a weighted bad block number.

[0104] See also Figure 3 and Figure 7 As shown, in one embodiment of the present invention, in steps S151-S153, the weights of the initial test environment a, the first test environment b, the second test environment c and the third test environment d are, for example, A%, B%, C% and D%, respectively, and A%+B%+C%+D%=100%. In step S151, the single block error bit number X obtained by counting in the four preset test environments is calculated according to the weights of each of the four preset test environments. a , X b , X c and X d Weighted, get the weighted single block error bit number X. Specifically, X=X a *A%+X b *B%+X c *C%+X d *D%. Due to the different requirements of consumer-grade standards, industrial-grade standards and automotive-grade standards for temperature and pressure, the weights of chips of different standards in the same test environment are different. Taking consumer-grade standards and automotive-grade standards as examples, compared with consumer-grade standards, automotive-grade standards need to be able to withstand higher temperature environments. Therefore, compared with consumer-grade standards, automotive-grade standards have a greater weight in high-temperature test environments, that is, the sum of the weights of automotive-grade standards in the initial test environment a and the first test environment b, A%+B%, is greater than the sum of the weights of consumer-grade standards in the initial test environment a and the first test environment b, A%+B%. In this embodiment, for consumer-grade standards, A% is, for example, 0-10%, B% is, for example, 0-10%, C% is, for example, 40%-50%, and D% is, for example, 40%-50%; for industrial-grade standards, A% is, for example, 0-20%, B% is, for example, 0-20%, C% is, for example, 40%-60%, and D% is, for example, 20%-40%; for automotive-grade standards, A% is, for example, 40%-60%, B% is, for example, 20%-40%, C% is, for example, 0-20%, and D% is, for example, 0-20%.

[0105] See also Figure 3 and Figure 7As shown, in one embodiment of the present invention, in step S152, the four total error bit numbers Y obtained by statistics in the four test environments are calculated according to the weights of the four preset test environments. a , Y b , Y c and Y d Weighted, we get the weighted total number of error bits Y. Specifically, Y=Y a *A%+Y b *B%+Y c *C%+Y d *D%.

[0106] See also Figure 3 and Figure 7 As shown, in one embodiment of the present invention, in step S153, the four bad block numbers Z obtained by counting in the four test environments are calculated according to the weights of the four preset test environments. a , Z b , Z c and Z d Weighted, we get the weighted bad block number Z. Specifically, Z=Z a *A%+Z b *B%+Z c *C%+Z d *D%.

[0107] See also Figure 3 and Figure 8 As shown, in one embodiment of the present invention, after calculating the weighted single block error bit number X, the weighted total error bit number Y and the weighted bad block number Z, step S1601 is still performed, that is, judging whether the life test of the chip to be tested is completed to monitor the life status of the chip to be tested.

[0108] See also Figure 3 and Figure 8 As shown, in one embodiment of the present invention, when the life test is not completed, step S1602 is executed, and step S1602 is to wear the chip to be tested and repeatedly burn and stress test the chip to be tested. Among them, the step of repeatedly burning the chip to be tested is the same as step S112, and the degree of repeatedly stress testing the chip to be tested is the same as the read-write stress test procedure in step S12, which will not be further elaborated here.

[0109] See also Figure 3 and Figure 8As shown, in one embodiment of the present invention, in step S1602, the chip to be tested is worn to shorten the life of the chip to be tested. In this embodiment, the chip to be tested has a preset number of erasable times, and the ratio of the average number of erasures to the preset number of erasable times is defined as the life percentage. In step S1602, the chip to be tested is worn, that is, the number of erasures of the chip to be tested is increased, that is, the average number of erasures and the life percentage of the chip to be tested are increased. The life percentage can be increased to 70%-95%, for example, to 90%. By setting steps S1601-S1602, it is possible to monitor the health changes of the chip to be tested under different life cycles, give early warning of the status of the chip to be tested, and improve the overall performance and reliability of the chip to be tested.

[0110] See also Figure 3 and Figure 8 As shown, in one embodiment of the present invention, when the life test is completed, step S16 is executed, and step S16 includes, for example, step S161, and step S161 is to grade the chip to be tested according to the weighted single block error bit number X, the weighted total error bit number Y and the weighted bad block number Z. Specifically, for the preset grade standard, the weighted single block error bit number X of the chip to be tested is less than the weighted single block error bit number threshold value x, the weighted total error bit number Y of the chip to be tested is less than the weighted total error bit number threshold value y, and the weighted bad block number Z of the chip to be tested is less than the weighted bad block number threshold value z. The chip to be tested can be considered to meet the preset grade standard only if the three conditions are met at the same time: the weighted single block error bit number X of the chip to be tested is less than the weighted single block error bit number threshold value x, the weighted total error bit number Y of the chip to be tested is less than the weighted total error bit number threshold value y, and the weighted bad block number Z of the chip to be tested is less than the weighted bad block number threshold value z. However, if the weighted single block error bit number X of the chip to be tested is less than the weighted single block error bit number threshold value x, the weighted total error bit number Y of the chip to be tested is less than the weighted total error bit number threshold value y, and the weighted bad block number Z of the chip to be tested is less than the weighted bad block number threshold value z, the chip to be tested does not meet the preset grade standard as long as one of the three conditions is not met.

[0111] See also Figure 3 and Figure 8As shown, in one embodiment of the present invention, in step S161, by comparing the weighted single block error bit number X and the weighted single block error bit number threshold value x, the weighted total error bit number Y and the weighted total error bit number threshold value y, and the weighted bad block number Z and the weighted bad block number threshold value z of the chip to be tested, it is possible to determine whether the chip to be tested meets the preset grade standard, thereby accurately classifying the chip to be tested. In this embodiment, for consumer-grade standards, the weighted single block error bit number threshold value, the weighted total error bit number threshold value, and the weighted bad block number threshold value are, for example, x1, y1, and z1, respectively; for industrial-grade standards, the weighted single block error bit number threshold value, the weighted total error bit number threshold value, and the weighted bad block number threshold value are, for example, x2, y2, and z2, respectively; for automotive-grade standards, the weighted single block error bit number threshold value, the weighted total error bit number threshold value, and the weighted bad block number threshold value are, for example, x3, y3, and z3, respectively. Moreover, among the three grade standards, since the requirements of the automotive grade are the most stringent, the requirements of the industrial grade are the second, and the requirements of the consumer grade are the most extensive, therefore, x1>x2>x3, y1>y2>y3, z1>z2>z3. Among them, x1 is, for example, 200-400, x2 is, for example, 100-200, x3 is, for example, 0-100, y1 is, for example, 1000-2500, y2 is, for example, 200-1000, y3 is, for example, 0-200, z1 is, for example, 4-6, z2 is, for example, 2-4, and z3 is, for example, 0-2.

[0112] See also Figures 1 to 8 As shown, the present invention provides a test method and test system for a memory chip. According to the weights of the various test environments, the number of bad blocks and the number of error bits of the statistical chip in various test environments are weighted to obtain the weighted number of bad blocks and the weighted number of error bits. Based on this, the chips can be graded comprehensively, quickly and accurately, and the chips can be adapted to different application scenarios. Moreover, the test method provided by the present invention can monitor the health changes of the chip under different environments, pressures, life cycles, etc., so as to provide early warning of the health status of the chip and improve the performance and reliability of the chip.

[0113] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing a memory chip, characterized in that: At least the following steps are included: Install the chip to be tested on the test board, and configure the preset test temperature and preset test voltage to form an initial test environment; The main control unit starts a read-write stress test program to perform a stress test on the chip to be tested; Counting the number of bad blocks and the number of error bits of the chip under test in the initial test environment; Changing the preset test temperature and the preset test voltage, and repeatedly performing stress testing on the chip to be tested until the chip to be tested completes stress testing under all preset test environments; Counting the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weight of each of the preset test environments; as well as The chip to be tested is graded according to the weighted number of bad blocks and the weighted number of error bits.

2. The testing method according to claim 1, characterized in that: Four preset test environments are set according to the preset test temperature and the preset test voltage.

3. The testing method according to claim 1, characterized in that: Install the chip to be tested on the test board, and configure the preset test temperature and preset test voltage to form an initial test environment, including the following steps: Provide a new chip to be tested; Burning the firmware program into the chip to be tested; Install the chip to be tested on the test board and confirm that the installation position is correct and there is no contact problem; and The test board is configured with a preset test temperature and a preset test voltage to form an initial test environment, and a power supply test is performed on the test board.

4. The testing method according to claim 3, characterized in that: Counting the number of bad blocks and the number of error bits of the chip under test in the initial test environment includes the following steps: Under the initial test environment, counting the single block error bit number of each flash memory block in the chip to be tested, obtaining a plurality of the single block error bit numbers, and recording the values ​​in a preset position of the chip to be tested; Determining whether the single-block error bit number of each flash memory block exceeds the processing capability of the error correction module; When the single-block error bit number of the flash memory block exceeds the processing capacity of the error correction module, the flash memory block is determined to be a bad block, the flash memory block is added to the bad block management, and the number of bad blocks of the chip to be tested and the total number of error bits of all flash memory blocks of the chip to be tested are counted; and When the single-block error bit number of the flash memory block does not exceed the processing capacity of the error correction module, the stress test is repeatedly performed on the next flash memory block in the chip to be tested until all the flash memory blocks in the chip to be tested have completed the stress test.

5. The testing method according to claim 4, characterized in that: Before changing the preset test temperature and the preset test voltage, the following steps are also included: Determine whether the chip under test has completed all stress tests under the preset test environment; When the chip under test completes the stress test under all the preset test environments, the number of bad blocks and the number of error bits of the chip under test under all the preset test environments are counted, and the weighted number of bad blocks and the weighted number of error bits are calculated according to the weight of each of the preset test environments; and When the chip under test has not completed all stress tests under the preset test environments, the preset test temperature and the preset test voltage are changed, and the stress test is repeatedly performed on the chip under test until the chip under test completes all stress tests under the preset test environments.

6. The testing method according to claim 5, characterized in that: Counting the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and calculating the weighted number of bad blocks and the weighted number of error bits according to the weight of each of the preset test environments, includes the following steps: According to the weight of each of the preset test environments, weighting the plurality of single block error bit numbers obtained by statistics in each of the preset test environments to obtain a weighted single block error bit number; According to the weight of each of the preset test environments, weighting the plurality of total error bit numbers obtained by statistics in each of the preset test environments to obtain a weighted total error bit number; and According to the weight of each of the preset test environments, the multiple bad block numbers obtained by counting in each of the preset test environments are weighted to obtain a weighted bad block number.

7. The testing method according to claim 6, characterized in that: Before grading the chip to be tested according to the weighted bad block number and the weighted error bit number, the following steps are also included: Determining whether the life test of the chip to be tested is completed; and When the life test is not completed, the chip to be tested is worn out, and the burning and stress tests are repeatedly performed on the chip to be tested.

8. The testing method according to claim 7, characterized in that: Before grading the chip to be tested according to the weighted bad block number and the weighted error bit number, the following steps are also included: When the life test is completed, the chip to be tested is graded according to the weighted single block error bit number, the weighted total error bit number and the weighted bad block number.

9. A memory chip testing system, characterized in that: At least: At least one test board, on which the chip to be tested is communicatively connected, and is configured with a plurality of preset test environments, wherein the preset test voltages and the preset test temperatures are different in the plurality of preset test environments; A main control module is communicatively connected to the chip to be tested and is configured with a read-write stress test program to perform a stress test on the chip to be tested; A bad block monitoring module, which counts the number of bad blocks and the number of error bits of the chip under test in all the preset test environments, and calculates the weighted number of bad blocks and the weighted number of error bits according to the weights of all the preset test environments, and classifies the chip under test according to the weighted number of bad blocks and the weighted number of error bits; as well as A power supply module supplies power to the test board, the main control module and the bad block monitoring module.

10. The test system according to claim 9, characterized in that: The test system further comprises a temperature sensing module and a voltage monitoring module, wherein the temperature sensing module and the voltage monitoring module are respectively connected to the main control module.

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