High time precision power glitch fault injection method and device for cryptographic chips

Abstract

The invention relates to the technical field of integrated circuit security and power glitch fault injection, and discloses a high-time-precision power glitch fault injection method and device for a cryptographic chip. The method comprises setting parameters of a power glitch fault injection device, initializing and configuring a cryptographic chip to be tested through a computer, and determining a power glitch fault injection time according to a power glitch voltage and a target instruction; setting the power glitch fault injection time through a computer, controlling a high-voltage pulse generator to generate a power glitch fault, and injecting the power glitch fault into the cryptographic chip to be tested, and judging and recording valid error ciphertexts; obtaining valid error ciphertexts generated by the cryptographic chip to be tested when different plaintexts are input through multiple power glitch fault injections; analyzing the valid error ciphertext according to differential faults, and cracking key information of the cryptographic chip to be tested, so that the injection time point can be more accurately controlled when the power glitch fault is injected into the cryptographic chip.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuit security and power glitch fault injection, and in particular to a high-time-precision power glitch fault injection method and device for a cryptographic chip. Background Art

[0002] Attacks on cryptographic chips are mainly divided into two categories: side channel attacks and fault injection attacks. Existing literature has proposed many different fault injection techniques, such as power supply fault injection, laser injection, clock glitches, and electromagnetic pulses.

[0003] Power supply fault injection is a method of fault injection by adjusting the power supply of the integrated circuit during operation. Early tampering with the power supply voltage injected faults into the target device by underfeeding. A power supply voltage lower than the standard voltage increases the delay of the combinational path. When the voltage is reduced to make the path delay greater than the clock cycle, it will cause a setup time violation, resulting in errors such as the data of the hardware circuit being modified or the instructions of the microcontroller being skipped. However, since all clock cycles are exposed to low voltage, this technology cannot control the timing of fault injection. The resulting improvement is power glitch fault injection, which inserts timely spikes in the power line or injects faults by temporarily powering off. Since the time of inserting the spike needs to be controlled, power glitch fault injection is time-sensitive. Power glitch fault injection does not leave traces of tampering, and is similar to clock glitch fault injection, and is non-invasive.

[0004] After implementing fault injection, attackers can use the injected faults to extract key information of the circuit through differential fault analysis (DFA). DFA gradually derives the key used by the encryption algorithm by comparing the correct ciphertext with the incorrect ciphertext (i.e., the ciphertext obtained from the incorrect encryption). The accuracy of DFA is related to the accuracy of fault injection. Fault injection is time-sensitive. If the fault is not induced at the appropriate time in the algorithm, or affects the spatial location of the error, the entire attack process fails. Therefore, time accuracy is a key factor in conducting any fault attack.

[0005] In the practical application of power glitch fault injection, existing research has great limitations in the time accuracy of injection when using a power glitch-based fault injection method. The power glitch-based fault injection method inserts a peak value into the clock power supply, destroys the timing constraints of the circuit, and causes the chip to skip an instruction, thereby achieving the purpose of generating a fault. Considering the inherent properties of the power glitch fault injection experimental device and the electrical signal, when inserting a peak value into the clock power supply, the signal rise time must be experienced. After extensive research, existing research has only considered the duration of the power glitch, and has not yet considered the impact of the signal rise time on the power glitch fault. There is currently no effective method to address the problem of power glitch fault injection attack failures caused by insufficient time accuracy.

[0006] Therefore, there is an urgent need for a high-time-precision power glitch fault injection method and device for cryptographic chips, which can more accurately control the injection time point when injecting power glitch faults into cryptographic chips, improve the analysis efficiency and effect of differential fault analysis, and increase the success rate of effective fault injection. Summary of the invention

[0007] In order to solve the above technical problems, the present invention provides a high-time-precision power glitch fault injection method and device for a cryptographic chip, which can more accurately control the injection time point when injecting power glitch faults into the cryptographic chip, improve the analysis efficiency and effect of differential fault analysis, and improve the success rate of effective fault injection.

[0008] The present invention provides a method and device for high time precision power glitch fault injection for a cryptographic chip, comprising the following steps:

[0009] The power glitch fault injection device includes: a computer, a high voltage pulse generator, and a circuit board;

[0010] Further, the computer: is connected to the high-voltage pulse generator, the circuit board and the password chip to be tested through a serial port cable, and is used to control the high-voltage pulse generator input power glitch fault, control the circuit board power supply voltage, and control the initialization of the password chip to be tested;

[0011] High-voltage pulse generator: connected to the computer, connected to the attack chip through a dedicated high-voltage cable, used to generate power glitch faults, and then generate power glitch faults in the password chip to be tested;

[0012] Circuit board: connected to the computer, connected to the high-voltage pulse generator via a dedicated high-voltage cable, used to provide the power supply voltage required by the password chip to be tested.

[0013] Furthermore, the power glitch fault injection device also includes:

[0014] Oscilloscope: connected to the computer and connected to the cryptographic chip to be tested through a probe, used to detect the electromagnetic signal of the cryptographic chip to be tested, monitor the fault injection time point, and detect the waveform fluctuation of the cryptographic chip to be tested, so as to preliminarily determine whether the fault injection is successfully completed.

[0015] Set the parameters of the power glitch fault injection device, the parameters specifically include:

[0016] Power supply voltage: according to the voltage required for the normal operation of the password chip circuit to be tested, the power supply voltage is set through the computer control circuit board;

[0017] Power supply glitch voltage: According to the power supply voltage, the glitch voltage is set by controlling the high voltage pulse generator through the computer;

[0018] Power supply glitch length: According to the power supply voltage, the power supply glitch length is set by controlling the high voltage pulse generator through a computer.

[0019] Initializing and configuring the password chip to be tested through a computer includes: powering on and inputting plain text.

[0020] Furthermore, the correct ciphertext of the cryptographic chip to be tested is obtained.

[0021] Determining a fault injection time of a power glitch according to the power glitch voltage and a target instruction;

[0022] Further, determining the rise time of the power supply glitch fault according to the power supply glitch voltage;

[0023] According to the target instruction, determine the peak moment of the power glitch fault;

[0024] The difference between the peak time of the power glitch fault and the rise time of the power glitch fault is used as the fault injection time of the single power glitch.

[0025] The fault injection time of the power glitch is set by a computer, and the high-voltage pulse generator is controlled to generate a power glitch fault.

[0026] The power glitch fault is injected into the cryptographic chip to be tested to determine whether the injection is valid. If it is valid, the error ciphertext generated by the injection is recorded as a valid error ciphertext; otherwise, it is not recorded.

[0027] Furthermore, the power glitch fault is injected into the cryptographic chip to be tested to determine whether the cryptographic chip to be tested outputs an erroneous ciphertext that skips the target instruction. If the erroneous ciphertext that skips the target instruction is output, the injection is determined to be a valid injection, otherwise, it is an invalid injection.

[0028] The power glitch fault injection includes: single power glitch fault injection and continuous power glitch fault injection.

[0029] Further, when continuous power glitch faults are injected, the injection time of the power glitch faults is determined according to the power glitch voltage and the target instruction, and further includes:

[0030] Determining the falling time of the power supply glitch fault according to the power supply glitch voltage;

[0031] The rise time of the power glitch fault, the fall time of the power glitch fault and the preset signal delay time are summed up to serve as a continuous fault injection cycle.

[0032] After the power glitch fault injection device completes a fault injection, it returns to the step of setting the parameters of the power glitch fault injection device and performs power glitch fault injection again until the preset fault injection times are reached to obtain the valid error ciphertext generated by the password chip to be tested when different plaintexts are input.

[0033] Analyze the valid error ciphertext according to the differential fault, and crack the key information of the cryptographic chip to be tested;

[0034] Further, a difference set is calculated according to the correct ciphertext output by the attacking ciphertext chip under a certain plaintext and the valid error ciphertext output by the ciphertext chip to be tested under the plaintext;

[0035] Repeat the above steps to obtain all difference sets of the attacking cryptographic chip under different plaintexts;

[0036] Compute the intersection based on all differences;

[0037] The key information of the cryptographic chip to be tested is determined according to the intersection.

[0038] The embodiments of the present invention have the following technical effects:

[0039] The present invention adjusts the injection time of the power glitch fault by considering the rise time of the power glitch fault, controls the injection time of the power glitch fault more accurately, reduces the limitation of the time accuracy of the power glitch fault injection, and improves the success rate of the power glitch fault injection. At the same time, according to the influence of the power glitch injection intensity on the glitch rising slope, the rise time is adjusted in time to ensure the accuracy of the power glitch fault injection time. When injecting continuous power glitch faults, according to the rise time and fall time of the power glitch fault, the injection cycle is adjusted to ensure the accuracy of the continuous power glitch fault injection time.

[0040] Multiple power glitch fault injections are performed on the cryptographic chip to be tested. The fault injection that successfully skips the target instruction is regarded as a valid injection. The erroneous ciphertext output by the same key under different input plaintexts is collected, and the key information of the cryptographic chip is cracked using differential fault analysis. This technology helps cryptographic chip designers to improve protection measures in a timely manner against power glitch fault injection and enhance the security of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0042] Figure 1 It is a flow chart of a method for high time precision power glitch fault injection for a cryptographic chip provided by an embodiment of the present invention;

[0043] Figure 2 It is a schematic diagram of a high time precision power glitch fault injection device for a cryptographic chip provided by an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of a power glitch fault injection time provided by an embodiment of the present invention;

[0045] Figure 4 is a schematic diagram of power glitch fault injection time with different power glitch fault injection strengths provided by an embodiment of the present invention;

[0046] Figure 5 It is a schematic diagram of a continuous fault injection cycle of continuous power glitch fault injection provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present invention.

[0048] In traditional power glitch fault injection methods, usually only the duration of the power glitch is considered, and the impact of the signal rise time on the power glitch fault has not been considered. Its effectiveness is often limited by the time accuracy.

[0049] In order to overcome this problem, the present invention takes into account the rise time of the power glitch and realizes the precise control of the power glitch fault injection time. Through this high-precision time adjustment, the present invention not only optimizes the more accurate control of the injection time point when injecting the power glitch fault into the cryptographic chip, but also significantly improves the accuracy and success rate of the fault injection. This adjustment strategy of precisely controlling the fault injection time in combination with the rise time of the power glitch enables the fault injection technology to act on the target cryptographic chip more finely and efficiently, and provides a more effective technical means for the security assessment and protection measures of the cryptographic chip. Through the method of the present invention, the electromagnetic fault injection into the cryptographic chip can be achieved with higher accuracy within a smaller number of tests, thereby greatly improving the efficiency and quality of security testing.

[0050] Figure 2 Schematic diagram of a power glitch fault injection device provided by an embodiment of the present invention. Figure 2 ,The power glitch fault injection device specifically includes: a computer, a high voltage pulse generator, a circuit board, and an oscilloscope;

[0051] Further, the computer: is connected to the high-voltage pulse generator, the circuit board and the password chip to be tested through a serial port cable, and is used to control the high-voltage pulse generator input power glitch fault, control the circuit board power supply voltage, and control the initialization of the password chip to be tested;

[0052] High-voltage pulse generator: connected to the computer, connected to the attack chip through a dedicated high-voltage cable, used to generate power glitch faults, and then generate power glitch faults in the password chip to be tested;

[0053] Circuit board: connected to the computer, connected to the high-voltage pulse generator via a dedicated high-voltage cable, used to provide the power supply voltage required by the password chip to be tested.

[0054] Oscilloscope: connected to the computer and connected to the cryptographic chip to be tested through a probe, used to detect the electromagnetic signal of the cryptographic chip to be tested, monitor the fault injection time point, and detect the waveform fluctuation of the cryptographic chip to be tested, so as to preliminarily determine whether the fault injection is successfully completed.

[0055] Specifically, the computer is connected to the high-voltage pulse generator, the circuit board and the password chip to be tested through a serial cable. The role of the computer is to control the entire experimental process, control the high-voltage pulse generator to generate a preset power glitch fault mode, control the power supply voltage of the circuit board, ensure that the password chip to be tested works within the correct voltage range, and control the initialization process of the password chip to be tested to ensure that the chip is in the expected state at the beginning of the experiment; the high-voltage pulse generator is connected to the password chip to be attacked through a dedicated high-voltage cable. The high-voltage pulse generator is responsible for generating power glitch fault signals, which will be transmitted to the power pins of the password chip to be tested through the connected cable to simulate the unstable power supply under electromagnetic interference; the circuit board is connected to the computer and the high-voltage pulse generator through a dedicated high-voltage cable. The circuit board provides the stable power supply voltage required by the password chip to be tested, ensuring that the circuit board can effectively transmit the power glitch generated by the high-voltage pulse generator to the password chip to be tested, while protecting other circuits from unnecessary interference or damage; the oscilloscope is connected to the computer and connected to the password chip to be tested through a probe. The oscilloscope is used to monitor the response and electromagnetic signals of the cryptographic chip to be tested in the experiment, detect the time point during the fault injection process, ensure that the fault is injected at the correct time point, analyze the waveform fluctuations of the cryptographic chip to be tested, and preliminarily determine whether the fault injection has been successfully completed.

[0056] Furthermore, the circuit board needs to be disconnected from the power supply and the capacitors on the circuit board need to be removed. Specifically, the circuit board needs to be powered off so that the power glitch fault injection device can control the power supply of the cryptographic chip to be tested; all capacitors on the circuit board used to stabilize the signal are removed to reduce the total capacitance value in the core power domain, thereby reducing the energy storage capacity of the power supply system and better completing the injection of the power glitch fault.

[0057] Figure 1 Flowchart of a method for injecting power glitch faults with high time accuracy into a cryptographic chip provided by an embodiment of the present invention. Figure 1 , including:

[0058] Step S1: setting parameters of a power glitch fault injection device, wherein the parameters specifically include:

[0059] Power supply voltage: according to the voltage required for the normal operation of the password chip circuit to be tested, the power supply voltage is set through the computer control circuit board;

[0060] Specifically, determine the power supply voltage required for the normal operation of the password chip to be tested, and enter the corresponding instructions through the communication interface between the computer and the circuit board to set the power supply voltage output by the circuit board to ensure that it meets the working requirements of the password chip.

[0061] Power supply glitch voltage: According to the power supply voltage, the glitch voltage is set by controlling the high voltage pulse generator through the computer;

[0062] Specifically, according to the required fault injection intensity, a high voltage pulse generator is controlled by a computer to set the voltage value when a power glitch is generated. This voltage value should be lower than the power supply voltage to simulate a power supply fault condition.

[0063] Power glitch length: According to the power supply voltage, the power glitch length is set by controlling the high voltage pulse generator through the computer;

[0064] Specifically, the length of the power glitch refers to the duration after the glitch occurs. The high-voltage pulse generator is controlled by a computer to set the duration of the power glitch, which is further adjusted according to the power supply voltage.

[0065] Step S2: initializing and configuring the cryptographic chip to be tested through a computer, including: powering on and inputting plain text.

[0066] Furthermore, the correct ciphertext of the cryptographic chip to be tested is obtained, that is, the ciphertext output by the cryptographic chip to be tested in the absence of a fault attack.

[0067] Step S3, determining a fault injection time of a power glitch according to the power glitch voltage and the target instruction;

[0068] Further, determining the rise time of the power supply glitch fault according to the power supply glitch voltage;

[0069] According to the target instruction, determine the peak moment of the power glitch fault;

[0070] The difference between the peak time of the power glitch fault and the rise time of the power glitch fault is used as the fault injection time of the single power glitch.

[0071] Specifically, the conventional fault injection method sets the peak moment t1 of the power glitch fault as the power glitch fault injection time, but the high time precision power glitch fault injection method for the cryptographic chip provided by the present invention takes into account the rise time of the power glitch on the power line. , accurately control the power glitch fault injection time. Figure 3 Schematic diagram of power glitch fault injection time provided by an embodiment of the present invention, such as Figure 3 The peak moment t1 of the power glitch fault is obtained according to the power supply voltage, and the rise time of the power glitch is , then the power glitch fault injection time is the difference between the peak moment of the power glitch fault and the rise time of the power glitch fault, that is: .

[0072] Furthermore, Figure 4 is a schematic diagram of power glitch fault injection time with different power glitch fault injection strengths provided by an embodiment of the present invention, such as Figure 4As shown in FIG. 1 , for different power glitch fault injection intensities, the peak time of the power glitch fault, the slope of the power glitch fault rise, and the rise time of the power glitch fault will all change. It is necessary to adjust the peak value of the power glitch fault according to the rise time of the power glitch fault reaching the peak value of the power glitch fault. Real-time adjustment , and then adjust the power glitch fault injection time to .

[0073] This step is crucial for accurately simulating the impact of power glitch faults on cryptographic chips. By accurately determining the power glitch fault injection time, the precise impact of actual power glitch faults on the timing of cryptographic chips can be simulated; by injecting power glitch faults into specific target instructions, the behavior of cryptographic chips under specific operations can be studied, providing a basis for analyzing and improving specific weaknesses of the chip; by controlling the rise time and peak moment of the power glitch fault, power glitch faults of different severity can be simulated, and the sensitivity of the cryptographic chip to different fault conditions can be evaluated.

[0074] Step S4, setting the fault injection time of the power glitch through a computer, and controlling the high-voltage pulse generator to generate a power glitch fault.

[0075] Specifically, a precise power glitch fault injection time is inputted by computer software, and the fault injection is based on the previously determined power glitch rise time and peak moment.

[0076] Step S5, injecting the power glitch fault into the cryptographic chip to be tested, and determining whether the injection is valid. If it is valid, recording the error ciphertext generated by the injection as a valid error ciphertext; otherwise, not recording.

[0077] Specifically, the power glitch fault is injected into the cryptographic chip to be tested, and it is determined whether the cryptographic chip to be tested outputs an erroneous ciphertext that skips the target instruction. If the erroneous ciphertext that skips the target instruction is output, then the injection is determined to be a valid injection, otherwise, it is an invalid injection.

[0078] Furthermore, the principle of power glitch fault injection causing the target instruction to be skipped is that when the power line in a digital circuit suffers a glitch fault of instantaneous voltage reduction, the power supply voltage may drop to a voltage level lower than the voltage level required for the normal operation of the circuit; this reduction in power supply voltage will extend the propagation delay of the signal in the circuit, especially on the combinational logic path; if the delay caused by the power glitch increases to a critical level, so that the signal cannot reach a stable state within the setup time of the clock cycle, a setup time violation will occur; at this time, the register in the circuit may not be able to capture the correct input signal at the clock sampling edge, resulting in its output failing to update correctly, so that the target instruction expected to be executed within the clock cycle is ignored or skipped; since the logical operation of the digital circuit depends on precise clock synchronization, any timing violation may cause operation errors or abnormal logic states, which not only affects the normal function of the circuit, but may also expose security vulnerabilities; therefore, power glitch fault injection is an effective testing method to evaluate the circuit's sensitivity to power supply fluctuations and its ability to resist potential attacks.

[0079] The power glitch fault injection includes: single power glitch fault injection and continuous power glitch fault injection.

[0080] Furthermore, when continuous power glitch fault injection occurs, after step S4, the method further includes: determining the injection time of the power glitch fault according to the power glitch voltage and the target instruction;

[0081] Specifically, according to the power glitch voltage, determining the falling time of the power glitch fault;

[0082] The rise time of the power glitch fault, the fall time of the power glitch fault and the preset signal delay time are summed up to serve as a continuous fault injection cycle.

[0083] Figure 5 is a schematic diagram of a continuous fault injection cycle of continuous power glitch fault injection provided by an embodiment of the present invention, such as Figure 5 As shown in FIG. 1 , continuous power glitch fault injection requires setting a reasonable continuous fault injection period for power glitch fault injection. Traditional fault injection methods usually set the continuous fault injection period to the signal delay time t when performing continuous fault injection. p The high time precision power glitch fault injection method for cryptographic chips provided by the present invention takes into account the rise time of the power glitch fault. , and the fall time of the power glitch fault , the continuous fault injection cycle is adjusted to , making the fault injection more precise.

[0084] Step S6: After the power glitch fault injection device completes one injection, it returns to step S1 and executes it again until the preset fault injection times are reached to obtain the valid error ciphertext generated by the cryptographic chip to be tested when different plaintexts are input.

[0085] Step S7, analyzing the valid error ciphertext according to the differential fault, and cracking the key information of the cryptographic chip to be tested;

[0086] Further, a difference set is calculated according to the correct ciphertext output by the attacking ciphertext chip under a certain plaintext and the valid error ciphertext output by the ciphertext chip to be tested under the plaintext;

[0087] Repeat the above steps to obtain all difference sets of the attacking cryptographic chip under different plaintexts;

[0088] Compute the intersection based on all differences;

[0089] The key information of the cryptographic chip to be tested is determined according to the intersection.

[0090] Furthermore, the effective fault injection success rate is defined as: the proportion of effective fault injection times that successfully cause the cryptographic chip to produce exploitable errors among all the attempted fault injections, which can be used as an indicator to measure the effectiveness of the fault injection method; it can be expressed as:

[0091] ,

[0092] Where n is the number of valid fault injections, that is, the number of times the fault injection caused the cryptographic chip to output valid error ciphertext; N is the total number of fault injections, that is, the total number of attempts to inject faults in the test; is the effective fault injection success rate.

[0093] The higher the value, the more effective the high time precision power glitch fault injection method for cryptographic chips is. Combined with the effect of differential fault analysis and the success rate of effective fault injection, the high time precision power glitch fault injection method for cryptographic chips can be evaluated.

[0094] The present invention aims at the power glitch fault injection attack of the cryptographic chip, and proposes a high time precision power glitch fault injection method for the cryptographic chip. Considering that the power glitch fault has a rise time and cannot reach the peak value immediately, and the cryptographic chip to be tested will be attacked only when the power glitch fault reaches the peak value, and the power glitch fault injection intensity is different, the rise slope and rise time of the power glitch fault are also different. Therefore, the present invention adjusts the power glitch fault injection time according to the peak time and rise time of the power glitch fault, controls the injection time point more accurately, improves the accuracy of the control injection time, improves the analysis efficiency and effect of differential fault analysis, and improves the success rate of effective fault injection; in addition, when performing continuous fault injection, the present invention also considers the rise time and fall time of the power glitch fault, and jointly adjusts the fault injection cycle according to the rise time, fall time and signal delay time of the power glitch fault, further improves the accuracy of the control injection time, improves the analysis efficiency and effect of differential fault analysis, improves the success rate of effective fault injection, and helps the cryptographic chip designer to timely improve the protection measures for the power glitch fault injection and enhance the security of the chip.

[0095] It should be noted that the terms used in the present invention are only for describing specific embodiments, rather than limiting the scope of the present application. As shown in the present specification, unless the context clearly indicates an exception, the words "one", "a", "a kind of" and / or "the" do not specifically refer to the singular, but may also include the plural. The terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method or device. In the absence of more restrictions, the elements defined by the sentence "include one..." do not exclude the presence of other identical elements in the process, method or device including the elements.

[0096] It should also be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", etc. should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a connection between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A high-time-precision power glitch fault injection method for a cryptographic chip, which is used for security testing of the cryptographic chip, is implemented based on a power glitch fault injection device, which includes: Computer, high voltage pulse generator, circuit board, characterized in that it comprises the following steps: Set the parameters of the power glitch fault injection device, the parameters specifically include: Power supply voltage: according to the voltage required for the normal operation of the password chip circuit to be tested, the power supply voltage is set through the computer control circuit board; Power supply glitch voltage: According to the power supply voltage, the glitch voltage is set by controlling the high voltage pulse generator through the computer; Power glitch length: According to the power supply voltage, the power glitch length is set by controlling the high voltage pulse generator through the computer; Initializing and configuring the password chip to be tested through a computer, including: powering on and inputting plain text; Determining the fault injection time of the power glitch according to the power glitch voltage and the target instruction, specifically including: determining the rise time of the power glitch fault according to the power glitch voltage; determining the peak moment of the power glitch fault according to the target instruction; using the difference between the peak moment of the power glitch fault and the rise time of the power glitch fault as the fault injection time of a single power glitch; Setting the fault injection time of the power glitch by a computer and controlling the high voltage pulse generator to generate a power glitch fault; Inject the power glitch fault into the cryptographic chip to be tested, and determine whether the injection is valid. If it is valid, record the error ciphertext generated by the injection as a valid error ciphertext; otherwise, do not record it; The power glitch fault injection includes: single power glitch fault injection and continuous power glitch fault injection; After the power glitch fault injection device completes a fault injection, it returns to the step of setting the parameters of the power glitch fault injection device, and performs power glitch fault injection again until a preset number of fault injections is reached, and obtains valid error ciphertexts generated by the cryptographic chip to be tested when different plaintexts are input; The valid error ciphertext is analyzed according to the differential fault, the key information of the cryptographic chip to be tested is cracked, and the security test of the cryptographic chip is completed.

2. The high time precision power glitch fault injection method for a cryptographic chip according to claim 1 is characterized in that: When continuous power glitch faults are injected, the injection time of the power glitch faults is determined according to the power glitch voltage and the target instruction, and further includes: Determining the falling time of the power supply glitch fault according to the power supply glitch voltage; The rise time of the power glitch fault, the fall time of the power glitch fault and the preset signal delay time are summed up to serve as a continuous fault injection cycle.

3. The high time precision power glitch fault injection method for a cryptographic chip according to claim 1, characterized in that: After the password chip to be tested is initialized and configured by a computer, the method further includes: Get the correct ciphertext of the cryptographic chip to be tested.

4. The high time precision power glitch fault injection method for a cryptographic chip according to claim 3 is characterized in that: The step of injecting the power glitch fault into the cryptographic chip to be tested and determining whether the injection is a valid injection specifically includes: The power glitch fault is injected into the cryptographic chip to be tested, and it is determined whether the cryptographic chip to be tested outputs an erroneous ciphertext that skips the target instruction. If the erroneous ciphertext that skips the target instruction is output, the injection is determined to be a valid injection, otherwise, it is an invalid injection.

5. The high time precision power glitch fault injection method for a cryptographic chip according to claim 4 is characterized in that: Analyzing the valid error ciphertext according to the differential fault and cracking the key information of the cryptographic chip to be tested specifically includes: Calculate a difference set according to the correct ciphertext output by the test cipher chip under a certain plaintext and the valid error ciphertext output by the cipher chip to be tested under the plaintext; Repeat the above steps to obtain all difference sets of the test cryptographic chip under different plaintexts; Compute the intersection based on all differences; The key information of the cryptographic chip to be tested is determined according to the intersection.

6. A power glitch fault injection device, used to implement the high time precision power glitch fault injection method for a cryptographic chip as described in any one of claims 1 to 5, characterized in that: include: Computer: connected to the high-voltage pulse generator, circuit board and password chip to be tested through a serial cable, used to control the high-voltage pulse generator input power glitch fault, control the circuit board power supply voltage, and control the initialization of the password chip to be tested; High-voltage pulse generator: connected to the computer, connected to the chip to be tested through a dedicated high-voltage cable, used to generate power glitch faults, and then generate power glitch faults in the password chip to be tested; Circuit board: connected to the computer, connected to the high-voltage pulse generator via a dedicated high-voltage cable, used to provide the power supply voltage required by the password chip to be tested.

7. The power glitch fault injection device according to claim 6, characterized in that: The power glitch fault injection device further includes: Oscilloscope: connected to the computer and connected to the cryptographic chip to be tested through a probe, used to detect the electromagnetic signal of the cryptographic chip to be tested, monitor the fault injection time point, and detect the waveform fluctuation of the cryptographic chip to be tested, so as to preliminarily determine whether the fault injection is successfully completed.

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