Array substrate, manufacturing method and display panel

Abstract

The present application belongs to the technical field of display panels, and provides an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises a substrate, a common electrode line, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a common electrode layer, a fourth insulating layer and a pixel electrode layer which are stacked in sequence; the first metal layer is formed with a scanning line, and at least part of the common electrode line is stacked with at least part of the scanning line; the common electrode layer is formed with a common electrode and a first connecting portion connected to the common electrode, and the first connecting portion is electrically connected to the common electrode line. The array substrate provided by the embodiment of the present application has a large aperture ratio and a flat surface.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and in application relates to an array substrate, a manufacturing method and a display panel. Background Art

[0002] Fringe Field Switching (FFS) technology is a current liquid crystal display technology and is the mainstream liquid crystal display technology. FFS liquid crystal panels have the advantages of fast response time and wide viewing angle.

[0003] However, for FFS liquid crystal panels with high PPI (pixels per inch, pixel density), common electrode lines are usually added, which reduces the opening area of ​​the pixels, reduces the aperture ratio and transmittance. In addition, the provision of common electrode lines makes the array substrate uneven, causing the spacer columns to slide and resulting in defects such as spacer column debris and bright spots. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an array substrate, a manufacturing method and a display panel to improve the aperture ratio of the array substrate and improve the flatness of the array substrate.

[0005] To achieve the above purpose, the technical solution adopted in this application is:

[0006] In a first aspect, the present application provides an array substrate, comprising a substrate, a common electrode line, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a common electrode layer, a fourth insulating layer and a pixel electrode layer stacked in sequence; the first metal layer is formed with a scanning line, and at least part of the common electrode line is stacked with at least part of the scanning line; the common electrode layer is formed with a common electrode and a first connecting portion connected to the common electrode, and the first connecting portion is electrically connected to the common electrode line.

[0007] The array substrate provided by the present application has the following beneficial effects: compared with the prior art, on the one hand, the array substrate provided by the present application reduces the wiring space occupied by the common electrode line by stacking the scanning line and the common electrode line in the thickness direction of the array substrate, and the common electrode is electrically connected to the common electrode line through the first connecting portion, so that the array substrate provided by the present application has the advantage of a large pixel aperture ratio; on the other hand, the processes of the common electrode line, the first metal layer and the second metal layer of the array substrate provided by the present application are all before the third insulating layer and the fourth insulating layer, thereby reducing the influence of the common electrode line, the first metal layer and the second metal layer on the surface flatness of the array substrate, further making the array substrate provided by the present application have the advantage of a flat surface, improving the flatness of the array substrate, and solving the problem of defects caused by sliding of the spacer column due to the uneven surface of the array substrate.

[0008] In addition, the array substrate provided in the present application is provided with the first connecting portion between the common electrode line and the common electrode, and the first connecting portion is located between the pixel electrode and the scanning line in the plane direction in which the array substrate extends. Compared with the array substrate in the related art, the array substrate provided in the present application has a higher flatness in the area between the scanning line and the pixel electrode, so that the array substrate provided in the present application has the advantage of a flat surface.

[0009] In one embodiment, the first connecting portion is overlapped with a portion of the common electrode line;

[0010] The second metal layer is formed with a data line and a second connection portion, the first insulating layer and the second insulating layer are provided with a first via hole, and the common electrode line and the second connection portion are connected through the first via hole;

[0011] The pixel electrode layer is formed with pixel electrodes and a third connecting portion arranged at intervals, a second via hole is provided in the fourth insulating layer, and the first connecting portion and the third connecting portion are connected through the second via hole;

[0012] A third via hole is provided in the third insulating layer and the fourth insulating layer, and the second connecting portion and the third connecting portion are connected through the third via hole.

[0013] In one embodiment, the common electrode line is provided with a protruding portion, and the second connecting portion is arranged to overlap with the protruding portion.

[0014] In one embodiment, the pixel electrode layer further forms a fourth connection portion connected to the pixel electrode, and the second metal layer further forms a source electrode, a drain electrode and a fifth connection portion, and the fifth connection portion is connected to the drain electrode;

[0015] A fourth via hole is provided in the second insulating layer, the third insulating layer and the fourth insulating layer, and the fourth connecting portion and the fifth connecting portion are connected through the fourth via hole.

[0016] In one embodiment, the protruding portion and the fifth connecting portion are both located on the same side of the data line or the common electrode line.

[0017] In one embodiment, the third insulating layer comprises a self-leveling insulating layer.

[0018] In a second aspect, the present application provides a display panel, comprising the array substrate described in any one of the above embodiments.

[0019] The beneficial effects of the display panel provided by the present application are as follows: compared with the prior art, on the one hand, the array substrate provided by the present application has the advantage of a high aperture ratio, thereby making the display panel provided by the present application have the advantage of high brightness; on the other hand, the array substrate provided by the present application has the advantage of a flat surface, thereby preventing the display panel provided by the present application from generating debris on the PS (photo-spacer) side after the array substrate and the color film substrate are aligned, thereby making the display panel provided by the present application have the advantage of a low failure rate.

[0020] In a third aspect, the present application provides a method for manufacturing an array substrate, comprising:

[0021] Common electrode lines, a first insulating layer and a first metal layer are sequentially formed on one surface of a substrate, wherein the first metal layer includes scan lines, and at least part of the scan lines and part of the common electrode lines are stacked;

[0022] A second insulating layer, a second metal layer, a third insulating layer, a common electrode layer, a fourth insulating layer and a pixel electrode layer are sequentially formed on a side of the first metal layer away from the first insulating layer, the common electrode layer is formed with a common electrode and a first connecting portion connected to the common electrode, and the first connecting portion is electrically connected to the common electrode line.

[0023] The beneficial effect of the array substrate manufacturing method provided by the present application is that: compared with the prior art, the array substrate manufacturing method of the present application stacks the scan lines and the common electrode lines in the thickness direction of the array substrate, reducing the routing space of the scan lines and the common electrode lines, so that the array substrate manufactured by the array substrate manufacturing method has the advantage of a large pixel aperture ratio; on the other hand, in the array substrate manufacturing method provided by the present application, the process of the common electrode lines, the first metal layer and the second metal layer is before the third insulating layer and the fourth insulating layer, thereby reducing the influence of the common electrode lines, the first metal layer and the second metal layer on the surface flatness of the array substrate, further making the array substrate provided by the present application have the advantage of a flat surface.

[0024] In addition, the array substrate manufacturing method provided in the present application manufactures the first connecting portion between the common electrode line and the common electrode, that is, the first connecting portion is also located between the pixel electrode and the scanning line. Compared with the array substrate in the related art, the array substrate manufactured by the array substrate manufacturing method provided in the present application has a higher flatness in the area between the scanning line and the pixel electrode, so that the array substrate manufactured by the array substrate manufacturing method has the advantage of a flat surface.

[0025] In one embodiment, the array substrate manufacturing method further includes:

[0026] In the process of manufacturing the second insulating layer, a first via hole is manufactured in the first insulating layer and the second insulating layer;

[0027] In the process of manufacturing the second metal layer, the second metal layer includes a data line and a second connecting portion, and the second connecting portion is connected to the common electrode layer through the first via hole;

[0028] In the process of manufacturing the common electrode layer and the fourth insulating layer, a second via hole is manufactured in the fourth insulating layer, and a third via hole is manufactured in the third insulating layer and the fourth insulating layer;

[0029] Wherein, the common electrode layer includes a common electrode and a first connecting portion;

[0030] In the process of manufacturing the pixel electrode layer, the pixel electrode layer includes a pixel electrode and a third connection portion, the third connection portion is connected to the first connection portion through the second via hole, and the third connection portion is connected to the second connection portion through the third via hole.

[0031] In one embodiment, the array substrate manufacturing method further includes:

[0032] In the process of manufacturing the pixel electrode layer, a fourth via hole is manufactured in the third insulating layer and the fourth insulating layer;

[0033] Wherein, the second metal layer further includes a source electrode, a drain electrode and a fifth connecting portion, and the fifth connecting portion is connected to the drain electrode;

[0034] The pixel electrode layer further includes a fourth connection portion, and the fourth connection portion is connected to the fifth connection portion through the fourth via hole. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0036] Figure 1 A schematic diagram of the structure of an array substrate provided in an embodiment of the present application;

[0037] Figure 2 for Figure 1 A partial cross-sectional view at AA in the middle;

[0038] Figure 3 for Figure 1 A partial cross-sectional view of the middle BB;

[0039] Figure 4 for Figure 1 A partial cross-sectional view of the CC in the middle;

[0040] Among them, the reference numerals in the figure are:

[0041] 100. Array substrate;

[0042] 000, substrate;

[0043] 10. common electrode line; 11. protrusion;

[0044] 20. a first insulating layer;

[0045] 31. Scan line;

[0046] 40. A second insulating layer;

[0047] 50. second metal layer; 51. second connection portion; 52. fifth connection portion; 53. drain electrode; 54. source electrode; 55. data line;

[0048] 60. third insulating layer; 61. self-leveling insulating layer; 62. fifth insulating layer;

[0049] 70. common electrode layer; 71. first connecting portion; 72. common electrode;

[0050] 80. fourth insulating layer;

[0051] 90. pixel electrode layer; 91. third connection portion; 92. fourth connection portion; 93. pixel electrode;

[0052] 001, first via hole; 002, second via hole; 003, third via hole; 004, fourth via hole. DETAILED DESCRIPTION

[0053] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0054] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0055] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0056] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0057] Embodiment 1

[0058] Please also read Figure 1 , Figure 2 , Figure 3 and Figure 4 , the array substrate 100 provided in the embodiment of the present application is now described.

[0059] The array substrate 100 includes a substrate 000, a common electrode line 10, a first insulating layer 20, a first metal layer, a second insulating layer 40, a second metal layer 50, a third insulating layer 60, a common electrode layer 70, a fourth insulating layer 80 and a pixel electrode layer 90 which are stacked in sequence; the first metal layer is formed with a scanning line 31, and at least part of the common electrode line 10 is stacked with at least part of the scanning line 31.

[0060] In application, the array substrate 100 extends in the plane where the x-direction and the y-direction shown in the figure are located, and the thickness direction of the array substrate 100 is the z-direction shown in the figure. The substrate 000, the common electrode line 10, the first insulating layer 20, the first metal layer, the second insulating layer 40, the second metal layer 50, the third insulating layer 60, the common electrode layer 70, the fourth insulating layer 80 and the pixel electrode layer 90 are stacked and arranged along the z-direction in the figure, the scanning line 31 extends along the x-direction in the figure, the common electrode line 10 extends along the x-direction in the figure, the scanning line 31 and the common electrode line 10 are stacked and arranged along the z-direction in the figure, and the common electrode line 10 is located on the side of the scanning line 31 facing the substrate 000 so that the projection of part of the common electrode line 10 in the z-direction in the figure coincides with the projection of the scanning line 31 in the z-direction in the figure.

[0061] Therefore, the common electrode line 10 and the scanning line 31 are overlapped to save the wiring space between pixels, thereby increasing the aperture ratio of the pixels.

[0062] The common electrode layer 70 is formed with a common electrode 72 and a first connection portion 71 connected to the common electrode 72, and the first connection portion 71 is electrically connected to the common electrode line 10. The pixel electrode 93 includes a plurality of slits and an electrode portion disposed between the slits. The common electrode 72 is disposed on a side of the pixel electrode 93 away from the substrate 000, and a fringe electric field can be generated between the common electrode 72 and the pixel electrode 93.

[0063] In applications, such as Figure 1 As shown, the common electrode layer 70 includes a common electrode 72 and a first connecting portion 71 protruding from the common electrode 72, the first connecting portion 71 extends toward the common electrode line 10 to connect the common electrode line 10 and the common electrode 72, and a portion of the first connecting portion 71 is arranged between the common electrode line 10 and the common electrode 72, thereby increasing the distribution uniformity of the ITO material between the common electrode 72 and the common electrode line 10, and further improving the flatness of the area between the common electrode 72 and the common electrode line 10.

[0064] The array substrate 100 provided by the present application has the following beneficial effects: compared with the prior art, on the one hand, the array substrate 100 provided by the present application reduces the wiring space occupied by the common electrode line 10 by stacking the scanning line 31 and the common electrode line 10 in the thickness direction of the array substrate 100, and the common electrode 72 is electrically connected to the common electrode line 10 through the first connecting portion 71, so that the array substrate 100 provided by the present application has the advantage of a large pixel aperture ratio; on the other hand, the process of the common electrode line 10, the first metal layer and the second metal layer 50 of the array substrate 100 provided by the present application is before the third insulating layer 60 and the fourth insulating layer 80, thereby reducing the influence of the common electrode line 10, the first metal layer and the second metal layer 50 on the surface flatness of the array substrate 100, further making the array substrate 100 provided by the present application have the advantage of a flat surface, improving the flatness of the array substrate 100, and solving the problem of defects caused by sliding of the spacer column due to the uneven surface of the array substrate 100.

[0065] In addition, the array substrate 100 provided in the present application is provided with a first connecting portion 71 between the common electrode line 10 and the common electrode 72. The first connecting portion 71 is located between the pixel electrode 93 and the scanning line 31 in the planar direction in which the array substrate 100 extends. Compared with the array substrate 100 in the related art, the array substrate 100 provided in the present application has a higher flatness in the area between the scanning line 31 and the pixel electrode 93, further improving the surface flatness.

[0066] In some embodiments provided in this application, Figures 1 to 4 As shown, the first connection portion 71 is overlapped with a portion of the common electrode line 10;

[0067] The second metal layer 50 is formed with a data line 55 and a second connection portion 51. The first insulating layer 20 and the second insulating layer 40 are provided with a first via hole 001, and the common electrode line 10 and the second connection portion 51 are connected through the first via hole 001.

[0068] The pixel electrode layer 90 is formed with pixel electrodes 93 and a third connection portion 91 arranged at intervals, and a second via hole 002 is provided in the fourth insulating layer 80, and the first connection portion 71 and the third connection portion 91 are connected through the second via hole 002;

[0069] The third insulating layer 60 and the fourth insulating layer 80 are provided with a third via hole 003 , and the second connection portion 51 and the third connection portion 91 are connected through the third via hole 003 .

[0070] In applications, such as Figure 1 , Figure 3 and Figure 4As shown, the first connection portion 71 extends to the side of a portion of the common electrode line 10 away from the substrate 000, that is, the projection of the first connection portion 71 in the thickness direction coincides with the projection of a portion of the common electrode line 10 in the thickness direction, and a second connection portion 51 and a third connection portion 91 are provided between the first connection portion 71 and the common electrode line 10, and the second connection portion 51 is connected to the common electrode line 10 through the first via hole 001, and the third connection portion 91 is connected to the second connection portion 51 through the third via hole 003, and the first connection portion 71 is adjacent to the third connection portion 91 through the second via hole 002, so that the first connection portion 71 and the common electrode line 10 are connected through the second connection portion 51 and the third connection portion 91, thereby realizing electrical connection between the first connection portion 71 and the common electrode line 10.

[0071] Thus, the first connection portion 71 and the common electrode line 10 are connected through the second connection portion 51 and the third connection portion 91, so that the first connection portion 71 and the common electrode line 10 are electrically connected, so that the common electrode line 10 can supply power to the common electrode 72. Figure 1 As shown, in the area between the scanning line 31 and the pixel electrode 93, the material of the pixel electrode layer 90 and the material of the second metal layer 50 are distributed in the x direction in the figure, which increases the distribution uniformity of the ITO material between the common electrode 72 and the common electrode line 10, thereby improving the flatness of the spacing area between the pixel electrode 93 and the scanning line 31 in the x direction and y direction in the figure, thereby making the array substrate 100 provided in the present application have the advantage of a flat surface.

[0072] In addition, the manufacturing process of the common electrode line 10, the first metal layer and the second metal layer 50 of the array substrate 100 provided in the present application is before the third insulating layer 60 and the fourth insulating layer 80, thereby reducing the influence of the common electrode line 10, the first metal layer and the second metal layer 50 on the surface flatness of the array substrate 100, and further making the array substrate 100 provided in the present application have the advantage of a flat surface.

[0073] In some embodiments provided in this application, Figure 1 As shown, the common electrode line 10 is provided with a protruding portion 11 , and the second connecting portion 51 is arranged to overlap with the protruding portion 11 .

[0074] In applications, such as Figure 1 As shown, the protrusion 11 extends along the common electrode line 10 toward the pixel electrode 93, so that the protrusion 11 is located between the common electrode line 10 and the pixel electrode 93 in the y direction in the figure, the first connection portion 71 overlaps with part of the protrusion 11, and the second connection portion 51 and the third connection portion 91 both overlap with part of the protrusion 11, that is, the first connection portion 71, the second connection portion 51 and the third connection portion 91 are all located in the interval between the common electrode line 10 and the pixel electrode 93 in the y direction in the figure.

[0075] As a result, on the one hand, the uniformity of the conductive material in the spacing area between the common electrode line 10 and the pixel electrode 93 in the y direction in the figure is improved, thereby improving the flatness of the area between the pixel electrode 93 and the scanning line 31, so that the array substrate 100 provided in the present application has the advantage of a flat surface. On the other hand, the first connecting portion 71, the second connecting portion 51 and the third connecting portion 91 are made on the protruding portion 11 to avoid the first connecting portion 71, the second connecting portion 51 and the third connecting portion 91 from affecting the common electrode line 10 and the scanning line 31.

[0076] In some embodiments provided in this application, Figure 1 and Figure 2 As shown, the pixel electrode layer 90 further forms a fourth connection portion 92 connected to the pixel electrode 93, and the second metal layer 50 further forms a source electrode 54, a drain electrode 53 and a fifth connection portion 52, and the fifth connection portion 52 is connected to the drain electrode 53;

[0077] The second insulating layer 40 , the third insulating layer 60 and the fourth insulating layer 80 are provided with a fourth via hole 004 , and the fourth connecting portion 92 and the fifth connecting portion 52 are connected through the fourth via hole 004 .

[0078] In application, the array substrate 100 is applied to the FFS liquid crystal panel, a semiconductor layer is provided between the source 54 and the drain 53, and part of the scanning line 31 extends to one side of the semiconductor layer along the y direction in the figure to form a gate of a thin film transistor (TFT), and the conduction state of the thin film semiconductor is controlled by the potential of the scanning line 31, thereby controlling the on-off between the source 54 and the drain 53, and the fifth connecting part 52 is connected to the fourth connecting part 92 through the fourth via 004, and the fourth connecting part 92 is connected to the pixel electrode 93, so that the thin film semiconductor controls the potential in the pixel electrode 93 according to the potential of the scanning line 31, thereby realizing the control of the pixel.

[0079] Therefore, in the spacing area between the common electrode line 10 and the pixel electrode 93, the data line 55, the source 54, the drain 53, the fifth connecting part 52 and the second connecting part 51 are sequentially distributed along the x direction in the figure, so that the second metal layer 50 is distributed in the spacing area between the common electrode line 10 and the pixel electrode 93 along the x direction in the figure, thereby improving the flatness of the spacing area between the pixel electrode 93 and the scanning line 31 in the y direction in the figure, and further making the array substrate 100 provided in the present application have the advantage of a flat surface.

[0080] In some embodiments provided in this application, Figure 1 As shown, the protruding portion 11 and the fifth connecting portion 52 are both located on the same side of the data line 55 or the common electrode line 10 .

[0081] In application, the protrusion 11 and the fifth connecting portion 52 are both located in the spacing area between the pixel electrode 93 and the scanning line 31 in the y direction in the figure, that is, the first connecting portion 71, the second connecting portion 51, the third connecting portion 91, the fourth connecting portion 92, the fifth connecting portion 52, the protrusion 11, the source 54, the thin film semiconductor and the drain 53 are all located on the same side of the pixel electrode 93 facing the scanning line 31 in the y direction in the figure.

[0082] Therefore, on the one hand, the basic internal wiring space of the FFS array is further reduced, thereby improving the aperture ratio of the array substrate 100 provided in the present application. On the other hand, the distribution uniformity of the ITO material and the metal material in the array substrate 100 provided in the present application in the x direction and the y direction in the figure is improved, thereby making the array substrate 100 provided in the present application have the advantage of a smooth surface.

[0083] In some embodiments provided in this application, Figure 2 As shown, the third insulating layer 60 includes a self-leveling insulating layer 61 .

[0084] In application, the third insulating layer 60 includes a self-leveling insulating layer 61 and a fifth insulating layer 62 . The fifth insulating layer 62 is located between the self-leveling insulating layer 61 and the second metal layer 50 . The self-leveling insulating layer 61 is an acrylic self-leveling material.

[0085] Therefore, on the one hand, the self-leveling insulating layer 61 in the third insulating layer 60 has good self-leveling performance, so that after the third insulating layer 60 is prepared, the surface flatness of the array substrate 100 provided by the present application is high. On the other hand, the process of the common electrode line 10, the first metal layer and the second metal layer 50 of the array substrate 100 provided by the present application is before the third insulating layer 60. After the third insulating layer 60 is manufactured by self-leveling, the influence of the common electrode line 10, the first metal layer and the second metal layer 50 on the surface flatness of the array substrate 100 is significantly reduced, so that the array substrate 100 provided by the present application has the advantage of a flat surface.

[0086] Embodiment 2

[0087] The display panel provided in the embodiments of the present application is described below.

[0088] The present application provides a display panel, comprising the array substrate 100 in any one of the above embodiments.

[0089] The beneficial effects of the display panel provided by the present application are as follows: compared with the prior art, on the one hand, the array substrate 100 provided by the present application has the advantage of a high aperture ratio, so that the display panel provided by the present application has the advantage of a high brightness; on the other hand, the array substrate 100 provided by the present application has the advantage of a flat surface, so that the display panel provided by the present application can avoid debris on the PS side after the array substrate 100 and the PS side are aligned, so that the display panel provided by the present application has the advantage of a low failure rate.

[0090] Embodiment 3

[0091] Combine the following Figure 1 , Figure 2 , Figure 3 and Figure 4 The array substrate manufacturing method provided in the embodiment of the present application is described.

[0092] The present application provides a method for manufacturing an array substrate, comprising:

[0093] A common electrode line 10, a first insulating layer 20 and a first metal layer are sequentially formed on one surface of a substrate 000, wherein the first metal layer includes a scanning line 31, and at least a part of the scanning line 31 is stacked with a part of the common electrode line 10;

[0094] A second insulating layer 40, a second metal layer 50, a third insulating layer 60, a common electrode layer 70, a fourth insulating layer 80 and a pixel electrode layer 90 are sequentially formed on a side of the first metal layer away from the first insulating layer 20. The common electrode layer 70 is formed with a common electrode 72 and a first connecting portion 71 connected to the common electrode 72. The first connecting portion 71 is electrically connected to the common electrode line 10.

[0095] In application, the scanning line 31 and the common electrode line 10 both extend along the x direction in the figure, and as shown in FIG. Figure 1 As shown, part of the scanning lines 31 and part of the common electrode lines 10 overlap in the z direction in the figure, which, on the one hand, saves the wiring space in the array substrate 100, thereby improving the aperture ratio of the array substrate 100, and on the other hand, the process of the common electrode lines 10, the first metal layer and the second metal layer 50 is before the third insulating layer 60 and the fourth insulating layer 80, thereby reducing the influence of the common electrode lines 10, the first metal layer and the second metal layer 50 on the surface flatness of the array substrate 100, further making the array substrate 100 provided by the present application have the advantage of a flat surface.

[0096] The beneficial effect of the array substrate manufacturing method provided in the present application is that: compared with the prior art, the array substrate manufacturing method of the present application stacks the scanning line 31 and the common electrode line 10 in the thickness direction of the array substrate 100, reducing the routing space of the scanning line 31 and the common electrode line 10, so that the array substrate 100 manufactured by the array substrate manufacturing method has the advantage of a large pixel aperture ratio; on the other hand, the array substrate manufacturing method provided in the present application manufactures a first connecting portion 71 between the common electrode line 10 and the common electrode 72, that is, the first connecting portion 71 is also located between the pixel electrode 93 and the scanning line 31. Compared with the array substrate 100 in the related art, the array substrate 100 manufactured by the array substrate manufacturing method provided in the present application has a higher flatness in the area between the scanning line 31 and the pixel electrode 93, so that the array substrate 100 manufactured by the array substrate manufacturing method has the advantage of a smooth surface.

[0097] In some embodiments provided in the present application, the array substrate manufacturing method further includes:

[0098] In the process of manufacturing the second insulating layer 40 , a first via hole 001 is manufactured in the first insulating layer 20 and the second insulating layer 40 ;

[0099] In the process of manufacturing the second metal layer 50, the second metal layer 50 includes a data line 55 and a second connection portion 51, and the second connection portion 51 is connected to the common electrode layer 70 through a first via hole 001;

[0100] In the process of manufacturing the common electrode layer 70 and the fourth insulating layer 80 , a second via hole 002 is manufactured in the fourth insulating layer 80 , and a third via hole 003 is manufactured in the third insulating layer 60 and the fourth insulating layer 80 ;

[0101] Among them, the common electrode layer 70 includes a common electrode 72 and a first connecting part 71, the pixel electrode layer 90 includes a pixel electrode 93 and a third connecting part 91, the third connecting part 91 is connected to the first connecting part 71 through the second via 002, and the third connecting part 91 is connected to the second connecting part 51 through the third via 003.

[0102] In application, a first via 001, a second metal layer 50, a first connecting portion 71, a second via 002, a third via 003 and a third connecting portion 91 are sequentially made on the side of a portion of the common electrode line 10 facing away from the substrate 000, so that the common electrode line 10 and the common electrode 72 are conductively connected through the second connecting portion 51, the third connecting portion 91 and the first connecting portion 71.

[0103] The second connection portion 51 is manufactured while the data line 55 is manufactured, the first connection portion 71 is processed while the common electrode 72 is manufactured, and the third connection portion 91 is manufactured while the pixel electrode 93 is manufactured.

[0104] Thus, on the one hand, the processing of the first connection part 71, the second connection part 51 and the third connection part 91 is more compatible with the processing technology of the array substrate 100, and on the other hand, the first connection part 71 and the common electrode line 10 are connected through the second connection part 51 and the third connection part 91, so that the first connection part 71 and the common electrode line 10 are electrically connected, so that the common electrode line 10 can supply power to the common electrode 72. Figure 1 As shown, in the area between the scanning line 31 and the pixel electrode 93, the material of the pixel electrode layer 90 and the material of the second metal layer 50 are distributed in the x direction in the figure, which increases the distribution uniformity of the ITO material between the common electrode 72 and the common electrode line 10, thereby improving the flatness of the spacing area between the pixel electrode 93 and the scanning line 31 in the y direction in the figure, thereby making the array substrate manufactured by the array substrate manufacturing method have the advantage of a flat surface.

[0105] In some embodiments provided in the present application, the array substrate manufacturing method further includes:

[0106] During the process of manufacturing the pixel electrode layer 90 , a fourth via hole 004 is manufactured in the third insulating layer 60 and the fourth insulating layer 80 .

[0107] In the process of manufacturing the second metal layer 50 , the second metal layer 50 further includes a source electrode 54 , a drain electrode 53 and a fifth connecting portion 52 , and the fifth connecting portion 52 is connected to the drain electrode 53 .

[0108] The pixel electrode layer 90 further includes a fourth connection portion 92 , and the fourth connection portion 92 is connected to the fifth connection portion 52 through a fourth via hole 004 .

[0109] In application, the data line 55 , the source 54 , the drain 53 and the fifth connection part 52 are manufactured at the same time as the second connection part 51 , and the fourth connection part 92 is manufactured at the same time as the pixel electrode 93 , and the fifth connection part 52 and the fourth connection part 92 are connected through the fourth via 004 .

[0110] Thus, on the one hand, the processing of the fourth connection part 92 and the fifth connection part 52 is more compatible with the processing technology of the array substrate 100. On the other hand, the data line 55, the source electrode 54, the drain electrode 53, the fifth connection part 52 and the second connection part 51 are sequentially distributed in the interval area between the common electrode line 10 and the pixel electrode 93 along the x direction in the figure, so that the second metal layer 50 is distributed in the interval area between the common electrode line 10 and the pixel electrode 93 along the x direction in the figure, thereby improving the flatness of the interval area between the pixel electrode 93 and the scanning line 31 in the y direction in the figure, and thus making the array substrate 100 provided by the present application have the advantage of a flat surface. The above is only a preferred embodiment of the present application, and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. An array substrate, characterized in that: It includes a substrate, a common electrode line, a first insulating layer, a first metal layer, a second insulating layer, a second metal layer, a third insulating layer, a common electrode layer, a fourth insulating layer and a pixel electrode layer which are stacked in sequence; The first metal layer is formed with a scan line, the scan line and the common electrode line extend in the same direction, and the common electrode line and the scan line are overlapped along the thickness direction of the array substrate, and the projection of the common electrode line in the thickness direction of the array substrate partially overlaps with the projection of the scan line in the thickness direction of the array substrate, so that the wiring space between pixels is saved by overlapping the common electrode line and the scan line, thereby increasing the aperture ratio of the pixel; The common electrode layer is formed with a common electrode and a first connecting portion connected to the common electrode; The common electrode line is provided with a protruding portion, the second metal layer is sequentially formed with a data line, a source electrode, a drain electrode, a fifth connecting portion and a second connecting portion along the extension direction of the common electrode line, the source electrode is connected to the data line, the drain electrode is arranged at intervals with the source electrode and the drain electrode is connected to the fifth connecting portion, the second connecting portion is arranged at intervals with the fifth connecting portion, the second connecting portion is stacked with the protruding portion, the first insulating layer and the second insulating layer are provided with a first via hole, and the protruding portion and the second connecting portion are connected through the first via hole; The pixel electrode layer is formed with a pixel electrode, a third connection portion and a fourth connection portion, the fourth connection portion is connected to the pixel electrode, and the fourth connection portion is stacked with the fifth connection portion, a second via hole is provided in the fourth insulating layer, and the first connection portion and the third connection portion are connected through the second via hole, a third via hole is provided in the third insulating layer and the fourth insulating layer, and the second connection portion and the third connection portion are connected through the third via hole; The source, the drain, the fifth connection portion and the second connection portion are all located between the common electrode line and the pixel electrode, and the source, the drain, the fifth connection portion and the second connection portion are arranged in sequence along the extension direction of the common electrode line, the fourth connection portion and the third connection portion are located between the common electrode line and the pixel electrode, and the fourth connection portion and the third connection portion are arranged along the extension direction of the common electrode line.

2. The array substrate according to claim 1, wherein: A fourth via hole is provided in the second insulating layer, the third insulating layer and the fourth insulating layer, and the fourth connecting portion and the fifth connecting portion are connected through the fourth via hole.

3. The array substrate according to claim 1, wherein: The protruding portion and the fifth connecting portion are both located on the same side of the data line or the common electrode line.

4. The array substrate according to any one of claims 1 to 3, characterized in that: The third insulating layer includes a self-leveling insulating layer.

5. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 4.

6. A method for manufacturing an array substrate, characterized in that: The steps include: A common electrode line, a first insulating layer and a first metal layer are sequentially formed on one surface of a substrate, wherein the first metal layer includes a scan line, and the scan line and the common electrode line are stacked so that the wiring space between pixels is saved by stacking the common electrode line and the scan line, thereby increasing the aperture ratio of the pixel; A second insulating layer, a second metal layer, a third insulating layer, a common electrode layer, a fourth insulating layer and a pixel electrode layer are sequentially formed on a side of the first metal layer away from the first insulating layer, wherein the common electrode layer is formed with a common electrode and a first connecting portion connected to the common electrode, and the first connecting portion is electrically connected to the common electrode line; In the process of manufacturing the second insulating layer, manufacturing a first via hole in the first insulating layer and the second insulating layer; In the process of manufacturing the second metal layer, the second metal layer includes a data line and a second connecting portion, and the second connecting portion is connected to the common electrode layer through the first via hole; In the process of manufacturing the common electrode layer and the fourth insulating layer, a second via hole is manufactured in the fourth insulating layer, and a third via hole is manufactured in the third insulating layer and the fourth insulating layer; In the process of manufacturing the pixel electrode layer, a fourth via hole is manufactured in the third insulating layer and the fourth insulating layer; Wherein, the common electrode layer includes a common electrode and a first connection portion, the pixel electrode layer includes a pixel electrode and a third connection portion, the third connection portion is connected to the first connection portion through the second via hole, and the third connection portion is connected to the second connection portion through the third via hole, the second metal layer also includes a source electrode, a drain electrode and a fifth connection portion, the fifth connection portion is connected to the drain electrode, the pixel electrode layer also includes a fourth connection portion, and the fourth connection portion is connected to the fifth connection portion through the fourth via hole; The source, the drain, the fifth connection portion and the second connection portion are all located between the common electrode line and the pixel electrode, and the source, the drain, the fifth connection portion and the second connection portion are arranged in sequence along the extension direction of the common electrode line, the fourth connection portion and the third connection portion are located between the common electrode line and the pixel electrode, and the fourth connection portion and the third connection portion are arranged along the extension direction of the common electrode line.

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