Array substrate, preparation method thereof and display panel

Abstract

The invention relates to an array substrate and a preparation method thereof, and a display panel. The array substrate comprises a first transistor and a substrate; the buffer layer is positioned on one side of the substrate; the first metal layer is located on the side, away from the substrate, of the buffer layer, the first metal layer comprises a first grid electrode of the first transistor, the first grid electrode comprises a first surface, a convex body extending in the direction away from the substrate is formed on the first surface, the convex body has a first orthographic projection on the substrate, and the first surface located outside the convex body has a second orthographic projection on the substrate; the active layer is located on the side, away from the substrate, of the first metal layer, the active layer comprises an active structure, the active structure comprises a channel region, at least part of the channel region and at least part of the first grid electrode are oppositely arranged, and the orthographic projection of the first part of the active structure on the substrate at least partially covers the first orthographic projection; and a second metal layer comprising a first pole of the first transistor, the first pole of the first transistor comprising a second surface facing the substrate, the second surface being in contact with the second portion.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to array substrates and their fabrication methods, and display panels. Background Technology

[0002] With the rapid iteration of near-eye display technologies such as Virtual Reality (VR) and Augmented Reality (AR), users have placed higher demands on the pixel density (Pixels Per Inch, PPI) of display panels in order to achieve immersive, grain-free displays.

[0003] Organic light-emitting diode (OLED) display panels are considered the mainstream technology for high PPI displays due to their advantages such as self-illumination, high contrast, and wide viewing angle. However, OLED pixel circuits require multiple array substrates (TFTs) (such as switching TFTs, driving TFTs, and compensation TFTs) to achieve pixel charging, discharging, and brightness control. The area ratio of the TFTs directly affects the space utilization of the pixel circuit. For example, the larger the TFT area, the lower the pixel aperture ratio, and the more difficult it is to meet the high PPI requirements for small-sized devices.

[0004] In related technologies, oxide semiconductor TFTs are widely used in the driving circuits of OLED display panels due to their excellent properties such as high carrier mobility and low off-state current. However, when the channel length is reduced to the submicron level to shrink the device area, a problem of negative threshold voltage dispersion occurs, meaning that the voltage values ​​of different devices differ significantly, leading to uneven pixel brightness and mura phenomena in the display image. To ensure voltage consistency, related technologies have to increase the channel length, which directly results in an increase in the horizontal projected area of ​​the TFT, making it impossible to meet the high PPI requirements of small-sized TFTs. Summary of the Invention

[0005] Based on this, an array substrate and its fabrication method are provided, as well as a display panel, which can increase the channel length and improve the overall performance.

[0006] An array substrate includes a first transistor, the array substrate comprising:

[0007] Substrate;

[0008] A buffer layer is located on one side of the substrate;

[0009] A first metal layer is located on the side of the buffer layer away from the substrate. The first metal layer includes a first gate of the first transistor. The first gate includes a first surface away from the substrate. The first surface is formed with at least one protrusion extending in a direction away from the substrate. The protrusion has a first orthographic projection on the substrate. The first surface located outside the protrusion has a second orthographic projection on the substrate.

[0010] An active layer, insulated from the first metal layer, is located on the side of the first metal layer away from the substrate. The active layer includes an active structure, which includes a channel region. At least a portion of the channel region and at least a portion of the first gate are disposed opposite each other. The active structure includes a first portion and a second portion. The orthographic projection of the first portion on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second portion on the substrate at least partially covers the second orthographic projection.

[0011] A second metal layer is located on the side of the active layer away from the substrate. The second metal layer includes a first electrode of the first transistor, and the first electrode of the first transistor includes a second surface facing the substrate. The second surface is in contact with the second portion.

[0012] In one embodiment, the first electrode of the first transistor includes a third surface remote from the substrate, the orthographic projection of the third surface onto the substrate being within the orthographic projection of the second surface onto the substrate;

[0013] Preferably, the edge of the channel region in the orthographic projection of the substrate coincides with the edge of the first electrode of the first transistor in the orthographic projection of the substrate;

[0014] Preferably, the protrusion includes a top wall opposite to the substrate, and the orthographic projection of the channel region onto the top wall at least partially overlaps with the orthographic projection of the first gate onto the top wall;

[0015] Preferably, the protrusion includes a sidewall surrounding the top wall, and the orthographic projection of the channel region onto the sidewall at least partially overlaps with the orthographic projection of the first gate onto the sidewall.

[0016] Preferably, the material of the buffer layer includes inorganic materials;

[0017] Preferably, the array substrate further includes a first insulating layer located between the first metal layer and the active layer, wherein the first insulating layer at least covers the first gate.

[0018] Preferably, the material of the first insulating layer includes inorganic materials;

[0019] Preferably, the second metal layer further includes a second electrode of the first transistor, the second electrode of the first transistor including a fourth surface facing the substrate, the fourth surface being in contact with the second portion;

[0020] Preferably, the second electrode of the first transistor includes a fifth surface remote from the substrate, the orthographic projection of the fifth surface onto the substrate being within the orthographic projection of the fourth surface onto the substrate.

[0021] In one embodiment, it further includes:

[0022] The second insulating layer is located on the side of the second metal layer and the active layer away from the substrate, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the second metal layer on the substrate and the orthographic projection of the active layer on the substrate.

[0023] A third metal layer, located on the side of the second insulating layer away from the substrate, includes the second gate of the first transistor, the orthogonal projection of the second gate onto the substrate covering the orthogonal projection of the channel region onto the substrate;

[0024] Preferably, the material of the second insulating layer includes inorganic materials.

[0025] In one embodiment, it further includes:

[0026] A third insulating layer is located on the side of the third metal layer away from the substrate, and the thickness of the third insulating layer is greater than the thickness of the first insulating layer, and / or the thickness of the third insulating layer is greater than the thickness of the second insulating layer;

[0027] Preferably, the material of the third insulating layer includes organic materials;

[0028] Preferably, the active layer is made of at least one of oxide semiconductor, monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

[0029] In one embodiment, the orthographic projection of the channel region onto the second metal layer is located between the first electrode and the second electrode;

[0030] Preferably, the orthographic projection of the second surface on the substrate has a first dimension l, the orthographic projection of the fourth surface on the substrate has a second dimension m, the orthographic projection of the first surface on the substrate has a third dimension n, and the orthographic projection of the channel region on the substrate has a dimension p = n - (l + m).

[0031] In one embodiment, the first part includes a first sub-channel region disposed opposite to the top wall of the protrusion and a second sub-channel region disposed opposite to the side wall of the protrusion, wherein the first sub-channel region and the second sub-channel region form a preset angle.

[0032] Preferably, the range of the preset included angle is [90°, 150°].

[0033] In one embodiment, the array substrate includes a pixel driving circuit, the pixel driving circuit including at least one of the first transistors;

[0034] Preferably, the pixel driving circuit includes a driving module and at least one switching module, wherein at least one transistor in the driving module and the at least one switching module is the first transistor.

[0035] In one embodiment, the pixel driving circuit includes a plurality of first transistors, the at least one switching module includes a data writing module, the transistor in the driving module is one of the plurality of first transistors, and the transistor in the data writing module is one of the plurality of first transistors, wherein:

[0036] The area of ​​the channel region of the first transistor in the driving module projected onto the substrate is greater than the area of ​​the channel region of the first transistor in the data writing module projected onto the substrate.

[0037] A display panel comprising an array substrate as described above.

[0038] A method for fabricating an array substrate, comprising:

[0039] Provide substrate;

[0040] A buffer layer is formed on one side of the substrate;

[0041] A first metal layer is formed on the side of the buffer layer away from the substrate using physical vapor deposition or atomic layer deposition techniques; the first metal layer is patterned to form a first gate of a first transistor, the first gate including a first surface away from the substrate, the first surface having at least one protrusion extending away from the substrate, the protrusion having a first orthographic projection on the substrate, and the first surface located outside the protrusion having a second orthographic projection on the substrate.

[0042] An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein the active layer is formed by physical vapor deposition or atomic layer deposition; the active layer is patterned to form an active structure, the active structure including a channel region, at least a portion of the channel region and at least a portion of the first gate are disposed opposite to each other, the active structure includes a first part and a second part, the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second part on the substrate at least partially covers the second orthographic projection;

[0043] A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form the first electrode of the first transistor; the first electrode of the first transistor includes a second surface facing the substrate, and the second surface is in contact with a second portion of the active layer.

[0044] The above-mentioned array substrate, its fabrication method, and display panel,

[0045] The first gate includes a protrusion extending away from the substrate, and a first portion of the active layer covers the orthogonal projection of the protrusion. The effective length of the channel region is mainly determined by the height of the protrusion (vertical direction). With a very small horizontal projection area, a sufficiently long channel path length can be obtained by increasing the height of the protrusion, avoiding the short-channel effect caused by channel shortening, and significantly reducing the area occupied by the TFT on the substrate, thereby improving the pixel aperture ratio and meeting the requirements of high PPI display panels for small-sized devices.

[0046] At least a portion of the channel region and at least a portion of the first gate are disposed opposite to each other, and the protrusion extends perpendicularly to the substrate. The protrusion structure enables the first gate to form a surrounding or multi-faceted electric field modulation on the channel region, which enhances the control capability of the gate electric field on the channel region, effectively suppresses the leakage-induced barrier reduction effect, makes the threshold voltage more stable, reduces the voltage value difference between different devices, thereby avoiding pixel brightness unevenness and spot phenomenon, and improving display uniformity.

[0047] Since the first electrode, which extends from the active layer to the flat surface outside the convex body, can directly contact the active layer without needing a via penetrating the insulating layer, this eliminates the complex steps of fabricating interlayer insulating layers and drilling vias in related technologies, simplifying the fabrication process. Simultaneously, planar contact offers a larger contact area and a more stable interface compared to via contact, effectively reducing contact resistance and improving the transmission efficiency of the drive current and the reliability of the device. Attached Figure Description

[0048] Figure 1 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0049] Figure 2 This is a schematic flowchart of a method for fabricating an array substrate in an exemplary embodiment.

[0050] Figure 3 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0051] Figure 4 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0052] Figure 5 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0053] Figure 6 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0054] Figure 7 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0055] Figure 8 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0056] Figure 9 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0057] Figure 10 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0058] Figure 11 This is a schematic cross-sectional view of an array substrate in an exemplary embodiment.

[0059] Figure label:

[0060] 1. Substrate; 2. Buffer layer; 3. First metal layer; 31. First gate; 311. First surface; 312. Protrusion; 3121. Top wall; 3122. Side wall; 4. Active layer; 41. Active structure; 411. First portion; 4111. First sub-channel region; 4112. Second sub-channel region; 412. Second portion; 5. Second metal layer; 51. First electrode; 511. Second surface; 512. Third surface; 52. Second electrode; 521. Fourth surface; 522. Fifth surface; 6. First insulating layer; 7. Second insulating layer; 8. Third metal layer; 81. Second gate; 9. Third insulating layer. Detailed Implementation

[0061] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application are described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0062] First Embodiment

[0063] like Figure 1 As shown, an array substrate suitable for high-resolution OLED display panels. Compared with planar channel transistors in related technologies, this embodiment constructs a vertically extending channel region by introducing a protrusion structure in the gate metal layer, achieving decoupling between "small horizontal projected area" and "long effective channel length," effectively suppressing the short-channel effect and improving the performance of the pixel driving circuit. The array substrate includes a first transistor T, and the array substrate includes a substrate 1, a buffer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5.

[0064] Substrate 1 can be a rigid substrate made of glass, which has good flatness and light transmittance, and is suitable for the substrate requirements of OLED display panels.

[0065] In this embodiment, as Figure 1 As shown, buffer layer 2 is located on one side of substrate 1. The material of buffer layer 2 is an inorganic material, such as at least one selected from silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), and hafnium oxide (HfO2). Buffer layer 2 is used to improve the surface flatness of substrate 1 and simultaneously prevent impurities (such as sodium ions) in substrate 1 from diffusing into active layer 4, thus avoiding the influence of impurities on the electrical performance of active layer 4 and ensuring the stability of the transistor's threshold voltage.

[0066] In this embodiment, as Figure 1 As shown, the first metal layer 3 is located on the side of the buffer layer 2 facing away from the substrate 1, and the first metal layer 3 includes the first gate 31 of the first transistor T. The material of the first gate 31 can be molybdenum (Mo) as the main metal layer, which is suitable for subsequent dry etching processes due to its low resistivity, high melting point and good etching resistance. Of course, a stacked structure of one or more of aluminum (Al), copper (Cu), titanium (Ti), tungsten (W) or indium tin oxide (ITO) can also be used.

[0067] A molybdenum thin film is deposited to the target thickness using magnetron sputtering to ensure sufficient conductive cross-sectional area. Photoresist is then applied for patterning. Finally, dry etching is performed to remove the unprotected molybdenum film, forming the first gate 31 with protrusions 312. After etching, residual photoresist is removed using oxygen plasma ashing or wet stripping.

[0068] The first gate 31 includes a first surface 311 facing away from the substrate 1, and at least one protrusion 312 extending away from the substrate 1 is formed on the first surface 311. The cross-sectional shape of the protrusion 312 can be rectangular, trapezoidal (narrow at the top and wide at the bottom), or inverted V-shaped. In this embodiment, a trapezoidal cross-section is preferred to facilitate the stepped coverage of the subsequent active layer 4 and prevent wire breakage.

[0069] The protrusion 312 has a first orthographic projection on the substrate 1, and the first surface 311 (i.e., the flat region) located outside the protrusion 312 has a second orthographic projection on the substrate 1. The extension direction of the protrusion 312 is perpendicular to the surface of the substrate 1, so that the length of the subsequently formed channel is physically equal to the height of the protrusion 312, thereby achieving long channel characteristics with a very small horizontal projection area.

[0070] It should be noted that the aforementioned protrusion 312 is not limited to one, such as... Figure 10 and Figure 11 As shown, one, two, three, or more bumps 312 can be added depending on design requirements. Adding multiple bumps 312 can further extend the total length of the channel path, thereby improving the transistor's driving capability.

[0071] By providing the protrusion 312, the conductive channel of the first gate 31 is extended in the vertical direction. The height of the protrusion 312 determines the length of the vertical channel, thereby increasing the total length of the channel without increasing the horizontal occupied area.

[0072] In this embodiment, as Figure 1 As shown, an active layer 4 is formed on the side of the first metal layer 3 away from the substrate 1, and the active layer 4 is insulated from the first metal layer 3. The material of the active layer 4 can be varied, including at least one of amorphous silicon, polycrystalline silicon, monocrystalline silicon, and oxide semiconductors. In this embodiment, an oxide semiconductor (e.g., IGZO material containing In, Ga, Zn, O, and doped elements) can be used, and the film is formed using atomic layer deposition (ALD) technology.

[0073] Due to the presence of the protrusion 312, the first surface 311 forms a stepped shape, and the active layer 4 is formed using physical vapor deposition (PVD) or atomic layer deposition (ALD) technology. ALD technology, with its excellent conformality, ensures that the active layer 4 uniformly covers the top and sidewalls of the protrusion 312, avoiding line breaks and guaranteeing the continuity of the carrier transport path. This is beneficial for achieving high carrier mobility, low off-state current, and excellent threshold voltage uniformity.

[0074] The active layer 4 includes an active structure 41, which includes a channel region, and at least a portion of the channel region and at least a portion of the first gate 31 are disposed opposite to each other. Specifically, the active structure 41 includes a first portion 411 and a second portion 412.

[0075] The first portion 411 is located on the top and sidewalls of the protrusion 312, and its orthographic projection on the substrate 1 at least partially covers the aforementioned first orthographic projection. This portion of the active layer 4 and the protrusion 312 constitute the vertical channel body of the transistor.

[0076] The second portion 412 is located on a flat surface outside the protrusion 312 (i.e., the non-protruding area of ​​the first surface 311), and its orthographic projection on the substrate 1 at least partially covers the aforementioned second orthographic projection. This portion of the active layer 4 serves as a transition connecting the vertical channel and the source / drain electrodes.

[0077] The actual path length of the channel area is determined by the first part 411 and the second part 412, wherein the length of the first part 411 is determined by the height of the protrusion 312, thereby realizing the design of a long channel in the vertical direction.

[0078] In this embodiment, as Figure 1 As shown, the second metal layer 5 is located on the side of the active layer 4 away from the substrate 1. The second metal layer 5 includes a first electrode 51 of the first transistor, such as a source or drain. The first electrode 51 of the first transistor includes a second surface 511 facing the substrate 1, and the second surface 511 is in contact with the second portion 412.

[0079] The first electrode 51 is formed by magnetron sputtering deposition, photolithography, and dry etching. Since the second portion 412 of the active layer 4 extends to a flat area outside the protrusion 312, the second metal layer 5 can directly contact the active layer 4 in this flat area without the need for vias penetrating the insulating layer. This planar contact method not only simplifies the process but also increases the contact area, effectively reducing contact resistance.

[0080] In planar TFTs of related technologies, the channel length is limited by photolithography precision and horizontal space. In this embodiment, the channel length is mainly determined by the height (vertical direction) of the protrusion 312, while the horizontal projected area is determined only by the top area of ​​the protrusion 312. By increasing the height of the protrusion 312, long channel characteristics can be obtained with a very small horizontal projected area, thereby significantly reducing the area occupied by the TFT on the substrate, improving the pixel aperture ratio, and meeting the high PPI (high resolution) requirements.

[0081] The long-channel characteristic effectively suppresses the leakage-induced barrier reduction effect and the negative drift of the threshold voltage, reduces the dispersion of electrical parameters between devices, and avoids the appearance of spots on the display screen.

[0082] The active layer 4 was deposited using ALD technology, which ensured good conformal coverage of the protrusion 312. The direct planar contact between the source / drain electrodes and the active layer 4 avoided the alignment difficulties and short-circuit risks of via processes, thus improving yield.

[0083] This embodiment successfully constructs an array substrate suitable for high-resolution displays by introducing a first gate 31 with a protrusion 312 structure and a corresponding vertical channel active layer 4, which greatly optimizes space utilization while ensuring device performance.

[0084] In this embodiment, as Figure 1 As shown, the first electrode 51 of the first transistor T includes a third surface 512 away from the substrate 1, and the orthographic projection of the third surface 512 on the substrate 1 lies within the orthographic projection of the second surface 511 on the substrate 1. The first electrode 51 has a solid frustum or truncated cone structure with a smaller top and larger bottom in the direction perpendicular to the substrate 1, or at least its horizontal cross-sectional dimension at the top is smaller than that at the bottom. The first electrode 51 is a solid metal electrode directly formed on the surface of the active layer 4, avoiding the drilling and filling processes in related technologies. The first electrode 51 forms a direct physical connection with the second part 412 of the active layer 4.

[0085] To optimize transistor performance, the edge of the channel region projected onto the substrate 1 coincides with the edge of the first electrode 51 of the first transistor T projected onto the substrate 1. This ensures a precise match between the lateral dimensions of the channel region and the contact area of ​​the first electrode 51, maximizing carrier injection efficiency and minimizing parasitic capacitance, thereby significantly improving the switching speed and driving capability of the transistor.

[0086] The protrusion 312 includes a top wall 3121 opposite to the substrate 1 and a side wall 3122 surrounding the top wall 3121. Exemplarily, the orthographic projection of the channel region onto the top wall 3121 at least partially overlaps with the orthographic projection of the first gate 31 onto the top wall 3121; simultaneously, the orthographic projection of the channel region onto the side wall 3122 also at least partially overlaps with the orthographic projection of the first gate 31 onto the side wall 3122. This omnidirectional projection overlap design ensures that the gate electric field can simultaneously perform three-dimensional surround modulation of the channel region from the top and side walls of the protrusion 312, greatly enhancing the control capability of the first gate 31 over the channel. Especially when using a protruding structure, it can effectively suppress short-channel effects and improve the threshold voltage stability and drive current of the transistor.

[0087] In this embodiment, as Figure 1 As shown, the array substrate also includes a first insulating layer 6 located between the first metal layer 3 and the active layer 4, for achieving electrical insulation between the first gate 31 and the active layer 4. The first insulating layer 6 at least covers the first gate 31, and covers not only the flat surface but also the first gate 31 located on the protrusion 312.

[0088] The material of the first insulating layer 6 includes inorganic materials. For example, the material of the first insulating layer 6 can be one or more of silicon oxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), and tantalum oxide (Ta2O5). In one possible implementation, the first insulating layer 6 adopts a stacked structure. For example, the lower layer (the layer that directly contacts the first gate 31) is aluminum oxide (Al2O3), and the upper layer is silicon nitride (SiNx). The aluminum oxide layer is deposited using atomic layer deposition (ALD) technology. ALD technology has excellent conformal properties and atomic-level interface control capabilities, which can effectively repair fine defects on the metal surface of the first gate 31 and improve interface quality. The silicon nitride layer, as the main insulating barrier layer, provides high dielectric strength and the ability to block water and oxygen penetration. Regardless of the height of the protrusion 312, the ALD technology process can ensure that the first insulating layer 6 uniformly covers the first gate 31 without any breaks or pinholes, thereby completely avoiding the risk of short circuit between the first gate 31 and the active layer 4, and ensuring the high reliability and high yield of the device.

[0089] In this embodiment, as Figure 1 As shown, the second metal layer 5 also includes a second electrode 52 of the first transistor T. The second electrode 52 and the first electrode 51 are respectively disposed on both sides of the protrusion 312, serving as the source and drain, respectively. The second electrode 52 includes a fourth surface 521 facing the substrate 1. The fourth surface 521 is in direct contact with the second portion 412 of the active layer 4 and is used to introduce or extract charge carriers in the channel region.

[0090] Similarly, to clarify the physical structure of the second electrode 52, the second electrode 52 of the first transistor T includes a fifth surface 522 located away from the substrate 1, the orthographic projection of the fifth surface 522 onto the substrate 1 lying within the orthographic projection of the fourth surface 521 onto the substrate 1. Like the first electrode 51, the second electrode 52 is also a solid electrode without vias.

[0091] The second electrode 52 is formed using standard semiconductor processes such as magnetron sputtering deposition, photolithography, and dry etching. Since the second portion 412 of the active layer 4 extends to the flat surface outside the protrusion 312 (i.e., the second orthographic projection area), the second electrode 52 can directly contact this portion without the need for additional via processes. This self-aligned planar contact design eliminates the complex steps of "preparing interlayer insulating layers and drilling" in related processes, simplifying the fabrication process, reducing costs, and significantly decreasing the contact resistance between the source / drain electrode and the active layer 4, thereby improving the overall electrical performance of the device.

[0092] Second Embodiment

[0093] like Figure 9 As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. The second embodiment differs from the first embodiment in that the array substrate further includes a second insulating layer 7 and a third metal layer 8, forming a dual-gate structure to achieve precise control of the transistor threshold voltage and further improve the electrical performance and stability of the device.

[0094] After forming the second metal layer 5 (including the first electrode 51 and the second electrode 52), a second insulating layer 7 is formed on the side of the second metal layer 5 away from the substrate 1. The material of the second insulating layer 7 preferably includes inorganic materials, such as silicon nitride (SiNx), silicon oxide (SiO2), or silicon oxynitride (SiON), which gives it excellent insulation properties and the ability to block water and oxygen.

[0095] In this embodiment, as Figure 9 As shown, the orthographic projection of the second insulating layer 7 onto the substrate 1 not only covers the orthographic projection of the second metal layer 5 onto the substrate 1, but also covers the orthographic projection of the active layer 4 onto the substrate 1. The second insulating layer 7 fills in the source, drain, and active layer structure 41 below, providing a flat base for the upper metal layer.

[0096] The third metal layer 8 is located on the side of the second insulating layer 7 away from the substrate 1. The third metal layer 8 includes the second gate 81 of the first transistor T. The orthogonal projection of the second gate 81 onto the substrate 1 covers the orthogonal projection of the channel region onto the substrate 1. Since the channel region is located in the active layer 4 and is opposite to the first gate 31, the second gate 81 corresponds exactly to the channel region in the vertical direction.

[0097] During the fabrication process, the second insulating layer 7 can be formed using processes such as atomic layer deposition or plasma-enhanced chemical vapor deposition. Since the second insulating layer 7 is deposited over the entire surface, it seamlessly covers the first electrode 51 and the second electrode 52 of the second metal layer 5, as well as the surface of the active layer 4. Subsequently, a metal material (such as molybdenum, aluminum, or copper) is deposited on the second insulating layer 7, and a third metal layer 8 and a second gate electrode 81 are formed through a patterning process.

[0098] The second gate 81 serves as a control gate. By applying a specific bias voltage, the carrier concentration in the channel region of the active layer 4 can be effectively adjusted, thereby precisely controlling the threshold voltage of the transistor. Unlike related technologies that require connecting electrodes of different layers through vias, the second insulating layer 7 in this embodiment is a continuous, full-surface layer, and the second gate 81 is formed directly on it, avoiding the risk of interlayer short circuits caused by via alignment deviations or poor filling.

[0099] The second insulating layer 7 completely covers the underlying metal traces and active layer 4, providing excellent protection and preventing damage to the underlying structure from subsequent processes. Simultaneously, the second gate 81 completely covers the channel region, ensuring the effectiveness and reliability of electric field control and resolving the technical problem in related technologies where complete coverage is impossible due to the presence of vias.

[0100] This embodiment introduces a second gate structure composed of a second insulating layer 7 and a third metal layer 8. While retaining the advantages of the long vertical channel in the first embodiment, it increases the ability to control the threshold voltage, significantly improving the performance and yield of thin-film transistors in high PPI display applications.

[0101] Third Embodiment

[0102] like Figure 1 , Figure 9 As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. The third embodiment differs from the first embodiment in that the array substrate further includes a third insulating layer 9 to address the surface step problem caused by the underlying vertical structure and to achieve physical and electrical isolation between layers.

[0103] The third insulating layer 9 serves as an interlayer dielectric layer, and its specific location varies depending on the underlying structure.

[0104] In the first embodiment, the third insulating layer 9 covers the second metal layer 5 and the active layer 4. In this case, the third insulating layer 9 not only fills the gap between the second metal layer 5 (the first electrode 51 and the second electrode 52), but also completely covers the exposed surface of the active layer 4, including the first portion 411 corresponding to the vertical channel region within the protrusion 312 and the second portion 412 on the flat surface. The third insulating layer 9 physically isolates the underlying second metal layer 5 and the active layer 4 from the subsequently fabricated upper structure, preventing short circuits.

[0105] In the second embodiment, the third insulating layer 9 covers the third metal layer 8. At this time, the third insulating layer 9 is located on the side of the third metal layer 8 (second gate 81) away from the substrate 1.

[0106] Due to the presence of the second metal layer 5 and the protrusion 312, the bottom surface has significant undulations (steps). In order to fabricate subsequent functional layers (such as pixel electrodes) on this uneven surface, the thickness of the third insulating layer 9 is specifically designed in this embodiment.

[0107] The thickness of the third insulating layer 9 is greater than the thickness of the second insulating layer 7 (based on the first embodiment) or greater than the thickness of the first insulating layer 6 (based on the second embodiment). The thicker insulating layer has a stronger step coverage capability.

[0108] The third insulating layer 9 is used to achieve global planarization. After the third insulating layer 9 is deposited, its surface is polished by chemical mechanical polishing (CMP) to eliminate the steps caused by the vertical structure of the underlying layer, and to process the uneven surface of the underlying layer into a smooth plane. After CMP treatment, the surface flatness of the third insulating layer 9 can meet the stringent requirements of subsequent photolithography processes (such as the fabrication of pixel electrodes).

[0109] The material selection for the third insulating layer 9 is diverse and can be flexibly chosen according to specific performance requirements. For example, organic materials can be selected. Organic materials include polyimide (PI), benzocyclobutene (BCB), or acrylic resin. Organic materials have a lower dielectric constant (k value), which can effectively reduce the parasitic capacitance between the source / drain electrodes and the upper metal layer, thereby improving the switching speed and high-frequency characteristics of the device.

[0110] For example, inorganic materials can be selected. Inorganic materials are one or more of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or hafnium oxide (HfO2). Inorganic materials possess high dielectric strength, good moisture barrier properties, and excellent semiconductor process compatibility.

[0111] For example, a multilayer structure can be chosen. The third insulating layer 9 can also be a composite structure of inorganic and organic insulating materials. For example, SiO2 or SiNx can be used at the bottom to provide water and oxygen barrier capabilities for the device due to their density; PI or BCB can be used at the top to achieve good planarization and reduce the k value due to their fluidity.

[0112] The third insulating layer 9 completely encapsulates the complex metal traces and active layer 4 structure below, preventing short-circuit risks with the upper structure and improving device reliability. By optimizing the thickness and combining it with CMP technology, the third insulating layer 9 effectively eliminates surface undulations caused by the underlying vertical channels and metal electrodes, providing a flat substrate for the fabrication of pixel electrodes in high PPI display panels, ensuring the film quality and patterning accuracy of the pixel electrodes.

[0113] This embodiment solves the planarization and interlayer isolation problems in multilayer structures by adding a third insulating layer 9 with specific thickness and material properties, while retaining the advantages of the vertical channel structure, thus providing a process basis for the fabrication of highly integrated, high-resolution OLED display panels.

[0114] Fourth embodiment

[0115] like Figure 1 As shown, an array substrate suitable for high-resolution OLED display panels effectively suppresses short-channel effects and improves the performance of pixel driving circuits by introducing a vertical channel structure. The array substrate includes a first transistor T, a substrate 1, a spacer layer 2, a first metal layer 3, an active layer 4, and a second metal layer 5. Compared with the previous embodiments, this embodiment defines the specific geometric layout of the channel region, the cross-sectional shape of the protrusion 312, and the dimensional relationship between the channel region and the source / drain electrodes, further optimizing the electrical performance and process yield of the transistor.

[0116] In this embodiment, as Figure 1 As shown, the orthographic projection of the channel region on the second metal layer 5 is located between the first electrode 51 and the second electrode 52. For example, the orthographic projection of the second surface 511 on the substrate 1 has a first dimension l, the orthographic projection of the fourth surface 521 on the substrate 1 has a second dimension m, the orthographic projection of the first surface 311 on the substrate 1 has a third dimension n, and the orthographic projection of the channel region on the substrate 1 has a dimension p, which satisfies p = n - (l + m).

[0117] The horizontal projection size of the channel region is equal to the total horizontal projection size of the first gate 31 minus the width of the source and drain, which ensures the precise positioning of the channel region in the horizontal direction, avoids the erosion of the channel by the source and drain, and thus effectively suppresses the short-channel effect.

[0118] In this embodiment, as Figure 1As shown, the first portion 411 of the active layer 4 includes a first sub-channel region 4111 and a second sub-channel region 4112. The first sub-channel region 4111 is disposed opposite to the top wall 3121 of the protrusion 312 and is located at the top of the protrusion 312, where it is relatively less affected by the gate electric field. The second sub-channel region 4112 is disposed opposite to the side wall 3122 of the protrusion 312 and is located at the side wall of the protrusion 312, where it is controlled by the gate electric field strength and is the main conductive channel.

[0119] The first sub-channel region 4111 and the second sub-channel region 4112 form a preset angle, which ranges from [90°, 150°].

[0120] When the included angle is 90° (i.e., rectangular protrusion 312), the manufacturing process is the least difficult, and the first gate 31 has the strongest control over the channel region. When the included angle is 100°, 110°, 120°, 130°, 140°, or 150°, the sidewalls of protrusion 312 form a slope, and the channel region forms an inclined path. This slope structure not only further increases the effective transport path length of charge carriers (achieving a larger equivalent channel length at the same protrusion 312 depth), but also makes the active layer 4 more gentle when covering the top of protrusion 312, avoiding film breakage caused by excessively steep steps, and significantly improving device yield.

[0121] The protrusion 312 adopts a trapezoidal (narrower at the top and wider at the bottom) cross-section. During the etching of the spacer layer 2, the slope is formed on the sidewalls by adjusting the proportion of etching gas and utilizing the polymer deposition effect. The trapezoidal structure makes the electric field lines distributed more smoothly on the sloping sidewalls, avoiding electric field concentration at the corners of the rectangular protrusion 312, significantly reducing the standard deviation of the threshold voltage, and improving the uniformity of the panel display. By setting the extension direction of the channel region to be perpendicular to the substrate 1 and located on the protrusion 312, the decoupling of "small horizontal area" and "long channel length" is successfully achieved. The channel length is no longer limited by the minimum feature size in the horizontal space, but by the film thickness in the vertical direction, which is easy to control and has high precision, thus solving the area technology problem of pixel driving circuits in high PPI OLED panels.

[0122] The second part 412 is located on both sides of the protrusion 312, serving as a bridge connecting the vertical channel and the planar electrode. The actual path length of the channel region (i.e., the total distance of carrier transport) is equal to the sum of the first part 411 (vertical path) and the second part 412 (horizontal path), forming a "folded path".

[0123] The second part 412 serves as a contact transition region, acting as a buffer between the second metal layer 5 and the first part 411. The second metal layer 5 forms a large-area planar contact with the active layer 4 through the planar second part 412, effectively reducing contact resistance. The second part 412 provides a wider carrier injection path, ensuring efficient connectivity between the source / drain and the channel region.

[0124] This embodiment achieves long channel characteristics with a very small horizontal projected area by precisely defining the dimensional relationship between the channel region and the electrode, adopting a trapezoidal protrusion 312 structure with a specific included angle, and optimizing the segmented design of the channel region. At the same time, it improves the electric field distribution and film coverage quality, greatly enhancing the performance uniformity and production yield of thin film transistors. It is particularly suitable for pixel driving circuits of high PPI OLED display panels.

[0125] Fifth Embodiment

[0126] like Figure 1 , Figure 9 As shown, an array substrate integrates a pixel driving circuit. The pixel driving circuit is used to drive display units (such as OLED light-emitting devices) for display, and includes at least one first transistor T. The first transistor T adopts the vertical channel structure in the aforementioned embodiments. By providing a protrusion 312 in the spacer layer 2 and utilizing a stepped first gate 3 and a cover active layer 4, a balance between long channel characteristics and small planar area is achieved, making it particularly suitable for high-resolution (high PPI) display panels.

[0127] In this embodiment, as Figure 1 , Figure 9 As shown, the pixel driving circuit includes a driving module and at least one switching module.

[0128] The driving module provides driving current to illuminate the pixel units. In this embodiment, the transistor in the driving module is the first transistor T. Because the driving module needs to carry a large current to ensure display brightness, the driving capability of the transistor is required to be high.

[0129] The switching module is used to control the writing and cutoff of signals. In this embodiment, the switching module includes at least a data writing module, and the transistor in the data writing module is also a first transistor T. The data writing module is mainly responsible for transmitting the data voltage signal to the gate or source of the driving module. Its main requirements are high-speed switching characteristics and low leakage current, and the requirement for driving current is relatively low.

[0130] In this embodiment, the pixel driving circuit includes a plurality of first transistors T. In order to optimize circuit performance within a limited pixel space, this embodiment has differentiated the design of the first transistors T in different functional modules.

[0131] For example, the area of ​​the channel region of the corresponding first transistor T in the driving module projected onto the substrate 1 is greater than the area of ​​the channel region of the corresponding first transistor T in the data writing module projected onto the substrate 1.

[0132] To achieve a larger drive current, the first transistor T in the drive module employs a larger bump 312 size and / or a wider active layer 4 coverage area. This results in a larger projected area of ​​its channel region, thereby increasing the channel width, effectively reducing on-resistance, and improving current drive capability.

[0133] The data writing module performs the switching function and does not require a large current. Therefore, its corresponding first transistor T uses a relatively small protrusion 312 size and active layer 4 coverage area, resulting in a smaller projected area of ​​the channel region. This not only meets the switching speed requirements but also significantly reduces the planar area occupied by the transistor, which is beneficial for achieving a high aperture ratio and high integration density of the pixel.

[0134] In this embodiment, the first transistor T of the vertical channel structure is applied to the pixel driving circuit. By precisely controlling the ratio of the orthogonal projection area of ​​the transistor channel region in the driving module and the data writing module, the defect between driving capability and pixel area in the high-resolution display panel is successfully solved, and the overall performance of the display panel is improved.

[0135] Sixth Embodiment

[0136] A display panel includes an array substrate as described in any of the above embodiments. The display panel provided in this embodiment, by employing an array substrate with a vertical channel structure, achieves long-channel characteristics within a very small horizontal projected area, effectively suppressing short-channel effects. This allows the display panel to maintain good electrical performance and uniformity even at high resolutions.

[0137] By integrating the aforementioned array substrate, this display panel achieves high resolution, high aperture ratio, low power consumption, and high reliability, making it particularly suitable for high-end OLED display products.

[0138] Seventh Embodiment

[0139] A method for fabricating an array substrate, suitable for high-resolution OLED display panels, effectively suppresses short-channel effects and improves the performance of pixel driving circuits by constructing thin-film transistors with vertical channel structures. Figure 2 As shown, the method for fabricating the array substrate includes the following steps:

[0140] S1, Provide a substrate.

[0141] In step S1, as Figure 3As shown, glass is selected as substrate 1. To ensure the adhesion of subsequent thin film layers and device performance, substrate 1 needs to be pretreated. For example, it is ultrasonically cleaned sequentially with deionized water, acetone, and ethanol to remove organic residues and particulate impurities from the surface; then it is dried with high-purity nitrogen and baked in an oven to completely remove moisture. This pretreatment step provides a flat and clean device substrate, which is fundamental to ensuring the uniformity of the electrical performance of thin-film transistors.

[0142] S2. A buffer layer is formed on one side of the substrate.

[0143] In step S2, as Figure 4 As shown, a buffer layer 2 is formed on one side of the substrate 1. The buffer layer 2 is made of an inorganic material, such as one or more stacks of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), aluminum oxide (Al2O3), or hafnium oxide (HfO2). The buffer layer 2 can be formed by plasma-enhanced chemical vapor deposition or magnetron sputtering. Its main function is to improve the surface flatness of the substrate 1, and at the same time, it acts as a barrier layer to prevent impurities (such as sodium ions) in the substrate 1 from diffusing into the subsequently formed active layer, thereby avoiding the influence of impurities on the electrical performance of the active layer and ensuring the stability of the transistor threshold voltage.

[0144] S3. A first metal layer is formed on the side of the buffer layer away from the substrate using physical vapor deposition or atomic layer deposition techniques; the first metal layer is patterned to form the first gate of the first transistor, the first gate including a first surface away from the substrate, and at least one protrusion extending away from the substrate is formed on the first surface.

[0145] In step S3, as Figure 5 As shown, a first metal layer 3 is formed on the side of the buffer layer 2 away from the substrate 1 using physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques.

[0146] If the first metal layer 3 is a metal gate, magnetron sputtering is preferably used to obtain low resistivity and high melting point characteristics; if excellent step coverage is required, ALD technology can also be used. The first metal layer 3 is subjected to photolithography and dry etching to form the first gate 31 of the first transistor T.

[0147] The first gate 31 includes a first surface 311 facing away from the substrate 1. At least one protrusion 312 extending away from the substrate 1 is formed on the first surface 311 by a controlled etching process. The protrusion 312 has a first orthographic projection on the substrate 1, and the first surface 311 (i.e., a flat region) located outside the protrusion 312 has a second orthographic projection on the substrate 1. The cross-sectional shape of the protrusion 312 can be rectangular, trapezoidal (narrow at the top, wide at the bottom), or inverted V-shaped. For example, a trapezoidal cross-section is chosen to facilitate the stepped coverage of the subsequent active layer 4 and prevent wire breakage.

[0148] By providing a protrusion 312, the conductive channel of the first gate 31 is extended vertically. The height of the protrusion 312 determines the length of the subsequent vertical channel, thereby increasing the total channel length without increasing the horizontal occupied area.

[0149] S4. An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein, physical vapor deposition or atomic layer deposition technology is used to form the active layer; the active layer is patterned to form an active structure.

[0150] In step S4, as Figure 6 As shown, an active layer 4 is formed on the side of the first metal layer 3 away from the substrate 1. The active layer 4 is isolated from the first metal layer 3 by an insulating layer. The active layer 4 is formed using physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques. The material of the active layer 4 includes amorphous silicon, polycrystalline silicon, single-crystal silicon, or oxide semiconductors (such as IGZO). In this embodiment, for example, an oxide semiconductor is selected to obtain high carrier mobility.

[0151] Because of the step caused by the protrusion 312 on the surface of the first gate 31, the ALD technology, with its excellent conformability, can make the active layer 4 uniformly cover the top, sidewalls and flat area of ​​the first surface 311 of the protrusion 312, avoid line breakage and ensure the continuity of the carrier transport path.

[0152] The active layer 4 is photolithographically and etched to form an active structure 41. The active structure 41 includes a channel region, at least a portion of which is disposed opposite to at least a portion of the first gate 31 (particularly the bump 312). The active structure 41 specifically includes a first portion 411 and a second portion 412.

[0153] The first part 411 is located on the top surface and sidewall of the protrusion 312, and its orthographic projection on the substrate 1 at least partially covers the first orthographic projection, forming a vertical conductive channel using the protrusion 312. The second part 412 is located on the flat surface outside the protrusion 312 (i.e., the non-protruding area of ​​the first surface 311), and its orthographic projection on the substrate 1 at least partially covers the second orthographic projection, serving as a transition connecting the vertical channel and the source / drain.

[0154] S5. A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form the first electrode of the first transistor.

[0155] In step S5, as Figure 7As shown, a second metal layer 5 is formed on the side of the active layer 4 away from the substrate 1, and the second metal layer 5 is patterned to form the first electrode 51 of the first transistor. The first electrode 51 is formed by magnetron sputtering deposition of metal followed by photolithography and dry etching.

[0156] The first electrode 51 of the first transistor includes a second surface 511 facing the substrate 1. This second surface 511 is in direct contact with the second portion 412 of the active layer 4. Since the second portion 412 of the active layer 4 extends into a flat region outside the protrusion 312, the second metal layer 5 can directly form a large-area planar contact with the active layer 4 in this flat region, eliminating the need for vias penetrating the insulating layer. This planar contact method simplifies the manufacturing process, avoids the alignment difficulties associated with via etching, and simultaneously increases the contact area, effectively reducing contact resistance.

[0157] It should be noted that between steps S3 and S4 above, such as Figure 1 As shown, the process may also include the step of forming a first insulating layer 6. The first insulating layer 6 is deposited using an atomic layer deposition (ALD) process, and the materials include silicon oxide, silicon nitride, aluminum oxide, etc. The excellent conformality of the ALD process ensures that the first insulating layer 6 can uniformly cover the sidewalls and bottom of the first gate 31 without any breaks, effectively preventing short circuits between the first gate 31 and the active layer 4.

[0158] After step S5, as Figure 1 As shown, the process may also include the step of forming a third insulating layer 9. The third insulating layer 9 is deposited on the second metal layer 5 and the active layer 4, and planarized by a chemical mechanical polishing process to eliminate the steps caused by the vertical structure of the underlying layer, providing a flat substrate for the subsequent fabrication of pixel electrodes.

[0159] This embodiment successfully fabricates a thin-film transistor with a vertical channel by introducing a convex structure during the gate formation stage and using PVD or ALD technology to achieve conformal coverage of the active layer. This method achieves long-channel characteristics with an extremely small horizontal projected area, effectively suppresses short-channel effects, and simplifies the source and drain processes through planar contact, making it highly suitable for the mass production requirements of high-resolution, high-integration OLED display panels.

[0160] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0161] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes a first transistor and comprises: Substrate; A buffer layer is located on one side of the substrate; A first metal layer is located on the side of the buffer layer away from the substrate. The first metal layer includes a first gate of the first transistor. The first gate includes a first surface away from the substrate. The first surface is formed with at least one protrusion extending in a direction away from the substrate. The protrusion has a first orthographic projection on the substrate. The first surface located outside the protrusion has a second orthographic projection on the substrate. An active layer, insulated from the first metal layer, is located on the side of the first metal layer away from the substrate. The active layer includes an active structure, which includes a channel region. At least a portion of the channel region and at least a portion of the first gate are disposed opposite each other. The active structure includes a first portion and a second portion. The orthographic projection of the first portion on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second portion on the substrate at least partially covers the second orthographic projection. A second metal layer is located on the side of the active layer away from the substrate. The second metal layer includes a first electrode of the first transistor, and the first electrode of the first transistor includes a second surface facing the substrate. The second surface is in contact with the second portion.

2. The array substrate according to claim 1, characterized in that, The first electrode of the first transistor includes a third surface remote from the substrate, and the orthographic projection of the third surface onto the substrate lies within the orthographic projection of the second surface onto the substrate; Preferably, the edge of the channel region in the orthographic projection of the substrate coincides with the edge of the first electrode of the first transistor in the orthographic projection of the substrate; Preferably, the protrusion includes a top wall opposite to the substrate, and the orthographic projection of the channel region onto the top wall at least partially overlaps with the orthographic projection of the first gate onto the top wall; Preferably, the protrusion includes a sidewall surrounding the top wall, and the orthographic projection of the channel region onto the sidewall at least partially overlaps with the orthographic projection of the first gate onto the sidewall. Preferably, the material of the buffer layer includes inorganic materials; Preferably, the array substrate further includes a first insulating layer located between the first metal layer and the active layer, wherein the first insulating layer at least covers the first gate. Preferably, the material of the first insulating layer includes inorganic materials; Preferably, the second metal layer further includes a second electrode of the first transistor, the second electrode of the first transistor including a fourth surface facing the substrate, the fourth surface being in contact with the second portion; Preferably, the second electrode of the first transistor includes a fifth surface remote from the substrate, the orthographic projection of the fifth surface onto the substrate being within the orthographic projection of the fourth surface onto the substrate.

3. The array substrate according to claim 2, characterized in that, Also includes: The second insulating layer is located on the side of the second metal layer and the active layer away from the substrate, and the orthographic projection of the second insulating layer on the substrate covers the orthographic projection of the second metal layer on the substrate and the orthographic projection of the active layer on the substrate. A third metal layer, located on the side of the second insulating layer away from the substrate, includes the second gate of the first transistor, the orthogonal projection of the second gate onto the substrate covering the orthogonal projection of the channel region onto the substrate; Preferably, the material of the second insulating layer includes inorganic materials.

4. The array substrate according to claim 3, characterized in that, Also includes: A third insulating layer is located on the side of the third metal layer away from the substrate, and the thickness of the third insulating layer is greater than the thickness of the first insulating layer, and / or the thickness of the third insulating layer is greater than the thickness of the second insulating layer; Preferably, the material of the third insulating layer includes organic materials; Preferably, the active layer is made of at least one of oxide semiconductor, monocrystalline silicon, polycrystalline silicon, and amorphous silicon.

5. The array substrate according to claim 2, characterized in that, The orthogonal projection of the channel region onto the second metal layer is located between the first electrode and the second electrode; Preferably, the orthographic projection of the second surface on the substrate has a first dimension l, the orthographic projection of the fourth surface on the substrate has a second dimension m, the orthographic projection of the first surface on the substrate has a third dimension n, and the orthographic projection of the channel region on the substrate has a dimension p = n - (l + m).

6. The array substrate according to claim 1, characterized in that, The first part includes a first sub-channel area disposed opposite to the top wall of the protrusion and a second sub-channel area disposed opposite to the side wall of the protrusion, wherein the first sub-channel area and the second sub-channel area form a preset angle. Preferably, the range of the preset included angle is [90°, 150°].

7. The array substrate according to claim 1, characterized in that, The array substrate includes a pixel driving circuit, and the pixel driving circuit includes at least one of the first transistors; Preferably, the pixel driving circuit includes a driving module and at least one switching module, wherein at least one transistor in the driving module and the at least one switching module is the first transistor.

8. The array substrate according to claim 7, characterized in that, The pixel driving circuit includes a plurality of first transistors, and the at least one switching module includes a data writing module. The transistor in the driving module is one of the plurality of first transistors, and the transistor in the data writing module is one of the plurality of first transistors, wherein: The area of ​​the channel region of the first transistor in the driving module projected onto the substrate is greater than the area of ​​the channel region of the first transistor in the data writing module projected onto the substrate.

9. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-8.

10. A method for fabricating an array substrate, characterized in that, include: Provide substrate; A buffer layer is formed on one side of the substrate; A first metal layer is formed on the side of the buffer layer away from the substrate using physical vapor deposition or atomic layer deposition techniques; The first metal layer is patterned to form the first gate of the first transistor. The first gate includes a first surface away from the substrate. The first surface is formed with at least one protrusion extending in a direction away from the substrate. The protrusion has a first orthographic projection on the substrate, and the first surface located outside the protrusion has a second orthographic projection on the substrate. An active layer is formed on the side of the first metal layer away from the substrate, and the active layer is insulated from the first metal layer; wherein the active layer is formed by physical vapor deposition or atomic layer deposition; the active layer is patterned to form an active structure, the active structure including a channel region, at least a portion of the channel region and at least a portion of the first gate are disposed opposite to each other, the active structure includes a first part and a second part, the orthographic projection of the first part on the substrate at least partially covers the first orthographic projection, and the orthographic projection of the second part on the substrate at least partially covers the second orthographic projection; A second metal layer is formed on the side of the active layer away from the substrate, and the second metal layer is patterned to form the first electrode of the first transistor; the first electrode of the first transistor includes a second surface facing the substrate, and the second surface is in contact with a second portion of the active layer.

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