Address mapping processing method, device, electronic device and storage medium
By generating preset mapping table entries and calculating the target address offset value, the problem of insufficient physical space length of mapping table entries in embedded storage devices is solved, data reading and writing efficiency is improved, and the number of accesses to flash memory is reduced.
Patent Information
- Application Number
- CN202411245624.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-06
- Publication Date
- 2024-12-17
- Estimated Expiration
- 2044-09-06
AI Technical Summary
In the prior art, the physical space length of the mapping table entry map of the embedded storage device is too small, resulting in the cache space not enough to meet most data read and write operations needs, and frequent access to flash memory is required, resulting in low data read and write efficiency.
By generating preset mapping table entries, recording the mapping relationship between logical addresses and physical addresses, and determining the target physical address based on the target address offset value, expanding the physical space length of each mapping table entry, and reducing the number of accesses to flash memory .
Improve the efficiency of data read and write operations, enable the mapping tables in the cache space to meet most data read and write operations requirements, and reduce the frequency of access to flash memory.
Smart Images
Figure CN118760629B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of address mapping, and in particular to a method, device, electronic device and storage medium for processing address mapping. Background Art
[0002] Embedded storage devices are devices integrated inside electronic devices for storing and accessing data. They are usually closely integrated with other parts of the system to provide efficient and reliable data storage solutions. Usually, a small number of mapping tables are stored in the cache space, and most of the mapping tables are stored in the flash memory. In addition, in the mapping method in the related art, the physical space length mapped by each mapping table item is relatively small, resulting in the mapping table in the cache space being insufficient to meet the needs of most data read and write operations. When performing data read and write operations, it is necessary to first read the mapping table from the flash memory, and then access the data according to the mapping table. Since the flash memory needs to be accessed multiple times, each access to the flash memory has a certain delay, which will lead to low data read and write efficiency. Summary of the invention
[0003] The present application aims to solve at least one of the technical problems existing in the prior art. To this end, the present application proposes a method, device, electronic device and storage medium for processing address mapping, which can expand the physical space length mapped by each mapping table entry.
[0004] According to the first aspect of the present application, the address mapping processing method includes:
[0005] When receiving a first data write instruction, obtaining first write information of the first write data from the first data write instruction; the first write information includes a first starting logical address and a first starting physical address of the first write data;
[0006] Based on the first starting logical address and the first starting physical address, generating a preset mapping table entry; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address;
[0007] When receiving a data read instruction, obtaining a read logical address from the data read instruction;
[0008] Based on the read logical address, determine a target starting logical address from the first starting logical addresses of a plurality of the preset mapping table entries, and calculate a target address offset value between the target starting logical address and the read logical address;
[0009] Determining a target starting physical address from the preset mapping table entry based on the target starting logical address;
[0010] Based on the target starting physical address and the target address offset value, a target storage physical address corresponding to the read logical address is obtained.
[0011] The address mapping processing method according to the embodiment of the present application has at least the following beneficial effects: the address mapping processing method of the present application generates a preset mapping table entry when a first data write instruction is received, and the preset mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address; obtains the read logical address from the data read instruction when a data read instruction is received; based on the read logical address, determines the target starting logical address from the first starting logical addresses of multiple preset mapping table entries, and calculates the target address offset value between the target starting logical address and the read logical address; based on the target starting logical address, obtains the target address offset value between the target starting logical address and the read logical address from the preset mapping table entries; The target starting physical address is determined in the table entry, and the target storage physical address corresponding to the read logical address is obtained based on the target starting physical address and the target address offset value. In this way, even if the read logical address is not equal to the target starting logical address, the target storage physical address corresponding to the read logical address can be determined. Only one preset mapping table entry is needed to map all the physical storage addresses of the first write data, thereby expanding the length of the physical space mapped by each mapping table entry, and then the mapping table in the cache space can meet most data read and write operation requirements, reduce the number of accesses to the flash memory when performing data read and write operations, and improve the efficiency of data read and write operations.
[0012] According to some embodiments of the first aspect of the present application, determining a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculating a target address offset value between the target starting logical address and the read logical address includes:
[0013] Determine, from the first starting logical addresses of the plurality of preset mapping table entries, a candidate starting logical address that is less than or equal to the read logical address;
[0014] Calculating an address offset value between the read logical address and each of the candidate start logical addresses;
[0015] The target address offset value with the smallest value is determined from the address offset values, and the candidate starting logic corresponding to the target address offset value is used as the target starting logic address.
[0016] According to some embodiments of the first aspect of the present application, the first write information further includes a first data length of the first write data; the preset mapping table entry includes a first mapping table entry, and the physical space length mapped by the first mapping table entry is a first preset length;
[0017] The generating a preset mapping table entry based on the first starting logical address and the first starting physical address includes:
[0018] When it is detected that the first starting logical address and the first data length meet a first preset condition, the first mapping table entry is generated; the first preset condition is: the first data length is a multiple of the first preset length, and the first starting logical address is a multiple of the first preset length.
[0019] According to some embodiments of the first aspect of the present application, the generating a preset mapping table entry based on the first starting logical address and the first starting physical address further includes:
[0020] In the case where it is detected that the first starting logical address and the first data length do not meet the first preset condition, if a second data write instruction is received within a preset time length, second write information of the second write data is obtained from the second data write instruction; wherein the second write information includes a second starting logical address, a second starting physical address, and a second data length;
[0021] Performing detection processing on the first written data and the second written data;
[0022] In the case where it is detected that the first write data and the second write data meet a second preset condition, generating the first mapping table entry, and the first mapping table entry records a mapping relationship between the first starting physical address and the first starting logical address;
[0023] The second preset condition is: the first starting logical address is a multiple of the first preset length, the physical storage addresses of the first write data and the second write data are continuous, the logical storage addresses of the first write data and the second write data are continuous, and the sum of the first data length and the second data length of the second write data is equal to the first preset length.
[0024] According to some embodiments of the first aspect of the present application, the preset mapping table entry further includes a second mapping table entry, the physical space length mapped by the second mapping table entry is a second preset length, and the first preset length is greater than the second preset length;
[0025] After the first write data and the second write data are detected and processed, the method further includes:
[0026] When it is detected that the first write data and the second write data do not meet the second preset condition, the second mapping table entry is generated; wherein the second mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address, and the mapping relationship between the second starting logical address and the second starting physical address.
[0027] According to some embodiments of the first aspect of the present application, determining a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculating a target address offset value between the target starting logical address and the read logical address includes:
[0028] Determine, from the first starting logical address in the first mapping table entry, a first candidate logical address that is less than or equal to the read logical address;
[0029] Calculating a first address offset value between the read logical address and each of the first candidate logical addresses;
[0030] Taking the first address offset value with the smallest value as the first candidate address offset value, and detecting the first candidate address offset value;
[0031] When it is detected that the first candidate address offset value is smaller than the first preset length, the first candidate address offset value is used as the target address offset value, and the first candidate logical address corresponding to the target address offset value is used as the target starting logical address.
[0032] According to some embodiments of the first aspect of the present application, after detecting the first candidate address offset value, the method further includes:
[0033] In the case where it is detected that the offset value of the first candidate address is greater than the first preset length, determining a second candidate logical address that is less than or equal to the read logical address from the first starting logical address in the second mapping table entry;
[0034] Calculating a second address offset value between the read logical address and each of the second candidate logical addresses;
[0035] Taking the second address offset value with the smallest value as the second candidate address offset value, and detecting the second candidate address offset value;
[0036] When it is detected that the second candidate address offset value is smaller than the second preset length, the second candidate address offset value is used as the target address offset value, and the second candidate logical address corresponding to the target address offset value is used as the target starting logical address.
[0037] A second aspect of the present application provides an address mapping processing device, including:
[0038] A first acquisition module is used to acquire first write information of first write data from the first data write instruction when receiving the first data write instruction; the first write information includes a first starting logical address and a first starting physical address of the first write data;
[0039] A mapping table entry generating module, configured to generate a preset mapping table entry based on the first starting logical address and the first starting physical address; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address;
[0040] A second acquisition module is used to acquire a read logical address from the data read instruction when receiving the data read instruction;
[0041] a calculation module, configured to determine a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculate a target address offset value between the target starting logical address and the read logical address;
[0042] A determination module, configured to determine a target starting physical address from the preset mapping table entry based on the target starting logical address;
[0043] The target address determination module is used to obtain the target storage physical address corresponding to the read logical address based on the target starting physical address and the target address offset value.
[0044] An embodiment of the third aspect of the present application provides an electronic device, comprising a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the address mapping processing method described in any one of the embodiments of the first aspect of the present application is implemented.
[0045] The fourth aspect of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the address mapping processing method described in any one of the second aspect of the present application.
[0046] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] The present application is further described below with reference to the accompanying drawings and embodiments, wherein:
[0048] Figure 1 A schematic diagram of the steps of the address mapping processing method according to an embodiment of the present application;
[0049] Figure 2 for Figure 1 A specific flow chart of step S140;
[0050] Figure 3 for Figure 1 A schematic diagram of a step flow chart of another embodiment of step S120;
[0051] Figure 4 for Figure 1 A schematic diagram of a step flow chart of another embodiment of step S140;
[0052] Figure 5 This is another step flow chart of the address mapping processing method according to the embodiment of the present application after step S430;
[0053] Figure 6 A schematic diagram of the structure of an address mapping processing device according to an embodiment of the present application;
[0054] Figure 7 A schematic diagram of the structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION
[0055] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.
[0056] In the description of the present application, it should be understood that descriptions involving orientation, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.
[0057] In the description of this application, "several" means more than one, "more" means more than two, "greater than", "less than", "exceed", etc. are understood to exclude the number itself, and "above", "below", "within", etc. are understood to include the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.
[0058] In the description of this application, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in this application based on the specific content of the technical solution.
[0059] In the description of the present application, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.
[0060] In the related art, embedded storage devices are devices integrated inside electronic devices for storing and accessing data. They are usually closely integrated with other parts of the system to provide efficient and reliable data storage solutions. Usually, a small number of mapping tables are stored in the cache space, and most of the mapping tables are stored in the flash memory. And the mapping method in the related art is that the logical address corresponds to the physical address one by one. In this way, a mapping table entry can only map one physical address, that is, the length of a mapping table entry mapped to the physical space is very small, resulting in the mapping table stored in the cache space being insufficient to meet the needs of most data read and write operations. When performing data read and write operations, it is necessary to first read the mapping table from the flash memory, and then access the data according to the mapping table, which will result in low data read and write efficiency.
[0061] Based on this, the embodiments of the present application provide an address mapping processing method, device, electronic device and storage medium, which can expand the physical space length mapped by each mapping table entry, so that the mapping table in the cache space can meet most data reading and writing operation requirements, reduce the number of accesses to the flash memory when performing data reading and writing operations, and improve the efficiency of data reading and writing operations.
[0062] The address mapping processing method of the embodiments of the present application can be applied to terminals. In some embodiments, the terminals can be smart phones, tablet computers, laptop computers, desktop computers, routers, programmable switches, network cards, etc.; in one embodiment, the address mapping processing method can be applied to servers. The server can be configured as an independent physical server, or as a server cluster or distributed system composed of multiple physical servers. It can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms; the software can be an application that implements the address mapping processing method, etc., but is not limited to the above forms.
[0063] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific services or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which services are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.
[0064] First, refer to Figure 1 , Figure 1 The address mapping processing method of the embodiment of the present application is a flowchart of the steps of the address mapping processing method of the embodiment of the present application. The address mapping processing method of the embodiment of the present application includes but is not limited to steps S110 to S160.
[0065] Step S110, when receiving a first data write instruction, obtaining first write information of the first write data from the first data write instruction; the first write information includes a first starting logical address and a first starting physical address of the first write data;
[0066] It is worth noting that the address mapping processing method of the embodiment of the present application can be applied to the solid-state hard disk of an embedded device. The main control module of the embedded device is connected to the solid-state hard disk. When the first write data is to be written into the solid-state hard disk, the main control module sends a first data write instruction to the solid-state hard disk. The first data write instruction includes the first write information of the first write data. The first write information includes the first starting logical address, the first starting physical address and the first data length of the first write data. The first write data includes multiple data. The first starting logical address refers to the logical address of the first data in the first write data, and the first starting physical address refers to the physical address of the first data in the first write data. The first data length refers to the length of the first write data.
[0067] Step S120, generating a preset mapping table entry based on the first starting logical address and the first starting physical address; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address;
[0068] It is worth noting that the preset mapping table entries are stored in the cache of the solid state drive.
[0069] Step S130, when a data read instruction is received, obtaining a read logical address from the data read instruction;
[0070] It is worth noting that when data is to be read, the main control module of the embedded device will send a data read instruction to the solid-state drive. The data read instruction includes a read logical address, and the read logical address refers to the logical address of the data storage to be read.
[0071] Step S140, based on the read logical address, determining a target start logical address from the first start logical addresses of a plurality of preset mapping table entries, and calculating a target address offset value between the target start logical address and the read logical address;
[0072] It is worth noting that since the read logical address may not be equal to the target start logical address, it is necessary to calculate the target address offset value between the target start logical address and the read logical address. For example, if the read logical address is 4352 and the target start logical address is 4096, the calculation of the target address offset value is expressed as: 4352-4096=256.
[0073] Step S150, determining a target starting physical address from a preset mapping table entry based on the target starting logical address;
[0074] It is worth noting that, since the preset mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address, the target starting physical address corresponding to the target starting logical address can be determined from the preset mapping table entry.
[0075] Step S160, obtaining a target storage physical address corresponding to the read logical address based on the target starting physical address and the target address offset value.
[0076] Exemplarily, the target address offset value is 256, the target starting physical address is X, and the target storage physical address is X + 256. After obtaining the target storage physical address, the data stored in the target storage physical address is read, and the data is the data corresponding to the read logical address.
[0077] The address mapping processing method of the embodiment of the present application is through the above steps S110 to S160. When a first data write instruction is received, a preset mapping table entry is generated, and the preset mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address; when a data read instruction is received, the read logical address is obtained from the data read instruction; based on the read logical address, the target starting logical address is determined from the first starting logical addresses of multiple preset mapping table entries, and the target address offset value between the target starting logical address and the read logical address is calculated; based on the target starting logical address, the target starting physical address is determined from the preset mapping table entry, and based on the target starting physical address and the target address offset value, the target storage physical address corresponding to the read logical address is obtained. In this way, even if the read logical address is not equal to the target starting logical address, the target storage physical address corresponding to the read logical address can be determined, and only one preset mapping table entry is needed to map all physical storage addresses of the first write data, so that the physical space length mapped by each mapping table entry can be expanded, so that the mapping table in the cache space can meet most data read and write operation requirements, reduce the number of accesses to the flash memory when performing data read and write operations, and improve the efficiency of data read and write operations.
[0078] It is understandable that, referring to Figure 2 , Figure 2 for Figure 1 A specific flow chart of step S140 in FIG. Step S140 may include but is not limited to steps S210 to S230.
[0079] Step S210, determining a candidate starting logical address that is less than or equal to the read logical address from the first starting logical addresses of a plurality of preset mapping table entries;
[0080] Step S220, calculating the address offset value between the read logical address and each candidate start logical address;
[0081] Step S230, determining a target address offset value with the smallest value from the address offset values, and using the candidate starting logic corresponding to the target address offset value as the target starting logic address.
[0082] Exemplarily, the first starting logical addresses recorded in the preset mapping table entry include 4096, 8192 and 12288, and the read logical address is 8220, then the candidate starting logics include 4096 and 8192. The address offset value between 8220 and 4096 is 4124, and the address offset value between 8192 and 8220 is 28, 28 is less than 4124, therefore, the target address offset value is 28, and the target starting logical address is 8192.
[0083] The embodiment of the present application determines the target starting logical address and the target address offset value from the first starting logical address of multiple preset mapping table entries through steps S210 to S230, thereby facilitating obtaining the target storage physical address corresponding to the read logical address in subsequent steps S150 and S160.
[0084] It can be understood that the preset mapping table entry includes a first mapping table entry, and the physical space length mapped by the first mapping table entry is a first preset length; step S120 may include the following steps:
[0085] When it is detected that the first starting logical address and the first data length meet the first preset condition, a first mapping table entry is generated; the first preset condition is: the first data length is a multiple of the first preset length, and the first starting logical address is a multiple of the first preset length.
[0086] Specifically, the length of the physical space mapped by the first mapping table entry is the first preset length, the length of the cache space of the solid state drive is A, and the length of the first mapping table entry is B. Then A / B first mapping table entries can be stored in the cache space, and the physical space length of each first mapping table entry is the first preset length. Therefore, the cache space can map the physical space of the first preset length*A / B, thus expanding the physical space that the cache space can map. The first data length is a multiple of the first preset length, and the first starting logical address is a multiple of the first preset length, so that it is convenient to determine the target starting logical address based on the first starting logical address when reading data, and it can avoid the first data length being less than the first preset length, which causes the physical space mapped by the first mapping table entry to be less than the first preset length.
[0087] Exemplarily, the first preset length is 4MB. When the starting physical address of the first write data is the 16MB physical address in the flash memory, the first starting logical address is 4096, and the first data length is 4MB, then when generating the first mapping table entry, the first mapping table entry records the mapping relationship between 4096 and the 16MB, then the 16MB to 20MB physical addresses in the flash memory are used to store the first write data. If the first data length is 2MB at this time, then the 16MB to 18MB physical addresses in the flash memory are used to store the first write data, and the 18MB+1KB physical address to the 19MB physical address cannot store data, resulting in waste. Exemplarily, the first preset length is 4MB. When the starting physical address of the first write data is the 16MB in the flash memory, the first starting logical address is 4096, and the first data length is 8MB, then when generating the first mapping table entry, the first mapping table entry records the mapping relationship between 4096 and the 16MB physical address, then the 16MB to 24MB physical addresses in the flash memory are used to store the first write data. When reading data, the read logical address is 4352, and it can be determined that the target starting logical address is 4096. The calculation of the target address offset value is expressed as: 4352-4096=256. The target starting physical address is the 16MB, and the target storage physical address corresponding to the read logical address is 16MB+256KB.
[0088] It should be noted that the first preset length of 4MB in the above example is only an example, but should not be construed as a limitation of the present application. Those skilled in the art may set the first preset length according to actual conditions.
[0089] It is worth noting that if the first data length is N times the first preset length, N first mapping table entries are generated for the first write data, and the first mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address; the i-th mapping table entry records the mapping relationship between (first starting logical address + i*first preset length) and (first starting physical address + i*first preset length), where i is a positive integer greater than or equal to 2 and less than or equal to N.
[0090] It is understandable that, referring to Figure 3 , Figure 3 for Figure 1 Schematic diagram of the step flow of another embodiment of step S120 in FIG. Step S120 may further include but is not limited to steps S310 to S330.
[0091] Step S310, when it is detected that the first starting logical address and the first data length do not meet the first preset condition, if a second data write instruction is received within a preset time length, second write information of the second write data is obtained from the second data write instruction; wherein the second write information includes a second starting logical address, a second starting physical address and a second data length;
[0092] It should be noted that the present application does not make any specific limitation on the preset time length, and those skilled in the art may set the preset time length according to actual conditions; the second data write instruction is sent by the main control module of the embedded device to the solid state drive.
[0093] Step S320, detecting and processing the first written data and the second written data;
[0094] Step S330, when it is detected that the first write data and the second write data meet the second preset condition, a first mapping table entry is generated, and the first mapping table entry records the mapping relationship between the first starting physical address and the first starting logical address; the second preset condition is: the first starting logical address is a multiple of the first preset length, the physical storage addresses of the first write data and each second write data are continuous, the logical storage addresses of the first write data and each second write data are continuous, and the sum of the first data length and the second data length of each second write data is equal to the first preset length.
[0095] Specifically, when it is detected that the first starting logical address and the first data length do not meet the first preset condition, the first mapping table entry is not generated temporarily, and a preset time length is waited. If a second data write instruction sent by the main control module of the embedded device is received within the preset time length, the first write data and the second write data are detected and processed. When it is detected that the first write data and the second write data meet the second preset condition, the first mapping table entry is generated.
[0096] In one embodiment, the first mapping table entry further records the storage order of the first write-in data and the second write-in data, and the first mapping table entry further records the first data length and the second data length.
[0097] It is worth noting that the continuity of the logical storage addresses of the first write data and the second write data means that the first starting logical address + the first data length is equal to the second starting logical address; the continuity of the physical storage addresses of the first write data and the second write data means that the first starting physical address + the first data length is equal to the second starting physical address; for example, the first starting logical address is 4096, and the first data length is 210kb, and the second starting logical address is 4306. Since 4096+210=4306, it can be determined that the logical storage addresses of the first write data and the second write data are continuous.
[0098] It should be noted that the embodiment of the present application does not limit the number of second write data, and the number of second write data can be multiple. When the number of second write data is multiple, for example, N, the logical storage address of the first write data and the second write data is continuous, which means: the first starting logical address + the first data length + (the sum of the second data lengths of the 1st to the i-1th second write data) = the second starting logical address of the i-th second write data; the physical storage address of the first write data and the second write data is continuous, which means: the first starting physical address + the first data length + (the sum of the second data lengths of the 1st to the i-1th second write data) = the second starting physical address of the i-th second write data. i is a positive integer greater than or equal to 2 and less than or equal to N.
[0099] It is worth noting that when the first starting logical address is a multiple of the first preset length, the logical storage addresses of the first write data and the second write data are continuous, and the sum of the first data length and the second data length of the second write data is equal to the first preset length, then a first mapping table entry can be generated. Exemplarily, the first starting physical address is the 4th MB, the first starting logical address is 4096, the first data length is 1MB, the second data length of the second write data is 3MB, the second starting logical address of the second write data is 5120, and the second starting physical address is the 5th MB. Since the sum of the first data length and the second data length is 4MB, and 4096+1MB=5120, the 4th MB+1MB is the 5th MB, so the first mapping table entry can be generated.
[0100] It can be understood that the preset mapping table entry also includes a second mapping table entry, the physical space length mapped by the second mapping table entry is a second preset length, and the first preset length is greater than the second preset length; and after step S320, the following steps are also included:
[0101] When it is detected that the first write data and the second write data do not meet the second preset condition, a second mapping table entry is generated; wherein the second mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address, and the mapping relationship between the second starting logical address and the second starting physical address.
[0102] It is worth noting that when it is detected that the first write data and the second write data do not meet the second preset condition, the second mapping table entry is first generated based on the first write data, and then the second mapping table entry is generated based on the second write data. The second mapping table entry corresponding to the first write data may be one or more, and the second mapping table entry corresponding to the second write data may be one or more. If the first data length is less than the second preset length, the second mapping table entry corresponding to the first write data is one, and if the first data length is greater than the second preset length, the second mapping table entry corresponding to the first write data is multiple. If the second data length is less than the second preset length, the second mapping table entry corresponding to the second write data is one, and if the second data length is greater than the second preset length, the second mapping table entry corresponding to the second write data is multiple.
[0103] Exemplarily, the second preset length is 512KB, the first data length is 510KB, the first starting physical address is C, and the first starting logical address is D, then a second mapping table entry is generated to record the mapping relationship between C and D. Exemplarily, the second preset length is 512KB, the first data length is 520KB, the first starting physical address is E, the first starting logical address is F, 520KB-512KB=8KB; then 2 second mapping table entries are generated, one second mapping table entry records the mapping relationship between F and E, and records that the first data length is 510KB; the other second mapping table entry records the mapping relationship between (F+512) and (E+512), and records that the first data length is 8KB.
[0104] It is worth noting that, in step S310, if the second data write instruction is not received within the preset time period, the second mapping table entry is directly generated based on the first write data.
[0105] It should be noted that both the first mapping table entry and the second mapping table entry are stored in the cache space, and a starting logical address can only be recorded by one of the first mapping table entry or the second mapping table entry.
[0106] It is understandable that, referring to Figure 4 , Figure 4 for Figure 1 FIG. 1 is a flow chart of another embodiment of step S140 in FIG. 1. Step S140 of another embodiment may include but is not limited to steps S410 to S440.
[0107] Step S410, determining a first candidate logical address that is less than or equal to the read logical address from the first starting logical address in the first mapping table entry;
[0108] Step S420, calculating a first address offset value between the read logical address and each first candidate logical address;
[0109] Step S430, taking the first address offset value with the smallest value as the first candidate address offset value, and detecting the first candidate address offset value;
[0110] Step S440, when it is detected that the first candidate address offset value is less than the first preset length, the first candidate address offset value is used as the target address offset value, and the first candidate logical address corresponding to the target address offset value is used as the target starting logical address.
[0111] It is worth noting that since the first preset length of the first mapping table entry is greater than the second preset length of the second mapping table entry, the target starting logical address corresponding to the read logical address is more likely to be recorded in the first mapping table entry. When reading data, first determine whether the target starting logical address corresponding to the read logical address is included in the first mapping table entry through steps S410 to S430, which can improve the efficiency of determining the target starting logical address.
[0112] It is understandable that, referring to Figure 5 , Figure 5 This is another flowchart of the address mapping processing method of the embodiment of the present application after step S430. After step S430, it also includes:
[0113] Step S510, when it is detected that the offset value of the first candidate address is greater than the first preset length, determining a second candidate logical address that is less than or equal to the read logical address from the first starting logical address in the second mapping table entry;
[0114] Step S520, calculating a second address offset value between the read logical address and each second candidate logical address;
[0115] Step S530, taking the second address offset value with the smallest value as the second candidate address offset value, and detecting the second candidate address offset value;
[0116] Step S540, when it is detected that the second candidate address offset value is less than the second preset length, the second candidate address offset value is used as the target address offset value, and the second candidate logical address corresponding to the target address offset value is used as the target starting logical address.
[0117] It is worth noting that when it is detected that the first candidate address offset value is greater than the first preset length, it can be determined that the target starting logic is not recorded by the first mapping table entry, so through steps S510 to S540, the target starting logic address is determined from the second mapping table entry.
[0118] Second, refer to Figure 6 , Figure 6: is a schematic diagram of the structure of the address mapping processing device of the embodiment of the present application. The address mapping processing device includes:
[0119] A first acquisition module 610 is used to acquire first write information of first write data from the first data write instruction when receiving the first data write instruction; the first write information includes a first start logical address and a first start physical address of the first write data;
[0120] A mapping table entry generating module 620, configured to generate a preset mapping table entry based on the first starting logical address and the first starting physical address; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address;
[0121] A second acquisition module 630 is used to acquire a read logical address from the data read instruction when receiving the data read instruction;
[0122] A calculation module 640, configured to determine a target starting logical address from first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculate a target address offset value between the target starting logical address and the read logical address;
[0123] A determination module 650, configured to determine a target start physical address from a preset mapping table entry based on the target start logical address;
[0124] The target address determination module 660 is used to obtain a target storage physical address corresponding to the read logical address based on the target starting physical address and the target address offset value.
[0125] The address mapping processing device is used to execute the address mapping processing method of the first aspect of the embodiment of the present application. When executing the method, when a first data write instruction is received, a preset mapping table entry is generated, and the preset mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address; when a data read instruction is received, the read logical address is obtained from the data read instruction; based on the read logical address, the target starting logical address is determined from the first starting logical addresses of multiple preset mapping table entries, and the target address offset value between the target starting logical address and the read logical address is calculated; based on the target starting logical address, the target starting physical address is determined from the preset mapping table entry, and based on the target starting physical address and the target address offset value, the target storage physical address corresponding to the read logical address is obtained. In this way, even if the read logical address is not equal to the target starting logical address, the target storage physical address corresponding to the read logical address can be determined, and only one preset mapping table entry is needed to map all physical storage addresses of the first write data, so that the physical space length mapped by each mapping table entry can be expanded, so that the mapping table in the cache space can meet most data read and write operation requirements, reduce the number of accesses to the flash memory when performing data read and write operations, and improve the efficiency of data read and write operations.
[0126] Reference Figure 7 , Figure 7 This is a schematic diagram of the structure of an electronic device according to an embodiment of the third aspect of the present application. The electronic device includes:
[0127] The processor 701 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;
[0128] The memory 702 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 702 can store an operating system and other applications. When the technical solution provided in the embodiments of this specification is implemented by software or firmware, the relevant program code is stored in the memory 702, and the processor 701 calls and executes the address mapping processing method of the embodiment of the present application;
[0129] Input / output interface 703, used to implement information input and output;
[0130] Communication interface 704, used to realize communication interaction between the device and other devices, which can be realized through wired mode (such as USB, network cable, etc.) or wireless mode (such as mobile network, WIFI, Bluetooth, etc.);
[0131] A bus 705 that transmits information between various components of the device (e.g., the processor 701, the memory 702, the input / output interface 703, and the communication interface 704);
[0132] The processor 701 , the memory 702 , the input / output interface 703 and the communication interface 704 are connected to each other in communication within the device via a bus 705 .
[0133] The fourth aspect of the present application is a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the address mapping processing method of any one of the first aspect embodiments.
[0134] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0135] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.
[0136] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.
[0137] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0138] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.
[0139] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0140] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the mapping relationship of the mapping objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next mapping objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.
[0141] In the several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0142] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0143] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.
[0144] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.
[0145] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.
[0146] The embodiments of the present application are described in detail above in conjunction with the accompanying drawings, but the present application is not limited to the above embodiments. Various changes can be made within the knowledge of ordinary technicians in the relevant technical field without departing from the purpose of the present application. In addition, the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
Claims
1. A method for processing address mapping, characterized in that: include: When receiving a first data write instruction, obtaining first write information of first write data from the first data write instruction; The first write information includes a first starting logical address and a first starting physical address of the first write data; Based on the first starting logical address and the first starting physical address, generating a preset mapping table entry; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address; When receiving a data read instruction, obtaining a read logical address from the data read instruction; Based on the read logical address, determine a target starting logical address from the first starting logical addresses of a plurality of the preset mapping table entries, and calculate a target address offset value between the target starting logical address and the read logical address; Determining a target starting physical address from the preset mapping table entry based on the target starting logical address; Based on the target starting physical address and the target address offset value, obtaining a target storage physical address corresponding to the read logical address; The first write information further includes a first data length of the first write data; the preset mapping table entry includes a first mapping table entry, and the physical space length mapped by the first mapping table entry is a first preset length; The generating a preset mapping table entry based on the first starting logical address and the first starting physical address includes: In the case where it is detected that the first starting logical address and the first data length meet a first preset condition, generating the first mapping table entry; the first preset condition is: the first data length is a multiple of the first preset length, and the first starting logical address is a multiple of the first preset length; The generating a preset mapping table entry based on the first starting logical address and the first starting physical address further includes: In the case where it is detected that the first starting logical address and the first data length do not meet the first preset condition, if a second data write instruction is received within a preset time length, second write information of the second write data is obtained from the second data write instruction; wherein the second write information includes a second starting logical address, a second starting physical address, and a second data length; Performing detection processing on the first write-in data and the second write-in data; In the case where it is detected that the first write data and the second write data meet a second preset condition, generating the first mapping table entry, and the first mapping table entry records a mapping relationship between the first starting physical address and the first starting logical address; The second preset condition is: the first starting logical address is a multiple of the first preset length, the physical storage addresses of the first write data and the second write data are continuous, the logical storage addresses of the first write data and the second write data are continuous, and the sum of the first data length and the second data length of the second write data is equal to the first preset length.
2. The method for processing address mapping according to claim 1, characterized in that: The step of determining a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculating a target address offset value between the target starting logical address and the read logical address comprises: Determine, from the first starting logical addresses of the plurality of preset mapping table entries, a candidate starting logical address that is less than or equal to the read logical address; Calculating an address offset value between the read logical address and each of the candidate start logical addresses; The target address offset value with the smallest value is determined from the address offset values, and the candidate starting logical address corresponding to the target address offset value is used as the target starting logical address.
3. The address mapping processing method according to claim 1, characterized in that: The preset mapping table entry also includes a second mapping table entry, the physical space length mapped by the second mapping table entry is a second preset length, and the first preset length is greater than the second preset length; After the first write data and the second write data are detected and processed, the method further includes: When it is detected that the first write data and the second write data do not meet the second preset condition, the second mapping table entry is generated; wherein the second mapping table entry records the mapping relationship between the first starting logical address and the first starting physical address, and the mapping relationship between the second starting logical address and the second starting physical address.
4. The method for processing address mapping according to claim 3, characterized in that: The step of determining a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculating a target address offset value between the target starting logical address and the read logical address comprises: Determine, from the first starting logical address in the first mapping table entry, a first candidate logical address that is less than or equal to the read logical address; Calculating a first address offset value between the read logical address and each of the first candidate logical addresses; Taking the first address offset value with the smallest value as the first candidate address offset value, and detecting the first candidate address offset value; When it is detected that the first candidate address offset value is smaller than the first preset length, the first candidate address offset value is used as the target address offset value, and the first candidate logical address corresponding to the target address offset value is used as the target starting logical address.
5. The method for processing address mapping according to claim 4, characterized in that: After detecting the first candidate address offset value, the method further includes: In the case where it is detected that the offset value of the first candidate address is greater than the first preset length, determining a second candidate logical address that is less than or equal to the read logical address from the first starting logical address in the second mapping table entry; Calculating a second address offset value between the read logical address and each of the second candidate logical addresses; Taking the second address offset value with the smallest value as the second candidate address offset value, and detecting the second candidate address offset value; When it is detected that the second candidate address offset value is smaller than the second preset length, the second candidate address offset value is used as the target address offset value, and the second candidate logical address corresponding to the target address offset value is used as the target starting logical address.
6. An address mapping processing device, characterized in that: include: A first acquisition module, configured to acquire first write information of first write data from the first data write instruction when receiving the first data write instruction; The first write information includes a first starting logical address and a first starting physical address of the first write data; A mapping table entry generating module, configured to generate a preset mapping table entry based on the first starting logical address and the first starting physical address; wherein the preset mapping table entry records a mapping relationship between the first starting logical address and the first starting physical address; A second acquisition module is used to acquire a read logical address from the data read instruction when receiving the data read instruction; a calculation module, configured to determine a target starting logical address from the first starting logical addresses of a plurality of preset mapping table entries based on the read logical address, and calculate a target address offset value between the target starting logical address and the read logical address; A determination module, configured to determine a target starting physical address from the preset mapping table entry based on the target starting logical address; A target address determination module, configured to obtain a target storage physical address corresponding to the read logical address based on the target starting physical address and the target address offset value; The first write information further includes a first data length of the first write data; the preset mapping table entry includes a first mapping table entry, and the physical space length mapped by the first mapping table entry is a first preset length; The generating a preset mapping table entry based on the first starting logical address and the first starting physical address includes: In the case where it is detected that the first starting logical address and the first data length meet a first preset condition, generating the first mapping table entry; the first preset condition is: the first data length is a multiple of the first preset length, and the first starting logical address is a multiple of the first preset length; The generating a preset mapping table entry based on the first starting logical address and the first starting physical address further includes: In the case where it is detected that the first starting logical address and the first data length do not meet the first preset condition, if a second data write instruction is received within a preset time length, second write information of the second write data is obtained from the second data write instruction; wherein the second write information includes a second starting logical address, a second starting physical address, and a second data length; Performing detection processing on the first write-in data and the second write-in data; In the case where it is detected that the first write data and the second write data meet a second preset condition, generating the first mapping table entry, and the first mapping table entry records a mapping relationship between the first starting physical address and the first starting logical address; The second preset condition is: the first starting logical address is a multiple of the first preset length, the physical storage addresses of the first write data and the second write data are continuous, the logical storage addresses of the first write data and the second write data are continuous, and the sum of the first data length and the second data length of the second write data is equal to the first preset length.
7. An electronic device, characterized in that: The electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the address mapping processing method according to any one of claims 1 to 5 when executing the computer program.
8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the address mapping processing method according to any one of claims 1 to 5 is implemented.