An interrupt processing module, method, bridge chip and multi-core processor system

Abstract

The present invention discloses an interrupt processing module, method, bridge chip and multi-core processor system, wherein the interrupt processing module includes an interrupt identification and classification unit, an interrupt merging unit and an interrupt request allocation unit, wherein: the interrupt identification and classification unit is configured to receive interrupt requests and determine the historical processing time of each interrupt request; the interrupt merging unit is configured to merge multiple interrupt requests according to the historical processing time and obtain one or more interrupt request groups; the interrupt request allocation unit is configured to obtain the current state of each processor, the current state includes the load state, and the interrupt request allocation unit allocates the interrupt request group to one or more of the multiple processors according to the current state of each of the processors, so that the load states of the multiple processors are balanced. The present invention can effectively solve the problem that the current interrupt processing method has excessive interference to the processor and the load imbalance of the processor.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an interrupt processing module, method, bridge chip and multi-core processor system. Background Art

[0002] Microprocessor technology is the core of computer systems, responsible for performing various computing and control tasks. Bridge chip design technology is an important technology for connecting different types of buses, which can realize data transmission and control between different types of buses. In modern computer systems, interrupt processing technology is a key technology that can handle interrupt requests from various devices (such as hard disks, network cards, graphics cards, etc.) and forward these requests to the central processing unit (CPU) for processing in a timely manner.

[0003] Most of the existing interrupt processing technologies use the method of directly requesting an interrupt from the CPU. Figure 1 The general PCIe device interrupt processing process is illustrated. First, the device prepares data and sends it through the PCIe (Peripheral Component Interconnect Express, a computer bus interface standard) interface. If the host system needs to be notified for further processing, the device sets an interrupt request in its internal interrupt request register (IRR). After receiving this request, the host system executes the interrupt service routine (ISR) and then clears the interrupt request flag in the IRR to complete the interrupt processing. In this way, the device can know that the interrupt has been processed. The whole process ensures the reliability of data transmission and the responsiveness of the system. In this way, the communication between the PCIe device and the CPU forms an efficient cycle, ensuring the responsiveness and reliability of the system. However, this interrupt processing technology has the following shortcomings: First, since the interrupt processing of the PCIe device is slow, if it is sent directly to the CPU, it may reduce the overall performance of the CPU and affect its efficiency in processing other tasks; second, this interrupt processing method has a large interference with the CPU.

[0004] In addition, some technologies use hardware interrupt merging, that is, multiple interrupt requests are merged into one request through a logic circuit and then sent to the CPU. This interrupt processing method can reduce interference to the CPU and improve the processing efficiency of the system. However, this interrupt processing technology has the following shortcomings: when processing interrupt requests of multi-core CPUs, it is impossible to achieve uniform distribution of interrupt requests, which may cause some CPU cores to be overloaded while other CPU cores are underloaded, thereby affecting the processing efficiency of the entire system.

[0005] The disclosure of the above background technology content is only used to assist in understanding the inventive concept and technical solution of the present invention. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0006] The object of the present invention is to provide an interrupt processing module, method, bridge chip and multi-core processor system, which can reduce interference to the processor, make full use of the idle cycle of the processor and improve the processing efficiency of the processor.

[0007] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0008] An interrupt processing module is applied to a multi-core processor, comprising an interrupt identification and classification unit, an interrupt merging unit and an interrupt request allocation unit, wherein:

[0009] The interrupt identification and classification unit is configured to receive interrupt requests and determine a historical processing time of each interrupt request;

[0010] The interrupt merging unit is configured to merge multiple interrupt requests according to historical processing time and obtain one or more interrupt request groups, each interrupt request group including one or more interrupt requests;

[0011] The interrupt request allocation unit is configured to obtain the current state of each processor, the current state including the load state, and the interrupt request allocation unit allocates the interrupt request group to one or more of the multiple processors according to the current state of each processor to balance the load states of the multiple processors.

[0012] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0013] Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ;

[0014] The interrupt requests whose historical processing time is within the same sub-time period are merged to obtain a corresponding interrupt request group.

[0015] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0016] Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ;

[0017] Multiple interrupt requests are merged according to the rule that historical processing times corresponding to different interrupt requests in each interrupt request group are in different sub-time periods.

[0018] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes merging multiple interrupt requests in the following manner:

[0019] Determine that each interrupt request group includes at most n interrupt requests, and calculate the historical processing time corresponding to the n interrupt requests and the n sub-time periods [T min , T1), [T1, T2),…, [T n , T max ]Merge multiple interrupt requests according to one-to-one corresponding rules.

[0020] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0021] Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ;

[0022] The interrupt requests whose historical processing time is in the same sub-time period are merged to obtain the corresponding interrupt request group, and the historical processing time is set in the sub-time period [T min , T1), [T1, T2),…, [T n , T max ] The maximum number of interrupt requests included in the segment request group is K1, K2, ..., Kn, where K1, K2, ..., Kn are all positive integers and K1≥K2≥...≥Kn≥1.

[0023] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes:

[0024] The maximum number of interrupt requests in each interrupt request group is the same; and / or,

[0025] The number of interrupt requests included in each interrupt request group is not less than 2 and not more than 10.

[0026] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions also includes: the maximum number of interrupt requests in each interrupt request group is 5.

[0027] Furthermore, any one of the above-mentioned technical solutions or a combination of multiple technical solutions further includes:

[0028] Prioritizing the allocation of the interrupt request group containing the largest number of interrupt requests to the processor for processing; and / or,

[0029] The interrupt request group with the smallest total historical processing time is preferentially assigned to the processor for processing, wherein the total historical processing time is the sum of the historical processing times corresponding to the various interrupt requests in the interrupt request group.

[0030] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the interrupt identification and classification unit includes a logic gate, a trigger, a system clock and a register, wherein the logic gate and the trigger are configured to monitor the signal on the PCIe bus in real time, identify and receive the interrupt request, and configure a corresponding identification code for each interrupt request, and the identification code has a one-to-one correspondence with the interrupt request;

[0031] The system clock is configured to record the completion time corresponding to each interrupt request and determine it as the historical processing time, and the historical processing time corresponds to the identification code one by one;

[0032] The register is configured to store each interrupt request and an identification code and a historical processing time of the interrupt request.

[0033] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the historical processing time of the interrupt request is determined by the following method:

[0034] If the interrupt request has no corresponding previous processing time record, the system clock time corresponding to when the interrupt request is received is used as the historical time record of the interrupt request;

[0035] If the interrupt request has one or more corresponding previous processing time records, the average of the multiple previous processing times is calculated, and the average is determined as the historical processing time of the interrupt request; or, the most recent previous processing time is determined as the historical processing time of the interrupt request.

[0036] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the load state of the processor includes an idle state, a full load state and a non-full load state, wherein the non-full load state is also a non-idle state;

[0037] The interrupt request allocating unit allocates the interrupt request group to one or more of the plurality of processors according to the load status of each of the processors, including:

[0038] not allocating the interrupt request group to a processor in a fully loaded state; and / or,

[0039] If there are one or more processors whose load status is not fully loaded and there is no processor in an idle state, the interrupt request group is allocated to one or more of the processors in the not fully loaded state; and / or,

[0040] If there are processors in an idle state and in a non-fully loaded state at the same time, the interrupt request group is preferentially allocated to the processor in the idle state.

[0041] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the number of interrupt request groups allocated to an idle processor at a single time does not exceed M, and the number of interrupt request groups allocated to a processor in a non-fully loaded state at a single time does not exceed P, where P≤M.

[0042] Further, according to any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the number of interrupt request groups allocated to an idle processor at a time is 1; and / or,

[0043] The number of interrupt request groups allocated at one time to a processor in a non-fully loaded state is 1.

[0044] According to another aspect of the present invention, the present invention provides an interrupt processing method, comprising the following steps:

[0045] Receive interrupt requests and determine the historical processing time corresponding to each interrupt request;

[0046] Merging multiple interrupt requests according to historical processing time and obtaining one or more interrupt request groups;

[0047] The current state of each processor is obtained, wherein the current state includes a load state. According to the current state of each processor, the interrupt request group is allocated to one or more of the multiple processors to balance the load states of the multiple processors.

[0048] According to another aspect of the present invention, the present invention provides a bridge chip, and the bridge chip includes an interrupt processing module as described in any one of the above technical solutions or a combination of multiple technical solutions.

[0049] According to another aspect of the present invention, the present invention provides a multi-core processor system, which includes multiple processors and an interrupt processing module as described in any one of the above technical solutions or a combination of multiple technical solutions, each of the processors is connected to a hardware device through the interrupt processing module, and the interrupt processing module receives interrupt requests sent by the hardware device and distributes them to one or more of the multiple processors.

[0050] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0051] a. The interrupt processing module provided by the present invention cooperates with the interrupt identification and classification unit, the interrupt merging unit and the interrupt request allocation unit to regularly merge the interrupt request groups and allocate them to the processor according to the set conditions, so as to achieve effective management of the interrupt requests of the low-speed PCIe device, reduce the interference to the CPU, realize intelligent scheduling, and improve the processing efficiency and processing capacity of the system;

[0052] b. The present invention evenly distributes the combined interrupt request group to the corresponding processors according to the real-time status and load information of each processor, thereby achieving uniform distribution of interrupt requests and avoiding the problem that some processors are overloaded while other processor cores are underloaded, thereby improving the processing efficiency of the entire system;

[0053] c. The present invention combines interrupt requests with similar historical processing times into one group, but sets different maximum numbers of interrupt requests for interrupt request groups corresponding to different sub-time periods, so that the sum of historical processing times of all interrupt requests corresponding to each interrupt request group in a full state is close. As a result, it is possible to simultaneously take into account multiple aspects such as instantaneous balancing of the load of each processor, reducing interference to the processor, making full use of the idle cycle of the processor, and improving the processing efficiency of the processor, thereby making the operation of the entire system more stable and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0055] Figure 1 A schematic diagram of the principle of the PCIe device interrupt processing process in the prior art;

[0056] Figure 2 A schematic diagram of a module of an interrupt identification and classification unit provided for an exemplary embodiment of the present invention;

[0057] Figure 3 A schematic diagram of the principle of an interrupt merging unit provided for an exemplary embodiment of the present invention;

[0058] Figure 4 A schematic diagram of the principle of an interrupt request allocation unit provided for an exemplary embodiment of the present invention;

[0059] Figure 5 A schematic diagram of a PCIe interrupt processing architecture provided for an exemplary embodiment of the present invention;

[0060] Figure 6 A flowchart of an interrupt processing method provided by an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0063] In one embodiment of the present invention, an interrupt processing module is provided. Figures 2 to 4 The interrupt processing module is applied to a multi-core processor, and includes an interrupt identification and classification unit, an interrupt merging unit, and an interrupt request allocation unit, wherein:

[0064] The interrupt identification and classification unit is configured to receive interrupt requests and determine a historical processing time of each interrupt request;

[0065] The interrupt merging unit is configured to merge multiple interrupt requests according to historical processing time and obtain one or more interrupt request groups;

[0066] The interrupt request allocation unit is configured to obtain the current state of each processor, the current state including the load state, and the interrupt request allocation unit allocates the interrupt request group to one or more of the multiple processors according to the current state of each processor to balance the load states of the multiple processors.

[0067] In one embodiment of the present invention, Figure 2 As shown, the interrupt identification and classification unit and the interrupt processing module include logic gates, triggers, system clocks and registers, wherein the logic gates and triggers are configured to monitor the signals on the PCIe bus in real time, identify and receive interrupt requests from source devices, and configure corresponding identification codes for each interrupt request. In this embodiment, a unique identification code is configured for an interrupt request, through which the entire processing process of the interrupt request and the time taken to complete the processing of the interrupt request can be tracked. The present invention uses the identification code to distinguish different interrupt requests, which helps to accurately identify which specific source device or component the interrupt request comes from, avoiding confusion and erroneous processing.

[0068] The system clock is configured to record the completion time corresponding to each interrupt request and determine it as the historical processing time, and the historical processing time corresponds to the identification code one by one. Specifically, the historical processing time of the interrupt request can be determined in the following manner:

[0069] If the interrupt request has no corresponding previous processing time record, the system clock time corresponding to when the interrupt request is received is used as the historical time record of the interrupt request;

[0070] If the interrupt request has one or more corresponding previous processing time records, the average of the previous processing times is calculated and the average is determined as the historical processing time of the interrupt request; or the most recent previous processing time is determined as the historical processing time of the interrupt request. Preferably, the average of the most recent processing times corresponding to the interrupt request is determined as the historical processing time. This historical processing time determination method is more in line with the latest operating status of the system and is less affected by a single fluctuation.

[0071] The information such as the identification code and historical processing time corresponding to the interrupt request follows the preset coding rules and is stored through a dedicated hardware register, which can realize efficient interrupt identification and classification. For example, an 8-bit binary number is used to represent the identification code corresponding to the interrupt request signal.

[0072] like Figure 3 As shown, the interrupt merging unit is a customized hardware logic circuit, which can merge multiple interrupt requests that meet the requirements into one group according to preset rules. Sending multiple interrupt requests to the processor independently is transformed into an interrupt request group including multiple interrupt requests to the processor at one time, thereby reducing the number of requests sent to the CPU and reducing unnecessary interference to the CPU.

[0073] In this embodiment, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0074] Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum value of the historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T maxThe interrupt requests with historical processing time in the same sub-time period are merged to obtain corresponding interrupt request groups, and the maximum number of interrupt requests in each interrupt request group is the same. Preferably, the number of interrupt requests included in each interrupt request group is not less than 2 and not more than 10. More preferably, the maximum number of interrupt requests in each interrupt request group is 5, that is, each interrupt request group contains at most 5 interrupt requests.

[0075] See also Figure 4 The interrupt request allocator is provided in the interrupt request allocator, which receives the combined interrupt request groups and dynamically adjusts the interrupt request allocation based on the core state perception mechanism. The combined interrupt request groups are evenly allocated to multiple CPU cores according to the real-time state and load information of the CPU cores, i.e., each processor.

[0076] By acquiring the working state of each processor, the load state of each processor is determined. In the present invention, the load state of the processor is divided into an idle state, a full load state and a non-full load state. In a specific embodiment of the present invention, the idle state indicates that the processor is not in a working state; the non-full load state indicates that the processor is in a working state and the load rate is less than 100%; the full load state indicates that the processor is in a working state and the load rate reaches 100%. More preferably, in a specific embodiment of the present invention, the idle state indicates that the processor is in a state where the load rate is lower than a first preset value, for example, the first preset value is 10%, then the idle state indicates that the processor is in a state where the load rate is lower than 10%; the non-full load state indicates that the processor is in a state where the load rate is between the first preset value and the second preset value, the second preset value is greater than the first preset value, preferably, the second preset value is 40%-70%; the full load state indicates that the processor load rate is greater than the second threshold load state.

[0077] In this embodiment, each of the interrupt request groups is dynamically allocated to one or more of the multiple processors according to the following rules:

[0078] (1) not allocating the interrupt request group to a processor in a fully loaded state;

[0079] (2) If there are one or more processors whose load status is not fully loaded and there is no processor in an idle state, a full interrupt request group is allocated to one or more of the processors in the non-fully loaded state, and a non-full interrupt request group is not allocated to each processor; wherein a full interrupt request group is an interrupt request group in which the number of interrupt requests contained in the interrupt request group reaches a preset upper limit value of the number of interrupt requests combined in each group; for example, it is stipulated that the number of interrupt requests included in each interrupt request group is at most 5, then an interrupt request group including 5 interrupt requests is the full interrupt request group;

[0080] (3) If there are processors in an idle state and in a non-fully loaded state at the same time, the interrupt request group is preferentially assigned to the processor in the idle state, and the interrupt request group containing the largest number of interrupt requests is preferentially assigned to the processor in the idle state;

[0081] (4) preferentially allocating the interrupt request group with the smallest total historical processing time to the processor for processing, wherein the total historical processing time is the sum of the historical processing times corresponding to the individual interrupt requests in the interrupt request group;

[0082] (5) The number of interrupt request groups allocated to an idle processor at a time does not exceed M, and the number of interrupt request groups allocated to a processor in a non-fully loaded state at a time does not exceed P, where P ≤ M; preferably, the number of interrupt request groups allocated to an idle processor at a time is 1; and the number of interrupt request groups allocated to a processor in a non-fully loaded state at a time is 1.

[0083] The following is a specific example of an example of a method for processing an interrupt request by an interrupt processing module provided by the present invention:

[0084] Assumption scenario: There are 10 interrupt request signals, and their historical processing times are shown in Table 1.

[0085]

[0086] Interrupt request merging rules: Each group contains a maximum of 5 interrupt requests; preset sub-time periods [10ms, 12ms), [12ms, 15ms), [15ms, 18ms], and merge the interrupt requests with historical processing time in the same sub-time period to obtain the corresponding interrupt request group.

[0087] Interrupt request merging results:

[0088] Interrupt request group 1: signal 1, signal 5, signal 7, signal 8, signal 10; (the historical processing time of this group is 10ms);

[0089] Interrupt request group 2: signal 3, signal 6; (the historical processing time of this group is 10ms and 11ms. Since interrupt group 1 is full, a new group is added here);

[0090] Interrupt request group 3: signal 2, signal 9; (the historical processing time of this group is 12ms);

[0091] Interrupt request group 4: signal 4; (the historical processing time of this group is 15ms).

[0092] Interrupt request allocation:

[0093] If there is an idle processor, interrupt request group 1 can be sent to the processor immediately. If there are other processors in the idle state, interrupt request group 2 will also be sent to an idle processor, that is, as long as there is an idle processor, even if the current interrupt request group has not been merged to reach the full state, it will be sent to the idle processor immediately, and the priority of sending to the idle processor is that the larger the number, the higher the number. In the case of the same number, the shorter the historical processing time, the higher the historical processing time.

[0094] If all current processors are in full load state, the full interrupt request groups enter the waiting mode, and the underfull interrupt request groups are further merged.

[0095] If there is only a processor that is not fully loaded, the full interrupt request group 1 is sent to the processor with the lowest load rate, and the under-full interrupt request groups 2, 3, and 4 are not sent to the processor.

[0096] The interrupt request group allocation method provided in this embodiment can immediately send one or more current interrupt request groups to the processor in the idle state if the processor is in an idle state, without waiting for the merged group to be full, so as to make full use of the idle cycle of the processor. The interrupt request allocation unit will give priority to interrupt groups with a large number or interrupt groups with short interrupt time according to the number of interrupt requests in the interrupt request group or the time required for the interrupt, that is, the historical processing time. Based on this information, the merging unit regularly merges the interrupt requests and sends the requests according to the CPU state to reduce unnecessary interference to the CPU. This embodiment merges interrupt requests with similar historical processing times into a group and sends them to one processor, so that the processor can process multiple interrupt requests in parallel and complete the processing of each interrupt request in a close time, and enter the idle state again, thereby improving the processing efficiency of the processor.

[0097] In summary, the interrupt processing module provided by the present invention can achieve effective management of low-speed PCIe device interrupt requests through the coordinated work of the interrupt identification and classification unit, the interrupt merging unit and the interrupt request allocation unit, thereby reducing interference to the CPU and improving the processing efficiency of the system.

[0098] In another embodiment of the present invention, the interrupt processing module provided processes the interrupt request differently from the above embodiment in that the rules for merging multiple interrupt requests are different. In this embodiment, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0099] Predetermine the minimum time T to complete the interrupt request min and the maximum time T max , and the time period [T min , T max ] is divided into several sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max .

[0100] Multiple interrupt requests are merged according to the rule that historical processing times corresponding to different interrupt requests in each interrupt request group are in different sub-time periods.

[0101] Preferably, it is determined that each interrupt request group includes at most n interrupt requests, and the historical processing time corresponding to the n interrupt requests and the n sub-time periods [T min , T1), [T1, T2),…, [T n , T max ]Merge multiple interrupt requests according to one-to-one corresponding rules.

[0102] For example, five sub-time periods are determined as [2ms, 5ms), [5ms, 8ms), [8ms, 11ms], [11ms, 14ms), and [14ms, 17ms]. Each interrupt request group contains at most five interrupt requests, and any two historical processing time records combined in one interrupt request group do not fall within the same sub-time period.

[0103] The interrupt request merging method provided in this embodiment can improve the instantaneous balance of the load of each processor compared to the interrupt request merging provided in the above embodiment. Specifically, for example, according to the above embodiment, the interrupt requests with similar historical processing time are merged into a group. The total time required for the first group of 5 interrupt requests may be 25ms (5ms each, 5 in number), and the total time required for the second group of interrupt requests may be 75ms (15ms each, 5 in number). The first group of interrupt requests is given to the idle first processor, and the second group is given to the idle second processor. This will cause an instantaneous imbalance in the load of the first processor and the second processor. The interrupt request merging method provided in this embodiment can improve the problem of instantaneous imbalance in the load of each processor.

[0104] It should be noted that, although from this simple example, the processing time of the interrupt requests of the first group and the second group is quite different, assigning them to different CPUs may cause load imbalance in the short term. However, the operation of the system is a dynamic process. Over a longer time frame, subsequent interrupt request grouping and allocation may gradually balance the load of each CPU. The core state perception mechanism provided by the above embodiment will dynamically adjust the allocation of interrupt requests according to the real-time state and load information of the CPU core. Even if the above-mentioned momentary imbalance occurs, the subsequent allocation mechanism may still be adjusted to achieve long-term load balancing.

[0105] In another embodiment of the present invention, the interrupt processing module provided processes the interrupt request differently from the above embodiments in that another interrupt request merging method is adopted. In this embodiment, the interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner:

[0106] Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum value of the historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max .

[0107] The interrupt requests whose historical processing time is in the same sub-time period are merged to obtain the corresponding interrupt request group, and the historical processing time is set in the sub-time period [T min , T1), [T1, T2),…, [T n , T max] The maximum number of interrupt requests included in the segmented request group is K1, K2, ..., Kn, respectively, wherein K1, K2, ..., Kn are all positive integers, and K1 ≥ K2 ≥ ... ≥ Kn ≥ 1. Specifically, in this embodiment, the interrupt requests with comparable historical processing times are also combined into one group, but the full numbers of interrupt request groups corresponding to different sub-time periods are set to be different, so that the sum of the historical processing times of all interrupt requests corresponding to each interrupt request group in the full state is close, thereby being able to simultaneously take into account multiple aspects such as instantaneous balancing of the load of each processor, reducing interference to the processor, making full use of the idle cycles of the processor, and improving the processing efficiency of the processor.

[0108] In other embodiments of the present application, the load state of the processor may be divided into a non-load state and a load state, and an interrupt request group is only allocated to the processor in the non-load state, and no interrupt request group is allocated to the processor in the load state.

[0109] In other embodiments of the present application, a priority level can also be configured for each interrupt request, and multiple interrupt requests can be merged according to the priority level and historical processing time, and the corresponding priority level can also be configured for the merged allocated interrupt request group; when allocating the interrupt request group, in addition to considering the number of interrupt requests included in the interrupt request group and the historical processing time corresponding to the interrupt request, the priority level of the interrupt request group is also considered, and the interrupt request group with the highest priority is allocated first, followed by the full interrupt request group, and then the interrupt request group with a large number is allocated.

[0110] For example, in one embodiment of the present invention, the priority level of each interrupt request is configured to be high or low accordingly. In the subsequent interrupt request merging process, all high-level interrupt requests are merged according to the merging method described in any of the above embodiments, and all low-level interrupt requests are merged according to the merging method described in any of the above embodiments. The level of the interrupt request group obtained by merging the high-level interrupt requests corresponds to the high level, and the level of the interrupt request group obtained by merging the low-level interrupt requests corresponds to the low level. In the subsequent interrupt request allocation process, all high-level interrupt request groups are allocated first before the low-level interrupt request groups are allocated.

[0111] In one embodiment of the present invention, an interrupt processing method is provided, such as Figure 6 As shown, the interrupt processing method includes the following steps:

[0112] Receive interrupt requests and determine the historical processing time corresponding to each interrupt request;

[0113] Merging multiple interrupt requests according to historical processing time and obtaining one or more interrupt request groups;

[0114] The current state of each processor is obtained, wherein the current state includes a load state. According to the current state of each processor, the interrupt request group is allocated to one or more of the multiple processors to balance the load states of the multiple processors.

[0115] Due to the advanced nature of the technical solution, it can be widely used in application fields such as computer system interrupt processing, microprocessor technology, and bridge chip design. With the development of computer technology, the interrupt requests of various devices (such as hard disks, network cards, graphics cards, etc.) are increasing, and the demand for interrupt processing technology is also increasing. The comprehensive interrupt processing module proposed by the present invention can effectively solve the problems existing in the prior art, such as the large amount of interrupt data of low-speed PCIe devices causing excessive CPU load, the hardware interrupt merging method cannot be intelligently scheduled according to the actual CPU load, and the multi-core CPU interrupt requests cannot be evenly distributed. Therefore, the present invention has a great market demand and is expected to be widely used in the fields of computer system interrupt processing, microprocessor technology, and bridge chip design.

[0116] In one embodiment of the present invention, a bridge sheet is provided, such as Figure 5 As shown, the bridge chip includes an interrupt processing module as described in any of the above embodiments. Figure 5 The integrated interrupt processing module shown, when the low-speed PCIe device sends interrupt data, it is directly sent to the integrated interrupt processing module. The interrupt data of the low-speed PCle device is first executed in the integrated interrupt processing module, and the result is sent to the CPU after execution. This can optimize interrupt processing, reduce interference to the CPU, and improve the processing efficiency of the system.

[0117] In addition, the technical solution combines multiple interrupt requests of low-speed PCIe devices into one interrupt request group for processing, which reduces interference to the CPU, improves the efficiency of sorting, and thus improves the processing capacity of the system. In general, compared with the prior art, the present invention can not only effectively manage and process the interrupt requests of low-speed PCIe devices, reduce interference to the CPU, and improve the processing efficiency of the system, but also realizes the optimized processing, regular scheduling and balanced distribution of interrupt requests, making the operation of the entire system more stable and efficient.

[0118] In one embodiment of the present invention, a multi-core processor system is provided, which includes multiple processors and an interrupt processing module as described in any one of the above embodiments, each of the processors is connected to a hardware device through the interrupt processing module, and the interrupt processing module receives interrupt requests sent by the hardware device and distributes them to one or more of the multiple processors.

[0119] It should be noted that the interrupt handling method embodiment, bridge chip embodiment and multi-core processor system embodiment provided by the present invention are the same as the inventive concept of the above-mentioned interrupt handling module embodiment, and the entire content of the interrupt handling module embodiment is incorporated into the interrupt handling method embodiment, bridge chip embodiment and multi-core processor system embodiment by introduction.

[0120] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0121] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. An interrupt processing module, characterized in that: The interrupt processing module is applied to a multi-core processor, and includes an interrupt identification and classification unit, an interrupt merging unit and an interrupt request allocation unit, wherein: The interrupt identification and classification unit is configured to receive an interrupt request and determine a historical processing time of each interrupt request, wherein the historical processing time is a historical duration of interrupt processing; The interrupt merging unit is configured to merge multiple interrupt requests according to historical processing time and obtain one or more interrupt request groups, each interrupt request group including one or more interrupt requests; The interrupt request allocation unit is configured to obtain the current state of each processor, the current state including the load state, and the interrupt request allocation unit allocates the interrupt request group to one or more of the multiple processors according to the current state of each processor to balance the load states of the multiple processors.

2. The interrupt processing module according to claim 1, characterized in that: The interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner: Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ; The interrupt requests whose historical processing time is within the same sub-time period are merged to obtain a corresponding interrupt request group.

3. The interrupt processing module according to claim 1, characterized in that: The interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner: Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum value of the historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ; Multiple interrupt requests are merged according to the rule that historical processing times corresponding to different interrupt requests in each interrupt request group are in different sub-time periods.

4. The interrupt processing module according to claim 3, characterized in that: It also includes merging multiple interrupt requests in the following ways: Determine that each interrupt request group includes at most n interrupt requests, and calculate the historical processing time corresponding to the n interrupt requests and the n sub-time periods [T min , T1), [T1, T2),…, [T n , T max ]Merge multiple interrupt requests according to one-to-one corresponding rules.

5. The interrupt processing module according to claim 1, characterized in that: The interrupt merging unit merges multiple interrupt requests according to the historical processing time in the following manner: Predetermine a number of sub-time periods [T min , T1), [T1, T2),…, [T n , T max ], where T min Not greater than the minimum historical processing time corresponding to each interrupt request, T max Not less than the maximum value of the historical processing time corresponding to each interrupt request, 0≤T min <T1<T2<……<T n <T max ; The interrupt requests whose historical processing time is in the same sub-time period are merged to obtain the corresponding interrupt request group, and the historical processing time is set in the sub-time period [T min , T1), [T1, T2),…, [T n , T max ] The maximum number of interrupt requests included in the segment request group is K1, K2, ..., Kn, where K1, K2, ..., Kn are all positive integers and K1≥K2≥...≥Kn≥1.

6. The interrupt processing module according to claim 1, characterized in that: Also includes: The maximum number of interrupt requests in each interrupt request group is the same; and / or, The number of interrupt requests included in each interrupt request group is not less than 2 and not more than 10.

7. The interrupt processing module according to claim 6, characterized in that: Also includes: The maximum number of interrupt requests in each interrupt request group is 5.

8. The interrupt processing module according to claim 1, characterized in that: Also includes: Prioritizing the allocation of the interrupt request group containing the largest number of interrupt requests to the processor for processing; and / or, The interrupt request group with the smallest total historical processing time is preferentially assigned to the processor for processing, wherein the total historical processing time is the sum of the historical processing times corresponding to the various interrupt requests in the interrupt request group.

9. The interrupt processing module according to claim 1, characterized in that: The interrupt identification and classification unit includes a logic gate, a trigger, a system clock and a register, wherein the logic gate and the trigger are configured to monitor the signal on the PCIe bus in real time, identify and receive an interrupt request, and configure a corresponding identification code for each interrupt request, and the identification code has a one-to-one correspondence with the interrupt request; The system clock is configured to record the completion time corresponding to each interrupt request and determine it as the historical processing time, and the historical processing time corresponds to the identification code one by one; The register is configured to store each interrupt request and an identification code and a historical processing time of the interrupt request.

10. The interrupt processing module according to claim 9, characterized in that: The historical processing time of the interrupt request is determined by: If the interrupt request has no corresponding previous processing time record, the system clock time corresponding to when the interrupt request is received is used as the historical time record of the interrupt request; If the interrupt request has one or more corresponding previous processing time records, the average of the multiple previous processing times is calculated, and the average is determined as the historical processing time of the interrupt request; or, the most recent previous processing time is determined as the historical processing time of the interrupt request.

11. The interrupt processing module according to claim 1, characterized in that: The load state of the processor includes an idle state, a full load state and a non-full load state, wherein the non-full load state is also a non-idle state; The interrupt request allocating unit allocates the interrupt request group to one or more of the plurality of processors according to the load status of each of the processors, including: not allocating the interrupt request group to a processor in a fully loaded state; and / or, If there are one or more processors whose load status is not fully loaded and there is no processor in an idle state, the interrupt request group is allocated to one or more of the processors in the not fully loaded state; and / or, If there are processors in an idle state and in a non-fully loaded state at the same time, the interrupt request group is preferentially allocated to the processor in the idle state.

12. The interrupt processing module according to claim 11, characterized in that: The number of interrupt request groups allocated to an idle processor at a single time does not exceed M, and the number of interrupt request groups allocated to a processor in a non-fully loaded state at a single time does not exceed P, where P≤M.

13. The interrupt processing module according to claim 12, characterized in that: The number of interrupt request groups allocated to an idle processor at a time is 1; and / or, The number of interrupt request groups allocated at one time to a processor in a non-fully loaded state is 1.

14. An interrupt processing method, characterized in that: The following steps are involved: Receive an interrupt request and determine a historical processing time corresponding to each interrupt request, where the historical processing time is a historical duration of interrupt processing; Merging multiple interrupt requests according to historical processing time and obtaining one or more interrupt request groups; The current state of each processor is obtained, wherein the current state includes a load state. According to the current state of each processor, the interrupt request group is allocated to one or more of the multiple processors to balance the load states of the multiple processors.

15. A bridge sheet, characterized in that: The bridge chip includes an interrupt processing module as described in any one of claims 1-13.

16. A multi-core processor system, characterized in that: It includes multiple processors and an interrupt processing module as described in any one of claims 1-13, each of the processors is connected to a hardware device through the interrupt processing module, and the interrupt processing module receives an interrupt request sent by the hardware device and distributes it to one or more of the multiple processors.

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