Filler Insertion Method, Computer Device, and Storage Medium

Abstract

A method for inserting fillers, a computer device, and a storage medium provided by the present application. The method includes: obtaining a chip design layout; determining any row according to the chip design layout, and determining any gap and the first width of the gap in the row; screening in a preset first set according to the first width to generate a second set; wherein the first set is a set including attribute data of at least one filler; arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme; performing rule checking on at least one insertion scheme according to a preset rule table; and determining a target scheme corresponding to the gap in at least one insertion scheme according to the check result, so as to complete the insertion of the filler for the gap through the target scheme.

Description

Technical Field

[0001] This application relates to the technical field of chip layout planning, and particularly relates to a filler insertion method, a computer device, and a storage medium. Background Art

[0002] Electronic Design Automation (EDA) refers to a design method that uses computer-aided design (CAD) software to complete the functional design, synthesis, verification, physical design (including layout, routing, layout, design rule checking, etc.) of very large scale integrated (VLSI) chips.

[0003] Among them, after the layout of functional modules is completed, fillers are generally inserted into the gaps between functional modules. However, in related technologies, the filler addition method usually simplifies the problem into row-based filler addition, treats blank gaps of different widths as sub-structures, and thus constructs a dynamic programming model to solve this problem. This method can only consider fillers within a row and between adjacent rows, but after the fillers are added, it will cause fillers in other rows or functional modules as a whole to violate multiple design constraints. Usually, post-processing needs to be added to solve these design violations, which seriously affects the overall layout efficiency and reduces the user experience. Summary of the Invention

[0004] In view of this, this application proposes a filler insertion method, a computer device, and a storage medium to solve or partially solve the above problems.

[0005] Based on the above purpose, in a first aspect, this application provides a filler insertion method, including:

[0006] Obtain a chip design layout;

[0007] Determine any row according to the chip design layout, and determine any gap and the first width of the gap in the row;

[0008] Filter in a preset first set according to the first width to generate a second set; where the first set is a set including attribute data of at least one filler;

[0009] Arrange and combine the fillers in the second set according to the first width to generate at least one insertion scheme;

[0010] Check the rules of the at least one insertion scheme according to a preset rule table;

[0011] According to the inspection result, determine the target scheme corresponding to the gap in the at least one insertion scheme, so as to complete the filler insertion of the gap through the target scheme.

[0012] In a second aspect of the present application, a computer device is provided, including one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to the first aspect.

[0013] In a third aspect of the present application, a non-volatile computer-readable storage medium containing a computer program is provided. When the computer program is executed by one or more processors, the processors are caused to execute the method according to the first aspect.

[0014] As can be seen from the above, the present application provides a filler insertion method, a computer device, and a storage medium. In the present application, for any gap in each row of the chip design layout, fillers that can be filled are first screened according to the width, and the screened set of fillers is arranged to generate multiple insertion schemes that meet the filling conditions. Then, rule checks are directly performed on each insertion scheme in sequence to determine the insertion scheme. Since corresponding rule checks are directly performed each time, further adjustment is not required through post-processing after the overall filler insertion is completed, ultimately improving the overall layout efficiency and enhancing the user experience. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] To more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0016] Figure 1 It shows a schematic diagram of the hardware structure of an exemplary computer device provided by an embodiment of the present application.

[0017] Figure 2 It shows a schematic diagram of the basic structure of an EDA tool according to an embodiment of the present application.

[0018] Figure 3 It shows a schematic diagram of the basic execution flow of a calculation command of an EDA tool according to an embodiment of the present application.

[0019] Figure 4 It shows a schematic diagram of the flow of an exemplary method provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] To make the objectives, technical solutions, and advantages of this specification more clear and understandable, the following further elaborates on this specification in detail with reference to specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of this application should have the ordinary meanings understood by those of ordinary skill in the field to which this application belongs. The "first", "second", and similar terms used in the embodiments of this application do not denote any order, quantity, or importance, but are only used to distinguish different components. Words such as "including" or "comprising" mean that the elements, objects, or method steps appearing before this word cover the elements, objects, or method steps listed after this word and their equivalents, without excluding other elements, objects, or method steps. "Connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0022] Figure 1 FIG. 1 shows a schematic structural diagram of a computer device 100 provided by an embodiment of this application. The computer device 100 may include: a processor 102, a memory 104, a network interface 106, a peripheral interface 108, and a bus 110. Among them, the processor 102, the memory 104, the network interface 106, and the peripheral interface 108 are communicatively connected to each other inside the device through the bus 110.

[0023] The processor 102 may be a central processing unit (CPU), a graphics processor, a neural network processor (NPU), a microcontroller (MCU), a programmable logic device, a digital signal processor (DSP), an application specific integrated circuit (ASIC), or one or more integrated circuits. The processor 102 may be used to execute functions related to the technologies described in this application. In some embodiments, the processor 102 may further include multiple processors integrated as a single logical component. As Figure 1 shown, the processor 102 may include multiple processors 102a, 102b, and 102c.

[0024] The memory 104 may be configured to store data (e.g., instruction sets, computer code, intermediate data, etc.). For example, as Figure 1As shown, the stored data may include program instructions (e.g., program instructions for implementing the technical solution of the present application) and data to be processed. The processor 102 can also access the stored program instructions and data, and execute the program instructions to operate on the data to be processed. The memory 104 may include a volatile storage device or a non-volatile storage device. In some embodiments, the memory 104 may include a random access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard disk, a solid state drive (SSD), a flash memory, a memory stick, etc.

[0025] The network interface 106 can be configured to provide communication with other external devices to the computer device 100 via a network. The network can be any wired or wireless network capable of transmitting and receiving data. For example, the network can be a wired network, a local wireless network (e.g., Bluetooth, WiFi, near field communication (NFC), etc.), a cellular network, the Internet, or a combination of the above. It can be understood that the type of the network is not limited to the above specific examples. In some embodiments, the network interface 106 may include any combination of any number of network interface controllers (NICs), radio frequency modules, transceivers, modems, routers, gateways, adapters, cellular network chips, etc.

[0026] The peripheral interface 108 can be configured to connect the computer device 100 to one or more peripheral devices to enable information input and output. For example, the peripheral devices may include input devices such as a keyboard, a mouse, a touchpad, a touch screen, a microphone, various sensors, etc. and output devices such as a display, a speaker, a vibrator, an indicator light, etc.

[0027] The bus 110 can be configured to transfer information between the various components of the computer device 100 (e.g., the processor 102, the memory 104, the network interface 106, and the peripheral interface 108), such as an internal bus (e.g., a processor-memory bus), an external bus (USB port, PCI-E bus), etc.

[0028] It should be noted that although the above devices only show the processor 102, the memory 104, the network interface 106, the peripheral interface 108, and the bus 110, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, those skilled in the art can understand that the above devices may also only include the components necessary for implementing the solution of the embodiments of the present application, and do not necessarily include all the components shown in the figure.

[0029] Figure 2 Shows a schematic diagram of the basic structure of the EDA tool 200 according to an embodiment of the present application.

[0030] As Figure 2As shown, the part above the dashed line is the user part; the part below the dashed line is the EDA tool 200, and the EDA tool 200 can be implemented by Figure 1 the device 100 shown. In some embodiments, the EDA tool 200 can be implemented as EDA software. More specifically, the EDA tool 200 can be software for performing placement and routing based on chip design. The simulation tool 200 can include a Tcl command (or graphical / window interface) module 204, various calculation modules (such as a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc.), and a database system 212. The user 202 can operate the EDA tool 200 by inputting relevant commands in the Tcl command (or graphical / window interface) module 204.

[0031] The Tcl command module 204 mainly functions as message passing or command passing. The Tcl command module 204 can read the instructions input by the user 202 to the simulation tool 200, and can, according to the specific content of the instructions, allocate and transfer them to the corresponding calculation modules to execute specific tasks.

[0032] According to different calculation tasks, the various calculation modules can be divided into, for example, a Place calculation module 206, a Route calculation module 208, an Optimization calculation module 210, etc. The Place calculation module 206 can be used to calculate a reasonable placement position for all components, the Route calculation module 208 can be used to calculate a reasonable wire connection method between the components, and the Optimization calculation module 210 can be used to optimize the placement positions and wire connection methods between the components. The calculation processes of these calculation modules can be performed, for example, Figure 1 in the processor 102.

[0033] The database system 212 can be used to comprehensively record and store all information of the chip to be simulated or designed (such as position, orientation, size, structure, wire connection method, etc.). This information can be stored, for example, Figure 1 in the memory 104.

[0034] Figure 3 shows a basic execution flow 300 of a calculation command of the EDA tool 200 according to an embodiment of the present application. As Figure 3As shown, in step 302, user 202 can issue a command (e.g., do_place command) to the EDA tool 200 through the command interface or graphical user interface (GUI) provided by the Tcl command module 204. Then, in step 304, the Tcl command module 204 parses this command and distributes it to the corresponding computing module (e.g., Place computing module 206). In step 306, each computing module performs the specific calculations required. During this period, as shown in step 308, each computing module needs to (frequently, repeatedly) retrieve data from the database system 212 for calculations. After the calculations are completed, as shown in step 310, each computing module can write the calculation results to the database system 212 and return the calculation results to the Tcl command module 204. In step 312, the Tcl command module 204 returns the calculation results to the user 202 through the command interface or graphical user interface (GUI), and the processing process of the EDA tool 200 for a calculation command ends. In step 314, the user can evaluate according to the calculation results and then determine the next plan.

[0035] In the integrated circuit design of related technologies, filler insertion is an important step, and its main purpose is to optimize the layout of the chip to meet specific design rules and limitations. The following are several main reasons for filler insertion: (1) Improve layout compatibility: The addition of fill cells helps ensure that the design complies with various physical and process rules in the manufacturing process, such as lithography, etching, etc., thereby improving layout compatibility. (2) Reduce routing delay: By adding an appropriate number of fill cells in the chip layout, the length of the routing path can be reduced, thereby reducing the delay of signal transmission and improving the performance of the chip. (3) Optimize power consumption and electrical characteristics: The addition of fill cells can improve the electrical characteristics of the chip, such as capacitance and resistance, etc., thereby optimizing power consumption and signal integrity. (4) Improve thermal management: Fill cells help optimize the thermal management of the chip. By increasing the surface area and improving the heat dissipation efficiency, the operating temperature of the chip is reduced, and the service life of the chip is extended. (5) Comply with design rules: In chip design, the addition of fill cells helps ensure that the design complies with specific design rules and standards, such as the requirements of the foundry. (6) Improve electromagnetic compatibility: The reasonable layout of fill cells can reduce electromagnetic interference and noise, improve the electromagnetic compatibility of the chip, and reduce signal interference in the system. In summary, adding fill cells to the design can improve the performance, reliability, and manufacturing feasibility of the chip in all aspects, thus playing an important role in integrated circuit design.

[0036] Afterwards, as described in the background art, the filler addition method usually simplifies the problem into adding filler units based on rows, treating blank gaps of different widths as substructures, and thus constructing a dynamic programming model to solve this problem. Such a setting will encounter the problems described in the background art, and this method only aims to fill the blank gaps of the chip without considering the types of filler units. For example, it is slightly insufficient in the case of pursuing adding more decoupling circuit units to meet power integrity requirements. As the chip develops to advanced process nodes, this method cannot be well extended to meet more and more complex design constraints, and its scalability is poor.

[0037] In view of this, the present application proposes a filler insertion scheme. In the present application, for any gap in each row of the chip design layout, fillers that can be filled are first screened according to the width, and the screened filler set is arranged to generate multiple insertion schemes that meet the filling conditions. Then, the rule check is directly performed on each insertion scheme in turn to complete the determination of the insertion scheme. Since the corresponding rule check is directly performed each time, further adjustment is no longer required through post-processing after the filler insertion is completed as a whole, ultimately improving the overall layout efficiency and enhancing the user experience.

[0038] Figure 4 The flowchart of an exemplary method 400 provided by an embodiment of the present application is shown. The method 400 can be implemented by Figure 1 a computer device 100 and can be implemented as Figure 2 a part of the functions of an EDA tool 200. As Figure 4 shown, the method 400 may further include the following steps.

[0039] Step 402, obtain the chip design layout.

[0040] Generally, a chip design layout includes each layer structure for chip processing, specifically transistor layout, wiring, routing, channel via interlayer connection positions, and so on. Based on this chip design layout, a chip processing service provider can directly operate and carry out batch processing production of the chip. Further, the chip design layout itself is drawn step by step, accompanied by various optimizations, and finally the entire chip design layout is completed. In the initial stage of the chip design layout, it may only indicate the functional information of the layers, such as a certain layer is a routing layer, a certain layer is an insulating layer, etc.; or only various functional elements are set, indicating the position, size, and other information of each functional element. Then, step-by-step design and optimization are carried out using EDA tools and the like, and finally a complete version of the chip design layout is formed. In this step, since it involves the filler insertion process, the chip design layout may still be a relatively initial version, with only relatively early data such as chip layer relationships, layer functions, and design positions of standard cells (generally functional cells cell, port FTerm, etc.). In a specific application scenario, initial data information such as layer structure and component positions can be obtained through the DEF (Design Exchange File, physical information of the design library) file and / or LEF (Library Exchange File, physical information of the process library) file of the chip design layout.

[0041] After that, in this step, the chip design layout can be partial (for example, dividing the entire design layout into a large number of sub-regions) or integral.

[0042] Step 404, determine any row according to the chip design layout, and determine any gap and the first width of the gap in the row.

[0043] In this step, when designing the chip, the chip design layout Figure 1 generally arranges each layer in rows or columns. In the chip design layout with the layout of standard cells completed, the standard cells therein will also be arranged row by row as much as possible, and then each row can be determined in the chip design layout. For any row among them, since the completed standard cells may not necessarily be closely adjacent to each other, gaps will be formed between these standard cells. In this embodiment, one of the gaps is used as an example for description. Other gaps in this row and gaps in other rows can be implemented in the same way as repeating this embodiment. Of course, this embodiment can also be implemented simultaneously on multiple rows or for multiple gaps.

[0044] After determining the gap, it is necessary to further determine the width of the gap (i.e., the first width). The width here can be marked using metric units. For example, the gap width is 10 μm, etc., or it can be marked using the standard units of chip design. This unit can be the generally recognized unit size in chip design. For example, one standard unit of A is 1 unit length, and one standard unit of B is 2 unit lengths. This can also be used to describe the gap width. For example, the width of gap C is 10 unit lengths, etc.

[0045] Step 406, screen in a preset first set according to the first width to generate a second set; wherein, the first set is a set including attribute data of at least one filler.

[0046] In this step, the first set is an initial set carrying all fillers, and which specific fillers it includes can be set in advance according to the specific scenario. At the same time, some basic attribute data of each filler can also be obtained through the first set. For example, the length of the filler, which units the filler can connect to, etc. It should be noted that the fillers here can include various types, and each structure that can be a filler can be added to the first set. For example, a decoupling circuit unit, etc.

[0047] After that, it is necessary to screen the first set using the first width to obtain the second set. First, explain the selection of fillers in chip design. For a gap, first, it is necessary to be able to completely fill the gap. After that, as few fillers as possible are needed for filling, and large fillers can be preferentially selected for filling. For example, for a 10-unit gap, if there is a 10-unit filler, the priority is the highest. Then, there is a 9-unit filler plus a 1-unit filler, and so on. After that, according to the above filler selection rules, for the screening method, the first width can be used to search in the first set to find fillers equivalent to or close to the first width as the second set. Of course, the closeness here needs to be less than the first width. For fillers larger than the first width, since they simply cannot be placed in the gap, they can be directly discarded. In some embodiments, all fillers less than or equal to the first width can be screened out from the first set to form the second set. That is, in some embodiments, the screening in the preset first set according to the first width to generate the second set includes: screening out fillers in the first set whose widths are less than or equal to the first width to generate the second set.

[0048] After that, in some embodiments, after obtaining the second set, the second set can be further screened in a more detailed manner. It should be noted that the formation of a gap is generally due to the need for two standard cells to be spaced apart by these gaps during layout to meet the corresponding design rules. The standard cells here can be the aforementioned functional units, which are used to implement corresponding specific functions in the chip. Furthermore, there are generally corresponding standard cells at both ends of a gap, and the filler generally needs to be connected to these standard cells. Thus, the second set can be further screened to filter out and remove the fillers that cannot be connected to the standard cells at both ends of the gap. This can make the second set more concise and improve efficiency. That is, in some embodiments, after generating the second set, the method further includes: determining the standard cells at both ends of the gap according to the chip design layout, and determining the first attribute of the standard cells; screening the second set again according to the first attribute to update the second set. The first attribute can be, for example, the connection attribute of the corresponding standard cell. By this connection attribute, the fillers that cannot be connected to it in the original second set are removed, thereby updating the second set.

[0049] Step 408, perform permutation and combination on the fillers in the second set according to the first width to generate at least one insertion scheme.

[0050] Step 410, perform rule checking on the at least one insertion scheme according to a preset rule table.

[0051] After generating the second set in step 406, the fillers in it can be permuted and combined according to the first width. Here, all the insertion schemes of the fillers that can be inserted into the gap (meeting the first width) can be arranged through simple permutation. It should be noted that since the corresponding connection and detection methods may be different for different placement methods, for example, for an insertion scheme of 9 units plus 1 unit, inserting the 9 units first and inserting the 1 unit first may have completely different effects. Thus, the schemes of "9 + 1" and "1 + 9" for the same fillers are actually two insertion schemes. Finally, multiple insertion schemes that can be checked later are generated.

[0052] After determining the insertion scheme, rule checking can be performed. Here, the design rules (LibraryExchange Format, LEF rule) generally refer to the restrictive conditions of the digital circuit layout design rules provided by chip processing service providers and industrial software companies. Design Rule Check (DRC) generally refers to the requirement that the designed chip layout conforms to the specified restrictive conditions due to the limitations of the manufacturing process by chip processing service providers. Design rule checking is an inspection carried out during the design process to check whether the chip design layout conforms to the restrictive conditions. In this embodiment, it is to perform corresponding design rule checking on each filler in the gap in the chip design layout.

[0053] In some embodiments, for the convenience of recording and display, the depth-first traversal algorithm of the tree structure can be used for the insertion scheme, so that the finally formed multiple insertion schemes can also be displayed or the relationship determined using the tree structure. Here, the depth-first traversal algorithm is an algorithm used to traverse or search a tree or graph, implemented through recursion or a stack. It starts from an unvisited vertex, walks along the edges of the current vertex to unvisited vertices until all vertices have been visited. The arrangement can be that the fillers inserted in the first step are used as the first-row parent nodes of the tree structure; then, for one of the parent nodes, the fillers that can be inserted in the second step after the fillers of this parent node can be used as the child nodes of this parent node; and so on, finally forming a tree structure. That is, in some embodiments, the arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: generating, based on the second set, the at least one insertion scheme that meets the first width using the depth-first traversal algorithm, where the at least one insertion scheme is represented by a tree structure.

[0054] After that, in some embodiments, during the process of generating the insertion scheme, since each selection is made from the second set, a situation may occur. For example, after selecting a filler of 8 units in the first step, it is necessary to continue selecting in the second set to fill the entire 10-unit gap. It can be seen that only fillers of 2 units or 1 unit need to be searched for here. However, in the second set selected this time, there are still a large number of fillers of other lengths, which will affect the selection efficiency. Further, the second set can be screened and updated again according to the remaining width. That is, in some embodiments, the arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: when generating any one of the insertion schemes, in response to selecting any filler in the second set and inserting it into the gap, determining the remaining second width of the gap, and screening the second set again according to the second width to update the second set. Wherein, the second width is the remaining width of the gap. For example, if a filler of 8 units or a filler of 5 units and a filler of 3 units have been selected before, the second width is 2 units.

[0055] After that, in some embodiments, according to the aforementioned rules for filling the gap with fillers, in some scenarios, it is more desirable to preferentially fill the fillers with longer lengths. Thus, the fillers in the second set can be arranged and their priorities can be set. For example, they can be arranged from long to short, and the insertion schemes containing longer fillers can be output first. For example, the insertion schemes of "9+1" or "1+9" are output first, the insertion schemes of "8+2" or "2+8" are output second, and the insertion schemes of "8+1+1" or "1+8+1" or "1+1+8" are output third. That is, in some embodiments, the arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: determining the third width of the fillers in the second set, arranging the fillers in the second set according to the third width, and determining the priority of the at least one insertion scheme according to the arrangement order. Wherein, the third width is the length of the filler, and the priority can be understood as the priority degree of rule checking. The higher the priority, the earlier the rule checking is performed. And when inserting the filler, only one insertion scheme that meets the rule checking is required. Therefore, the higher the priority, the earlier it is checked and the easier it is to become the final insertion scheme. That is, in some embodiments, the performing rule checking on the at least one insertion scheme according to a preset rule table includes: performing the rule checking on the at least one insertion scheme in sequence according to the priority.

[0056] Step 412, according to the inspection result, determine the target scheme corresponding to the gap in the at least one insertion scheme, so as to complete the insertion of the filler for the gap through the target scheme.

[0057] For the results of the rule check, they are generally divided into passing and not passing. For those that pass, the corresponding insertion scheme can be directly inserted as the final filler for the gap (i.e., the target scheme), and it can be finally inserted according to the filler insertion method recorded in this scheme.

[0058] For those that do not pass the check, it is necessary to continue to determine the next insertion scheme and re - conduct the check. This cycle continues until a target scheme is selected after passing the check or all of them do not pass. That is, in some embodiments, determining the target scheme corresponding to the gap in the at least one insertion scheme according to the check result includes: in response to being unable to pass the rule check, determining the next insertion scheme of the current insertion scheme, and re - conducting the rule check on the next insertion scheme until the target scheme that can pass the rule check is selected.

[0059] And in some embodiments, according to the manner of presenting the insertion scheme using a tree structure in the foregoing embodiments, since the entire tree structure is generally recorded and stored after being determined to facilitate operations such as scheme rollback. Based on the tree structure itself, it can be determined that the tree branch to which the current insertion scheme belongs is unavailable, and the next branch can be determined accordingly. For example, the first - level node of a tree structure is a 7 - unit filler a1, the child nodes of this node, that is, the second - level nodes are two 2 - unit fillers b1 and b2, and then the child nodes of the second - level node b1, that is, the third - level nodes are three 1 - unit fillers c1, c2, and c3. When the insertion scheme "a1 - b1 - c1" does not pass the rule check, then according to the tree structure, the next branch "a1 - b1 - c2" of this branch is selected as the object of the next rule check. That is, in some embodiments, in response to the at least one insertion scheme being represented by a tree structure; determining the next insertion scheme of the current insertion scheme includes: in the tree structure, according to the preset branch arrangement order, determining the next insertion scheme based on the branch where the current insertion scheme is located.

[0060] Finally, in some embodiments, to further improve the overall efficiency, after determining the target solution for each time, the corresponding relationship between the target solution and the gap can be determined, and these corresponding relationships can be statistically analyzed. Then, by using machine learning algorithms or other means, the similar corresponding relationships can be summarized, so that when encountering similar gaps later, the corresponding insertion solutions can be preferentially set and preferentially checked. For example: for gaps of multiple 10 units, the standard cells at both ends are also standard cell a and standard cell b, and their insertion solutions are all a "7 + 3" filler insertion solution. Then, through machine learning, when encountering a similar gap again, this "7 + 3" filler insertion solution can be set as the most preferred solution for setting and rule checking. That is, in some embodiments, after determining the target solution corresponding to the gap in the at least one insertion solution, the method further includes: establishing the corresponding relationship between the target solution and the gap, generating a third set by collecting the corresponding relationships of each gap; training a machine learning algorithm using the third set to adjust the priority order of the at least one insertion solution according to the output of the machine learning algorithm. Among them, the third set is the set recording these corresponding relationships and is also the training set of the machine learning algorithm.

[0061] As can be seen from the above, the embodiment of the present application uses a tree - structured filler addition method to solve the row - based filler addition problem, and models the filler addition problem into a model of searching the solution space using a tree - type structure. The tree - type structure has the characteristic of being easy to access successor nodes. By using the traversal method of the tree - type structure and predicting the remaining blank space of successor nodes, more reasonable filler units can be added. At the same time, the tree - type structure has a memory function, which is more conducive to updating and saving. If a design violation occurs for the filler units within the current row itself or with the filler units of other nearby rows, the saved tree - type structure can be used to restore the scene, correct the design violation of the filler, and perform the method of adding multiple rows simultaneously to ensure that the filler units of all rows meet the design requirements. In addition, by using the tree - structured filler addition method, more decoupling circuit filler units can be added by pursuing the depth - first traversal of the tree, better meeting the power integrity requirements of the chip. Finally, for different design constraints, by using the pruning method of the tree structure, the filler addition time can be shortened, enabling the algorithm to converge quickly.

[0062] Finally, in a specific application scenario, first, for gaps (filler gaps) of different widths, a suitable set of fillers (filler cell class), i.e., the second set, is initially screened out. Each filler cell class is a set of fillers (filler cells). Then, different gap patterns (filler gap patterns) are identified, mainly including standard cells around the left side and standard cells around the right side. A set of fillers suitable for different gap patterns (filler gap patterns) is further screened out from the set of fillers (filler cell class). Here, the updated set of fillers can be named filler cell sub-class. Finally, the depth-first traversal algorithm in the tree structure is used for the insertion of fillers.

[0063] Among them, the insertion of fillers using the depth-first traversal algorithm mainly includes: (1) It is necessary to consider the number of remaining gap spaces (white spaces) after adding a filler (filler cell) each time. Therefore, the most suitable filler (filler cell) needs to be selected from the filler cell sub-class with the highest priority. This can be understood as a further screening of the filler cell sub-class. (2) The depth-first traversal algorithm of the tree structure is used to add fillers, and the tree structure is still remembered until the end of the program life after the addition is completed. (3) Due to the need to meet various design requirements, a legality check is required for the surroundings of the added filler cell. (4) If a design violation occurs, the tree structure is restored according to the memory, and on-site violation repair is performed.

[0064] Finally, the filler gap patterns between different rows can be combined and classified to form a pattern cluster class. A suitable model can be trained using machine learning algorithms, and this model can be used for the addition of fillers based on the pattern cluster class, so that the user's requirements can be realized faster.

[0065] As can be seen from the above embodiments, an insertion method for fillers provided by the embodiments of the present application. In the present application, for any gap in each row of the chip design layout, fillers that can be filled are first screened according to the width, and the screened set of fillers is arranged to generate multiple insertion schemes that meet the filling conditions. Then, rule checks are directly performed on each insertion scheme in sequence to determine the insertion scheme. Since corresponding rule checks are directly performed each time, after the overall insertion of fillers is completed, there is no need for further adjustment through post-processing, ultimately improving the overall layout efficiency and enhancing the user experience.

[0066] It should be noted that the method of the embodiments of the present application can be executed by a single device, such as a computer or a server. The method of the embodiments of the present application can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In this case of a distributed scenario, one of the multiple devices can only execute one or more steps of the method of the embodiments of the present application, and these multiple devices will interact with each other to complete the described method.

[0067] It should be noted that the above specifically describes certain embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be executed in a different order than in the above embodiments and still achieve the desired result. Additionally, the processes depicted in the drawings do not necessarily require the specific order or sequential order shown to achieve the desired result. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0068] Based on the same inventive concept, corresponding to the method of any of the above embodiments, the present application also provides a non-volatile computer-readable storage medium containing a computer program. The non-volatile computer-readable storage medium containing the computer program stores computer instructions, and the computer instructions are used to cause the computer to execute the method 400 described in any of the above embodiments.

[0069] The computer-readable storage medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. The information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device.

[0070] The computer instructions stored in the storage medium of the above embodiment are used to cause the computer to execute the method 400 described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0071] Based on the same inventive concept, corresponding to the method 400 in any of the above embodiments, the present application also provides a computer program product, which includes a computer program. In some embodiments, the computer program is executable by one or more processors to cause the processors to execute the method 400. Corresponding to the execution subjects of each step in each embodiment of the method 400, the processors that execute the corresponding steps can belong to the corresponding execution subjects.

[0072] The computer program product of the above embodiment is used to cause the processor to execute the method 400 described in any of the above embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be elaborated here.

[0073] Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is only exemplary, and is not intended to imply that the scope of the present application (including the claims) is limited to these examples; under the idea of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations in different aspects of the embodiments of the present application as described above, and they are not provided in detail for the sake of brevity.

[0074] In addition, for simplicity of explanation and discussion, and so as not to make the embodiments of the present application difficult to understand, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Further, the devices may be shown in block diagram form in order to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that details regarding the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present application are to be implemented (i.e., these details should be fully within the understanding of those skilled in the art). In cases where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present application, it will be apparent to those skilled in the art that the embodiments of the present application may be practiced without these specific details or with variations of these specific details. Accordingly, these descriptions should be regarded as illustrative rather than restrictive.

[0075] Although the present application has been described in connection with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0076] Embodiments of the present application are intended to cover all such alternatives, modifications, and variations that fall within the broad scope of the appended claims. Accordingly, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the embodiments of the present application shall be included within the protection scope of the present application.

Claims

1. A filler insertion method, characterized in that: include: Obtain chip design layout; Determine any row according to the chip design layout, determine any gap in the row and a first width of the gap; Screening a preset first set according to the first width to generate a second set; wherein the first set is a set of attribute data including at least one filler; Arrange and combine the fillers in the second set according to the first width to generate at least one insertion scheme; Performing a rule check on the at least one insertion scheme according to a preset rule table; wherein the rule check is to check the filler inserted into the gap; According to the inspection result, a target solution corresponding to the gap in the at least one insertion solution is determined, so as to complete the insertion of the filler in the gap through the target solution.

2. The method according to claim 1, characterized in that After generating the second set, the method further includes: Determine the standard cells at both ends of the gap according to the chip design layout, and determine the first attribute of the standard cells; The second set is screened again according to the first attribute to update the second set.

3. The method according to claim 1, characterized in that The step of arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: Based on the second set, a depth traversal algorithm is used to generate the at least one insertion solution that meets the first width, wherein the at least one insertion solution is represented by a tree structure.

4. The method according to claim 1, characterized in that The step of arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: When any of the insertion schemes is generated, in response to selecting any filler in the second set to be inserted into the gap, a second width remaining for the gap is determined, and the second set is screened again according to the second width to update the second set.

5. The method according to claim 1, characterized in that: The step of arranging and combining the fillers in the second set according to the first width to generate at least one insertion scheme includes: Determine a third width of the fillers in the second set, arrange the fillers in the second set according to the third width, and determine the priority of the at least one insertion scheme according to the arrangement order.

6. The method according to claim 5, characterized in that The performing rule checking on the at least one insertion scheme according to a preset rule table includes: The rule checking is performed on the at least one insertion scheme in sequence according to the priority.

7. The method according to claim 1, characterized in that The step of determining, according to the inspection result, a target solution corresponding to the gap in the at least one insertion solution comprises: In response to failure to pass the rule check, a next insertion scheme of the current insertion scheme is determined, and the rule check is performed again on the next insertion scheme until the target scheme that can pass the rule check is selected.

8. The method according to claim 7, characterized in that In response to the at least one insertion scheme being represented by a tree structure; The step of determining a next insertion scheme of the current insertion scheme includes: In the tree structure, according to a preset branch arrangement order and according to the branch where the current insertion scheme is located, the next insertion scheme is determined.

9. The method according to claim 1, characterized in that: After determining the target solution corresponding to the gap in the at least one insertion solution, the method further includes: Establishing a correspondence between the target solution and the gap, and generating a third set by collecting the correspondence of each gap; The machine learning algorithm is trained using the third set to adjust the priority of the at least one insertion scheme according to the output of the machine learning algorithm.

10. The method according to claim 1, characterized in that The step of screening a preset first set according to the first width to generate a second set includes: The fillers in the first set whose width is less than or equal to the first width are screened out to generate the second set.

11. A computer device comprising one or more processors, a memory; and one or more programs, wherein the one or more programs are stored in the memory and executed by the one or more processors, and the programs include instructions for executing the method according to any one of claims 1 to 10.

12. A non-volatile computer-readable storage medium containing a computer program, which, when executed by one or more processors, causes the processors to perform the method of any one of claims 1 to 10.

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