SiC MOSFET Device Integrated with Channel-Accumulation Diode

Abstract

The present invention relates to a SiC MOSFET device integrated with a channel-accumulation diode, belonging to the technical field of power semiconductor devices. The device includes a source electrode, an N+ contact region, a P-body region, a CSL layer, P-shield regions on both sides of the CSL layer, a polysilicon gate dielectric, a polysilicon gate connected to the gate electrode, a polysilicon gate connected to the source electrode, an N-type epitaxial layer, an N-type substrate, and a drain electrode. In the present invention, a channel-accumulation diode is formed in the device body, and the channel-accumulation diode is composed of the N+ contact region on the right side, the CSL layer under the N+ contact region, the polysilicon gate dielectrics on the left and right sides of the N+ contact region, and the polysilicon gate connected to the source electrode. The present invention can improve the third-quadrant performance, achieve a low reverse conduction voltage and reverse recovery charge, and avoid the problem of bipolar degradation; while improving the third-quadrant performance, it reduces the switching loss, decreases the gate-source capacitance, and enhances the high-frequency operating performance.

Description

Technical Field

[0001] The present invention belongs to the technical field of power semiconductor devices, and relates to a SiC MOSFET device integrated with a channel-accumulation diode. Background Art

[0002] As one of the representatives of the third-generation wide-bandgap semiconductor materials, silicon carbide (SiC) material has advantages such as a wider bandgap width than silicon material, a higher critical electric field, a higher carrier saturation drift velocity, and a higher thermal conductivity. It is an excellent material for preparing high-voltage power electronic devices and has broad application prospects in the fields of high-power, high-temperature, high-voltage, and radiation-resistant power electronics.

[0003] MOSFET is the most widely used gate-controlled device structure in SiC power devices. Since SiC MOSFET is a device characterized by a unipolar transport working mechanism and has no charge storage effect, it can achieve lower switching losses and higher frequency characteristics compared with bipolar devices. At the same time, its low on-resistance and excellent high-temperature characteristics make SiC MOSFET a new generation of highly competitive low-loss power devices.

[0004] SiC MOSFETs are mainly divided into planar and trench types. The cell size of trench MOSFETs is smaller than that of planar MOSFETs, the channel density is larger, and the on-resistance is also smaller. However, the trenches introduce excessive electric fields at the bottom and corners of the trenches, and an additional P+ shielding layer needs to be added. The currently industry-leading Infineon asymmetric trench-gate MOSFET covers a part of the P-well region under the trench to protect the gate oxide layer. Although one channel is sacrificed, the asymmetric structure has a smaller cell width, effectively improving the channel density of the device and making up for the loss in on-resistance.

[0005] With the higher requirements of the industry for the power density and efficiency of the new generation of power electronic systems, the core SiC MOSFET device of the system not only needs to have excellent electrical performance in the first quadrant, but also special attention should be paid to the optimization of the third quadrant performance. Although the MOSFET structure has a parasitic body diode with reverse conduction ability, due to the wide bandgap width of SiC material, the turn-on voltage of its body diode is about 3 volts. Therefore, the loss during reverse conduction of the body diode is large. At the same time, due to the unresolved defect problems such as stacking faults in the SiC epitaxial material, the body diode is extremely likely to cause bipolar degradation during long-term operation, resulting in the degradation of the electrical performance of the MOSFET, such as an increase in on-resistance and an increase in blocking leakage current, etc. This will pose a severe challenge to the performance and reliability of the entire power system.

[0006] In order to optimize the performance of SiC MOSFET devices in the third quadrant and avoid bipolar degradation, there is an urgent need for a SiC MOSFET device that can suppress the bipolar degradation caused by the conduction of the body diode and improve the reliability and performance of the device. Summary of the Invention

[0007] In view of this, the purpose of the present invention is to provide a SiC MOSFET device integrated with a channel-accumulation diode, which can improve the performance of the SiC MOSFET in the third quadrant (low reverse conduction voltage and reverse recovery charge), suppress the bipolar degradation caused by the conduction of the body diode, improve the reliability of the device; improve the switching speed, reduce the switching loss, and enhance the high-frequency operating performance.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A SiC MOSFET device integrated with a channel-accumulation diode, comprising:

[0010] Source 1, located at the uppermost part of the device;

[0011] P-shield region 8, divided into left and right parts, located on the left and right sides below source 1;

[0012] Polysilicon gate dielectric 7, divided into left and right parts, located in the middle position below source 1;

[0013] N+ contact region 2, divided into left and right parts, located in the middle position below source 1. The right surface of the left part thereof is in contact with the left surface of the left part of polysilicon gate dielectric 7, the left surface of the left part thereof is in contact with the right surface of the left part of P-shield region 8, the left surface of the right part thereof is in contact with the right surface of the left part of polysilicon gate dielectric 7, and the right surface of the right part thereof is in contact with the left surface of the right part of polysilicon gate dielectric 7;

[0014] P-body region 3, located below the left part of N+ contact region 2, its right side is in contact with the left surface of the left part of polysilicon gate dielectric 7, and its left side is in contact with the right surface of the left part of P-shield region 8;

[0015] CSL layer 4, located below the right part of N+ contact region 2, P-body region 3 and polysilicon gate dielectric 7, and its left and right surfaces are respectively in contact with the left and right parts of P-shield region 8;

[0016] Polysilicon gate 5 connected to the gate, located on the inner left side of the left part of polysilicon gate dielectric 7;

[0017] Polysilicon gate 6 connected to the source, located on the inner right side of the left part of polysilicon gate dielectric 7 and inside the right part of polysilicon gate dielectric 7;

[0018] An N-type epitaxial layer 9, located below the CSL layer 4;

[0019] An N-type substrate 10, located below the N-type epitaxial layer 9;

[0020] A drain 11, located below the N-type substrate 10;

[0021] The right part of the N+ contact region 2, the CSL layer 4, the polysilicon gate 6, and the polysilicon gate dielectric 7 located in the middle of the polysilicon gate 6 form a channel accumulation diode.

[0022] Preferably, when the device is in the blocking state, the channel region can be completely depleted by the polysilicon gate, thereby constructing an electron barrier to realize a normally-off device. At the same time, the PN junction formed by the P-shield region and the CSL layer on the right will completely deplete the channel, thereby further ensuring the blocking ability of the device. When the device operates in the third quadrant, the channel accumulation diode with a low turn-on voltage conducts in advance, suppressing the bipolar degradation caused by the conduction of the body diode and improving the reliability and performance of the device.

[0023] Preferably, the thickness T1 of the CSL layer 4 is 1.5 - 2 μm, and the channel width W1 in the middle of the P-shield regions 8 on both sides of the CSL layer is 0.8 - 1.4 μm.

[0024] Preferably, the thickness T2 of the P-shield region 8 is 1.5 - 2 μm, and the widths W2, W3 of the left and right parts of the P-shield region 8 are 0.5 - 1.6 μm.

[0025] Preferably, the depth T3 of the polysilicon gate 5 is 1 - 1.5 μm, and the width W4 is 0.5 - 1 μm; the depth of the polysilicon gate 6 is the same as that of the polysilicon gate 5, and the widths W5, W8 of its left and right parts are 0.2 - 0.5 μm.

[0026] Preferably, the width W6 of the right part of the N+ contact region 2 is 0.1 - 0.3 μm, and the width W7 of the left part of the N+ contact region 2 is 0.3 - 0.7 μm.

[0027] Preferably, the annular width of the polysilicon gate dielectric 7 around the polysilicon gate 5 connecting the gate is 50 nm; the annular width of the polysilicon gate dielectric 7 around the polysilicon gate 6 connecting the source is 20 - 50 nm; the width of the polysilicon gate dielectric 7 between the polysilicon gate 5 connecting the gate and the polysilicon gate 6 connecting the source is 100 nm.

[0028] Preferably, the thickness T4 of the N-type epitaxial layer 9 is 8 - 13 μm.

[0029] Preferably, the thickness T5 of the N-type substrate 10 is 1 - 3 μm.

[0030] The beneficial effects of the present invention are as follows: The SiC MOSFET device proposed by the present invention can improve the performance in the third quadrant, achieve a low reverse conduction voltage and reverse recovery charge, and avoid the problem of bipolar degradation; while improving the performance in the third quadrant, it reduces the switching loss, decreases the gate-source capacitance, and enhances the high-frequency operating performance.

[0031] Other advantages, objectives, and features of the present invention will be described to some extent in the subsequent specification, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be achieved and obtained through the following specification. Brief Description of the Drawings

[0032] In order to make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0033] Figure 1 is a schematic cross-sectional view of the structure of the SiC MOSFET device integrating a channel-accumulation diode of the present invention;

[0034] Figure 2 is a schematic cross-sectional view of the structure of a traditional SiC MOSFET device;

[0035] Figure 3 is a comparison diagram of the transfer characteristic curves of the present invention and a traditional SiC MOSFET;

[0036] Figure 4 is a comparison diagram of the output characteristic curves of the present invention and a traditional SiC MOSFET;

[0037] Figure 5 is a comparison diagram of the reverse conduction characteristic curves of the present invention and a traditional SiC MOSFET;

[0038] Figure 6 is a comparison diagram of the breakdown characteristic curves of the present invention and a traditional SiC MOSFET;

[0039] Figure 7 is a comparison diagram of the switching characteristic curves of the present invention and a traditional SiC MOSFET;

[0040] Figure 8 is a comparison diagram of the reverse recovery characteristic curves of the present invention and a traditional SiC MOSFET;

[0041] Reference numerals: 1 - source electrode, 2 - N+ contact region, 3 - P-body region, 4 - CSL layer, 5 - polysilicon gate connected to the gate electrode, 6 - polysilicon gate connected to the source electrode, 7 - polysilicon gate dielectric, 8 - P-shield region, 9 - N-type epitaxial layer, 10 - N-type substrate, 11 - drain electrode. Detailed implementation manners

[0042] The following specific examples illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following examples only schematically illustrate the basic concept of the present invention. Without conflict, the following examples and the features in the examples can be combined with each other.

[0043] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, and do not represent the dimensions of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0044] In the drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only for illustrative purposes and should not be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0045] Such as Figure 1As shown in the figure, an embodiment of the present invention provides a SiC MOSFET device integrated with a channel-accumulation diode, which specifically includes a source electrode 1, an N+ contact region 2, a P-body region 3, a CSL layer 4, P-shield regions 8 on both sides of the CSL layer, a polysilicon gate dielectric 7, a polysilicon gate 5 connected to the gate electrode, a polysilicon gate 6 connected to the source electrode, an N-type epitaxial layer 9, an N-type substrate 10, and a drain electrode 11. Among them, the N+ contact region 2 on the right side, the CSL layer 4 located below the N+ contact region 3 on the right side, the polysilicon gate 6 connected to the source electrode on both the left and right sides of the N+ contact region 2 on the right side, and the polysilicon gate dielectric 7 located in the middle of the N+ contact region 2 on the right side and the polysilicon gates 6 connected to the source electrode on both the left and right sides form a channel-accumulation diode.

[0046] In this embodiment, the thickness T1 of the CSL layer 4 is 1.8 μm, and the channel width W1 in the middle of the P-shield regions 8 on both sides of the CSL layer is 0.9 μm.

[0047] The thickness T2 of the P-shield region 8 is 1.6 μm, the width W2 of the left P-shield region 8 is 0.5 μm, and the widest width W3 of the right P-shield region 8 is 1.6 μm.

[0048] The depth T3 of the polysilicon gate 5 connected to the gate electrode is 1 μm, and the width W4 is 0.5 μm.

[0049] The depth of the polysilicon gate 6 connected to the source electrode is the same as that of the polysilicon gate 5 connected to the gate electrode, and the widths W5 and W8 are 0.2 μm. The width W6 of the N+ contact region 2 on the right side is 0.2 μm, and the width W7 of the N+ contact region 2 on the left side is 0.5 μm.

[0050] The thickness of the polysilicon gate dielectric 7 on the left side and below the polysilicon gate 5 connected to the gate electrode is 50 nm, the thickness of the polysilicon gate dielectric 7 in the middle of the polysilicon gates 6 connected to the source electrode on both the left and right sides and the N+ contact region 2 on the right side is 20 nm, and the thickness of the polysilicon gate dielectric 7 in the middle of the polysilicon gate 5 connected to the gate electrode and the polysilicon gate 6 connected to the source electrode inside the left polysilicon gate dielectric 7 is 100 nm.

[0051] The thickness T4 of the N-type epitaxial layer 9 is 9.2 μm, and the thickness T5 of the N-type substrate 10 is 2 μm.

[0052] In the present invention, by forming a channel-accumulation diode in the device, when the device operates in the third quadrant, the low-turn-on-voltage channel-accumulation diode conducts in advance, suppressing the bipolar degradation caused by the conduction of the body diode, and improving the reliability and performance of the device; at the same time, due to the adoption of a split-gate structure, the gate-source capacitance is reduced, the switching speed is increased, and the switching loss is reduced.

[0053] By Figure 3 、 Figure 4It can be seen that the gate control ability of the structural device in the embodiment of the present invention is slightly better than that of the traditional structural device (such as Figure 2 shown). The threshold voltage of the structural device in the embodiment of the present invention is 6.12V, and the threshold voltage of the traditional structural device is 6.15V. When the gate voltage is 15V and the drain voltage is 1V, the specific on-resistance of the structural device in the embodiment of the present invention is 2.99 mΩ / cm 2 , and the specific on-resistance of the traditional structural device is 3.02 mΩ / cm 2 .

[0054] Through Figure 5 it can be seen that the reverse conduction voltage of the structural device in the embodiment of the present invention is significantly lower than that of the traditional structural device. When the voltage at 100 A / cm 2 is taken as the reverse conduction voltage, the reverse conduction voltage of the structural device in the embodiment of the present invention is 1.42V, and the reverse conduction voltage of the traditional structural device is 2.80V. Compared with the traditional structure, the reverse conduction voltage of the structure in the embodiment of the present invention is reduced by 49.28%, and the bipolar degradation caused by the diode conduction is suppressed, improving the reliability of the device.

[0055] Figure 6 is the breakdown characteristic diagram of the structure in the embodiment of the present invention and the traditional structure. The breakdown voltage of the structure in the embodiment of the present invention is 1790V, and the breakdown voltage of the traditional structure is 1823V. The breakdown voltage of the structure in the embodiment of the present invention is only slightly less than that of the traditional structure.

[0056] Figure 7 is the switching characteristic diagram of the structure in the embodiment of the present invention and the traditional structure. The turn-on loss of the structure in the embodiment of the present invention is 1.892 mJ / cm 2 , the turn-off loss is 2.732 mJ / cm 2 , and the total switching loss is 4.624 mJ / cm 2 . The turn-on loss of the traditional structure is 3.212 mJ / cm 2 , the turn-off loss is 4.733 mJ / cm 2 , and the total switching loss is 7.945 mJ / cm 2 . Compared with the traditional structure, the turn-on loss of the structure in the example of the present invention is reduced by 41.09%, the turn-off loss is reduced by 42.27%, and the total switching loss is reduced by 41.79%.

[0057] Figure 8 is the reverse recovery characteristic diagram of the structure in the embodiment of the present invention and the traditional structure. It can be clearly seen from the figure that the reverse recovery charge of the structure in the embodiment of the present invention is less than that of the traditional structure. The reverse recovery charge of the structure in the embodiment of the present invention is 1.09 μC / cm 2 , and the reverse recovery charge of the traditional structure is 2.864 μC / cm 2Compared with the traditional structure, the reverse recovery charge of the structure of the embodiment of the present invention is reduced by 61.94%, greatly improving the reverse conduction recovery characteristics.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A SiC MOSFET device integrated with a channel accumulation diode, characterized in that, The device includes: A source electrode (1), located at the uppermost part of the device; A P-shield region (8), divided into left and right parts, located on the left and right sides below the source electrode (1); A polysilicon gate dielectric (7), divided into left and right parts, located in the middle position below the source electrode (1); An N+ contact region (2), divided into left and right parts, located in the middle position below the source electrode (1). The right surface of the left part thereof contacts the left surface of the left part of the polysilicon gate dielectric (7), the left surface of the left part thereof contacts the right surface of the left part of the P-shield region (8), the left surface of the right part thereof contacts the right surface of the left part of the polysilicon gate dielectric (7), and the right surface of the right part thereof contacts the left surface of the right part of the polysilicon gate dielectric (7); A P-body region (3), located below the left part of the N+ contact region (2). Its right side contacts the left surface of the left part of the polysilicon gate dielectric (7), and its left side contacts the right surface of the left part of the P-shield region (8); A CSL layer (4), located below the right part of the N+ contact region (2), the P-body region (3), and the polysilicon gate dielectric (7). Its left and right surfaces respectively contact the left and right parts of the P-shield region (8); A polysilicon gate (5) connected to the gate, located on the inner left side of the left part of the polysilicon gate dielectric (7); A polysilicon gate (6) connected to the source, located on the inner right side of the left part of the polysilicon gate dielectric (7) and inside the right part of the polysilicon gate dielectric (7); An N-type epitaxial layer (9), located below the CSL layer (4); An N-type substrate (10), located below the N-type epitaxial layer (9); A drain electrode (11), located below the N-type substrate (10); The right part of the N+ contact region (2), the CSL layer (4), the polysilicon gate (6) connected to the source, and the polysilicon gate dielectric (7) located in the middle of the polysilicon gate (6) connected to the source form a channel accumulation type diode; The annular width of the polysilicon gate dielectric (7) surrounding the polysilicon gate (6) connected to the source is 20 - 50 nm; the width W6 of the right part of the N+ contact region (2) is 0.1 - 0.3 μm; the annular width of the polysilicon gate dielectric (7) surrounding the polysilicon gate (5) connected to the gate is 50 nm; the width of the polysilicon gate dielectric (7) between the polysilicon gate (5) connected to the gate and the polysilicon gate (6) connected to the source is 100 nm.

2. The SiC MOSFET device according to claim 1, characterized in that, The thickness T1 of the CSL layer (4) is 1.5 - 2 μm, and the channel width W1 between the P-shield regions (8) on both sides of the CSL layer is 0.8 - 1.4 μm.

3. The SiC MOSFET device according to claim 1, wherein The thickness T2 of the P-shield region (8) is 1.5 - 2 μm, and the widths W2, W3 of the left and right parts of the P-shield region (8) are 0.5 - 1.6 μm.

4. The SiC MOSFET device according to claim 1, wherein The depth T3 of the polysilicon gate (5) is 1 - 1.5 μm, and the width W4 is 0.5 - 1 μm; the depth of the polysilicon gate (6) is the same as that of the polysilicon gate (5), and the widths W5, W8 of its left and right parts are 0.2 - 0.5 μm.

5. The SiC MOSFET device according to claim 1, characterized in that, The width W7 of the left part of the N+ contact region (2) is 0.3 - 0.7 μm.

6. The SiC MOSFET device according to claim 1, characterized in that, The thickness T4 of the N-type epitaxial layer (9) is 8 - 13 μm.

7. The SiC MOSFET device according to claim 1, characterized in that, The thickness T5 of the N-type substrate (10) is 1 - 3 μm.

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