A dynamic adjustment and calibration circuit for a charge pump

Abstract

The purpose of the present invention is to provide a dynamic adjustment and calibration circuit for a charge pump, the circuit comprising: a charge pump operational amplifier module and a charge pump dynamic calibration module; the charge pump operational amplifier module and the charge pump dynamic calibration module are connected; the charge pump dynamic calibration module is used to adjust the power supply capacity of the charge pump according to a feedback clock signal; the charge pump operational amplifier module is used to adjust the current output by a MOS current source and an NMOS current source. The present invention can further reduce the current source mismatch, reduce the circuit power consumption, and improve the performance of the charge pump by dynamically regulating the PMOS and NMOS current sources.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a dynamic adjustment and calibration circuit of a charge pump. Background Art

[0002] As the design of chips continues to develop in the direction of high speed, the frequency required by the phase-locked loop is getting higher and higher. The charge pump CP (charge pump) is an important module in the phase-locked loop and is known as the heart of the phase-locked loop. Its main function is to convert the clock phase difference output by the phase frequency detector (PFD) into charge and transmit it to the loop filter to generate the voltage to control the VCO. The charge pump, also known as the switched capacitor voltage converter, is a DC-DC (converter) that uses "fast" or "pumping" capacitors (rather than inductors or transformers) to store energy. Charge pumps can be divided into: switching regulator boost pumps, non-adjustable capacitor charge pumps, and adjustable capacitor charge pumps. The working process of the three charge pumps is: first store energy, and then release energy in a controlled manner to obtain the required output voltage. The switching regulator boost pump uses an inductor to store energy, while the capacitive charge pump uses a capacitor to store energy. The capacitive charge pump achieves voltage boost through a switch array and oscillator, logic circuit, and comparison controller, and uses a capacitor to store energy. Because it works at a higher frequency, small ceramic capacitors can be used, which takes up minimal space and has a low cost. The charge pump can provide ±2 times the output voltage with only external capacitors. Its loss mainly comes from the equivalent series resistance (ESR) of the capacitor and the RDS (ON) of the internal switching transistor. The charge pump converter does not use an inductor, so its radiated EMI can be ignored. The input noise can be filtered out with a small capacitor. Its output voltage is precisely preset during factory production and can be adjusted by the back-end on-chip linear regulator. Therefore, the charge pump can be designed to increase the number of switch stages of the charge pump as needed to provide sufficient room for the back-end regulator. The charge pump is very suitable for the design of portable application products. It is a system composed of reference, comparison, conversion and control circuits.

[0003] Most charge pump circuits currently used face a common problem: the mismatch between the PMOS and NMOS current sources. A better solution is to use an operational amplifier to make the UP and DN currents track each other and reduce the mismatch between the current sources. However, the power supply capacity of the circuit always remains consistent and cannot be dynamically adjusted according to the needs of the circuit. Summary of the invention

[0004] The object of the present invention is to provide a dynamic adjustment and calibration circuit for a charge pump, which can further reduce current source mismatch, reduce circuit power consumption, and improve the performance of the charge pump by dynamically adjusting PMOS and NMOS current sources.

[0005] A dynamic adjustment and calibration circuit for a charge pump, comprising: a charge pump operational amplifier module and a charge pump dynamic calibration module;

[0006] The charge pump operational amplifier module is connected to the charge pump dynamic calibration module;

[0007] The charge pump dynamic calibration module is used to adjust the power supply capacity of the charge pump according to the feedback clock signal;

[0008] The charge pump operational amplifier module is used to adjust the current output by the MOS current source and the NMOS current source;

[0009] The charge pump dynamic calibration module includes: a first transmission module, a second transmission module, a first capacitor, a first MOS transistor and a second MOS transistor;

[0010] The first transmission module is connected to the upper plate of the first capacitor;

[0011] The second transmission module is connected to the upper plate of the first capacitor;

[0012] The drain of the first MOS tube is connected to the drain of the second MOS tube;

[0013] The gate of the second MOS tube is connected to the upper plate of the first capacitor;

[0014] The drain of the first MOS tube and the drain of the second MOS tube are connected to the upper plate of the first capacitor.

[0015] Preferably, the first transmission module includes: a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor and a second capacitor;

[0016] The first transmission gate, the second transmission gate and the third transmission gate are connected in series;

[0017] The input end of the first transmission gate is connected to the drain of the third MOS tube;

[0018] The gate of the fourth MOS transistor is connected between the output end of the first transmission gate and the input end of the second transmission gate;

[0019] The output end of the fourth transmission gate is connected to the drain of the fifth MOS tube, the drain of the sixth MOS tube and one end of the second capacitor;

[0020] The other end of the second capacitor is connected between the output end of the second transmission gate and the input end of the third transmission gate;

[0021] The output end of the third transmission gate is connected to the upper plate of the first capacitor.

[0022] Preferably, the second transmission module includes: a fifth transmission gate, a sixth transmission gate, a seventh transmission gate, an eighth transmission gate, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor and a third capacitor;

[0023] The fifth transmission gate, the sixth transmission gate and the seventh transmission gate are connected in series;

[0024] The input end of the fifth transmission gate is connected to the drain of the seventh MOS tube;

[0025] The gate of the eighth MOS transistor is connected between the output end of the fifth transmission gate and the input end of the sixth transmission gate;

[0026] The output end of the eighth transmission gate is connected to the drain of the ninth MOS tube, the drain of the tenth MOS tube and one end of the third capacitor;

[0027] The other end of the third capacitor is connected between the output end of the sixth transmission gate and the input end of the seventh transmission gate;

[0028] The output end of the seventh transmission gate is connected to the upper plate of the first capacitor.

[0029] Preferably, the charge pump operational amplifier module includes: an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube and a nineteenth MOS tube;

[0030] The drain of the eleventh MOS tube is connected to the source of the twelfth MOS tube and the source of the thirteenth MOS tube;

[0031] The drain of the twelfth MOS tube is connected to the drain of the fourteenth MOS tube and the drain of the fifteenth MOS tube;

[0032] The gate of the fifteenth MOS tube is connected to the drain of the fourteenth MOS tube;

[0033] The source of the sixteenth MOS tube is connected to the drain of the thirteenth MOS tube;

[0034] The drain of the seventeenth MOS tube is connected to the gate of the sixteenth MOS tube and the drain of the thirteenth MOS tube;

[0035] The gate of the eighteenth MOS tube is connected to the drain of the seventeenth MOS tube;

[0036] The drain of the eighteenth MOS tube is connected to the drain of the nineteenth MOS tube.

[0037] Preferably, it also includes: a bias current generating module;

[0038] The bias current generating module is connected to the charge pump operational amplifier module and is used to generate a bias current in the circuit;

[0039] The bias current generating module includes: a 20th MOS tube, a 21st MOS tube, a 22nd MOS tube, a 23rd MOS tube and a 24th MOS tube;

[0040] The gate of the 20th MOS tube is connected to the gate of the 21st MOS tube;

[0041] The drain of the 20th MOS tube is connected to the source of the 21st MOS tube;

[0042] The source of the 20th MOS tube is connected to the drain and gate of the 22nd MOS tube;

[0043] The source of the twenty-second MOS tube is connected to the source of the twenty-third MOS tube;

[0044] The gate of the twenty-third MOS tube is connected to the drain of the twenty-first MOS tube;

[0045] The drain of the twenty-third MOS tube is connected to the source of the twenty-fourth MOS tube;

[0046] The drain of the twenty-fourth MOS tube is connected to the drain of the twenty-first MOS tube.

[0047] Preferably, it also includes: a RST signal generating module;

[0048] The RST signal generating module is connected to the charge pump operational amplifier module and the charge pump dynamic calibration module, and is used to compare the difference between VCAL_N and VCAL_P to generate an RST signal;

[0049] The RST signal generating module includes: a Schmitt trigger inverter, a first NOT gate, a second NOT gate, a twenty-fifth MOS transistor, a twenty-sixth MOS transistor, a twenty-seventh MOS transistor, a twenty-eighth MOS transistor, a twenty-ninth MOS transistor, a thirtieth MOS transistor and a thirty-first MOS transistor;

[0050] The drain of the twenty-fifth MOS tube is connected to the source of the twenty-sixth MOS tube and the twenty-seventh MOS tube;

[0051] The drain of the twenty-sixth MOS tube is connected to the source of the twenty-ninth MOS tube;

[0052] The drain of the twenty-seventh MOS transistor is connected to the source of the twenty-eighth MOS transistor;

[0053] The drains of the twenty-eighth MOS transistor and the twenty-ninth MOS transistor are grounded;

[0054] The sources of the thirtieth MOS transistor and the thirty-first MOS transistor are connected;

[0055] The drain of the thirty-first MOS transistor is connected to the input terminal of the Schmitt trigger inverter;

[0056] The output terminal of the Schmitt trigger inverter is connected to the input terminal of the first NOT gate;

[0057] The output terminal of the first NOT gate is connected to the input terminal of the second NOT gate.

[0058] A control method for a dynamic regulation and calibration circuit of a charge pump, which is applied to a dynamic regulation and calibration circuit of a charge pump, includes:

[0059] Controlling the opening of the transmission gates of the first transmission module and the second transmission module according to the output of the RST signal generation module;

[0060] Controlling the power supply capacity of the current source according to the opening or closing of the transmission gate;

[0061] Adapting to adjust the opening of the transmission gate according to the change of the feedback clock.

[0062] Preferably, the controlling the opening of the transmission gates of the first transmission module and the second transmission module according to the output of the RST signal generation module includes:

[0063] When the RST signal is at a high level, VCAL_P > VCAL_N, the first transmission gate is opened, and the fifth transmission gate is closed;

[0064] The logic control signal switches the opening of the transmission gate according to the change of the feedback clock, the voltage of VCAL_N is raised, and the voltage of VBP is increased;

[0065] When the RST signal is at a low level, VCAL_P < VCAL_N, the fifth transmission gate is opened, and the first transmission gate is closed;

[0066] The logic control signal switches the opening of the transmission gate according to the change of the feedback clock, the voltage of VCAL_P is raised, and the voltage of VBN is pulled down.

[0067] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, the computer program codes include computer instructions, and when the processor executes the computer instructions, the electronic device executes a method for controlling a dynamic adjustment calibration circuit of a charge pump.

[0068] The beneficial effects of the present invention are as follows: 1. The present invention can dynamically adjust the power supply capacity of the charge pump according to the feedback of the feedback clock signal in real time, reduce the mismatch of the charge pump, further improve the accuracy of the phase-locked loop, and thus improve the locking ability of the circuit. 2. The present invention further reduces the power consumption of the circuit, reduces the heating of the circuit, and improves the safety and stability of the circuit by adjusting the power supply capacity of the charge pump. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0070] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0071] Figure 1 It is a circuit diagram of a charge pump dynamic calibration module of the present invention;

[0072] Figure 2 is a schematic diagram of a first output module circuit of the present invention;

[0073] Figure 3 is a schematic diagram of a second output module circuit of the present invention;

[0074] Figure 4 It is a circuit diagram of a charge pump operational amplifier module of the present invention;

[0075] Figure 5 is a schematic diagram of a bias current generating module circuit of the present invention;

[0076] Figure 6 The schematic diagram of the RST signal generating module circuit of the present invention;

[0077] Figure 7 It is a schematic diagram of the main circuit structure of the charge pump of the present invention;

[0078] Figure 8 A schematic diagram of the hardware structure of an electronic device of the present invention;

[0079] Fig. 9This is a schematic diagram of a control signal generating logic circuit of the present invention. DETAILED DESCRIPTION

[0080] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0081] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0082] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0083] Most charge pump circuits currently used face a common problem: the mismatch between the PMOS and NMOS current sources. A better solution is to use an operational amplifier to make the UP and DN currents track each other and reduce the mismatch between the current sources. However, the power supply capacity of the circuit always remains consistent and cannot be dynamically adjusted according to the needs of the circuit.

[0084] The present invention can dynamically adjust the power supply capacity of the charge pump according to the feedback of the feedback clock signal in real time, reduce the mismatch of the charge pump, further improve the accuracy of the phase-locked loop, and thus improve the locking ability of the circuit. By adjusting the power supply capacity of the charge pump, the present invention further reduces the power consumption of the circuit, reduces the heating of the circuit, and improves the safety and stability of the circuit.

[0085] Example 1

[0086] A dynamic adjustment and calibration circuit for a charge pump, referring to Figure 1 and Figure 7 , including: a charge pump operational amplifier module and a charge pump dynamic calibration module;

[0087] The charge pump operational amplifier module is connected to the charge pump dynamic calibration module;

[0088] The main function of the operational amplifier module is to amplify and process the signal, including mathematical operations such as signal addition, subtraction, differentiation, and integration. In actual circuits, the operational amplifier module is usually combined with a feedback network to form a functional module that can amplify the differential signal between the two input ends, suppress the common-mode signal, and has the characteristics of extremely large input impedance and extremely small output impedance. The operational amplifier module is not only used to implement mathematical operations in analog computers, but is also widely used in active filters, switched capacitor circuits, digital-to-analog and analog-to-digital converters, DC signal amplification, waveform generation and transformation, and signal processing. In addition, the operational amplifier module can also amplify small signals like triodes and MOS tubes.

[0089] The charge pump dynamic calibration module is used to adjust the power supply capability of the charge pump according to the feedback clock signal;

[0090] A charge pump is a circuit based on the principle of capacitance, which is used to increase or decrease voltage. It achieves voltage increase or decrease by periodically changing the connection mode of the capacitor to transfer charge from one capacitor to another. However, due to certain errors in the component parameters in the charge pump, the output voltage of the charge pump may be mismatched with the theoretical value. Charge pump mismatch calibration is a calibration method used to adjust the component parameters of the charge pump so that its output voltage matches the theoretical value. The principle of the charge pump is based on the charging and discharging process of the capacitor. By changing the connection mode of the capacitor, the charge can be transferred from one capacitor to another, thereby achieving voltage increase or decrease. The charge pump is usually composed of two alternating capacitors and switches. When the switch is switched, the connection mode between the capacitors changes, causing the charge to flow from one capacitor to another. Through multiple switching, the charge is gradually accumulated or released, thereby achieving voltage increase or decrease. However, there are certain errors in the component parameters in the charge pump, such as the capacitance of the capacitor, the on-resistance of the switch, etc. These errors will cause the output voltage of the charge pump to be mismatched with the theoretical value. Therefore, charge pump mismatch calibration is required to adjust the component parameters so that the output voltage matches the theoretical value.

[0091] The charge pump operational amplifier module is used to adjust the current output by the MOS current source and the NMOS current source.

[0092] A constant current power supply is a power supply that keeps the output current at a certain value. Its function is to ensure that the output current remains unchanged within a certain load range. The magnitude of the current depends on the components in the circuit and the values ​​of components such as resistors, capacitors, and inductors. By adjusting the resistance, capacitance, and inductance of these components, the output current of the constant current power supply can be adjusted.

[0093] Preferably, the charge pump dynamic calibration module comprises: a first transmission module, a second transmission module, a first capacitor (C1), a first MOS transistor (M1) and a second MOS transistor (M2);

[0094] The first transmission module is connected to the upper plate of the first capacitor (C1);

[0095] The second transmission module is connected to the upper plate of the first capacitor (C1);

[0096] The drain of the first MOS tube (M1) is connected to the drain of the second MOS tube (M2);

[0097] The gate of the second MOS tube (M2) is connected to the upper plate of the first capacitor (C1);

[0098] The drain of the first MOS tube (M1) and the drain of the second MOS tube (M2) are connected to the upper plate of the first capacitor (C1).

[0099] VXS is a constant input voltage, REFCAL is a bias voltage, and the transmission gate control signal is Fig. 9 In the control signal generation logic circuit, the feedback signal (DIV_CLK) is firstly used to generate the related control signals PH1, PH1Z, PH2, PH2Z, PH1N and PH1P through the logic circuit (D flip-flop and inverter), as shown in Fig. 9 As shown, the frequency of DIV_CLK determines the switching speed of these control signals.

[0100] Preferably, reference Figure 2 The first transmission module includes: a first transmission gate (T1), a second transmission gate (T2), a third transmission gate (T3), a fourth transmission gate (T4), a third MOS transistor (M3), a fourth MOS transistor (M4), a fifth MOS transistor (M5), a sixth MOS transistor (M6) and a second capacitor (C2);

[0101] A first transmission gate (T1), a second transmission gate (T2) and a third transmission gate (T3) are connected in series;

[0102] An input end of the first transmission gate (T1) is connected to a drain of a third MOS tube (M3);

[0103] The gate of the fourth MOS tube (M4) is connected between the output end of the first transmission gate (T1) and the input end of the second transmission gate (T2);

[0104] The output end of the fourth transmission gate (T4) is connected to the drain of the fifth MOS tube (M5), the drain of the sixth MOS tube (M6) and one end of the second capacitor (C2);

[0105] The other end of the second capacitor (C2) is connected between the output end of the second transmission gate (T2) and the input end of the third transmission gate (T3);

[0106] The output end of the third transmission gate (T3) is connected to the upper plate of the first capacitor (C1).

[0107] Preferably, reference Figure 3 The second transmission module includes: a fifth transmission gate (T5), a sixth transmission gate (T6), a seventh transmission gate (T7), an eighth transmission gate, a seventh MOS tube (M7), an eighth MOS tube (M8), a ninth MOS tube (M9), a tenth MOS tube (M10) and a third capacitor (C3);

[0108] A fifth transmission gate (T5), a sixth transmission gate (T6) and a seventh transmission gate (T7) are connected in series;

[0109] The input end of the fifth transmission gate (T5) is connected to the drain of the seventh MOS tube (M7);

[0110] The gate of the eighth MOS transistor (M8) is connected between the output end of the fifth transmission gate (T5) and the input end of the sixth transmission gate (T6);

[0111] The output end of the eighth transmission gate is connected to the drain of the ninth MOS tube (M9), the drain of the tenth MOS tube (M10) and one end of the third capacitor (C3);

[0112] The other end of the third capacitor (C3) is connected between the output end of the sixth transmission gate (T6) and the input end of the seventh transmission gate (T7);

[0113] The output end of the seventh transmission gate (T7) is connected to the upper plate of the first capacitor (C1).

[0114] Preferably, reference Figure 4 The charge pump operational amplifier module includes: an eleventh MOS tube (M11), a twelfth MOS tube (M12), a thirteenth MOS tube (M13), a fourteenth MOS tube (M14), a fifteenth MOS tube (M15), a sixteenth MOS tube (M16), a seventeenth MOS tube (M17), an eighteenth MOS tube (M18) and a nineteenth MOS tube (M19);

[0115] The drain of the eleventh MOS tube (M11) is connected to the source of the twelfth MOS tube (M12) and the source of the thirteenth MOS tube (M13);

[0116] The drain of the twelfth MOS tube (M12) is connected to the drain of the fourteenth MOS tube and the drain of the fifteenth MOS tube (M15);

[0117] The gate of the fifteenth MOS tube (M15) is connected to the drain of the fourteenth MOS tube (M14);

[0118] The source of the sixteenth MOS tube (M16) is connected to the drain of the thirteenth MOS tube (M13);

[0119] The drain of the seventeenth MOS tube (M17) is connected to the gate of the sixteenth MOS tube (M16) and the drain of the thirteenth MOS tube (M13);

[0120] The gate of the eighteenth MOS tube (M18) is connected to the drain of the seventeenth MOS tube (M17);

[0121] The drain of the eighteenth MOS tube (M18) is connected to the drain of the nineteenth MOS tube (M19).

[0122] In the charge pump operational amplifier module, VCAL_P and VCAL_N can dynamically adjust the output voltage values ​​of VBNFB and VBPFB to change the current size of the current source.

[0123] Preferably, it also includes: reference Figure 5 , bias current generating module;

[0124] The bias current generating module is connected to the charge pump operational amplifier module and is used to generate a bias current in the circuit;

[0125] The bias current generating module includes: a twentieth MOS tube (M20), a twenty-first MOS tube (M21), a twenty-second MOS tube (M22), a twenty-third MOS tube (M23) and a twenty-fourth MOS tube (M24);

[0126] The gate of the twentieth MOS tube (M20) is connected to the gate of the twenty-first MOS tube (M21);

[0127] The drain of the twentieth MOS tube (M20) is connected to the source of the twenty-first MOS tube (M21);

[0128] The source of the twentieth MOS tube (M20) is connected to the drain and gate of the twenty-second MOS tube (M22);

[0129] The source of the twenty-second MOS tube (M22) is connected to the source of the twenty-third MOS tube (M23);

[0130] The gate of the twenty-third MOS tube (M23) is connected to the drain of the twenty-first MOS tube (M21);

[0131] The drain of the twenty-third MOS tube (M23) is connected to the source of the twenty-fourth MOS tube (M24);

[0132] The drain of the twenty-fourth MOS tube (M24) is connected to the drain of the twenty-first MOS tube (M21).

[0133] Bias current is the DC current flowing through the base of the amplifier input transistor. This current is necessary to ensure that the amplifier operates in the linear range and provides the DC operating point for the amplifier. In op amps (operational amplifiers), bias current is particularly important because it limits the value of the input resistor and feedback resistor to ensure operational accuracy and stable operation of the amplifier in the linear range. If the design requires the use of large feedback resistors and input resistors, consider using an op amp with J-FET inputs, because J-FETs are voltage-controlled devices and their input bias current parameter refers to the reverse leakage current of the input PN junction, which is usually small. Biasing refers to the method of setting an appropriate operating point by establishing predetermined voltages and / or currents at multiple points in an electronic circuit. This involves providing a fixed DC voltage and current to a specific part of the circuit to ensure that the circuit operates under the expected operating conditions. In transistor circuits, the bias circuit ensures that the transistor operates properly by providing current (bias current) to the base and providing appropriate voltages to the emitter and collector junctions. The offset current is a small current generated by the bias current of active devices and the leakage current flowing through the insulators in the instrument under certain conditions, such as when the input of the ammeter is open. This is related to the concept of bias current, but the offset current refers more to the small current deviation caused by various factors in actual measurement or operation. The bias current generation module can ensure that the amplifier operates in the linear range and provide a DC operating point for the amplifier.

[0134] Preferably, reference Figure 6 , further comprising: a RST signal generating module;

[0135] The RST signal generation module is connected to the charge pump operational amplifier module and the charge pump dynamic calibration module, and is used to compare the difference between VCAL_N and VCAL_P to generate the RST signal;

[0136] The RST signal generating module includes: a Schmitt trigger inverter, a first NOT gate (N1), a second NOT gate (N2), a twenty-fifth MOS tube (M25), a twenty-sixth MOS tube (M26), a twenty-seventh MOS tube (M27), a twenty-eighth MOS tube (M28), a twenty-ninth MOS tube (M29), a thirtieth MOS tube (M30) and a thirty-first MOS tube (M31);

[0137] The drain of the twenty-fifth MOS tube (M25) is connected to the source of the twenty-sixth MOS tube (M26) and the twenty-seventh MOS tube (M27);

[0138] The drain of the twenty-sixth MOS tube (M26) is connected to the source of the twenty-ninth MOS tube (M29);

[0139] The drain of the twenty-seventh MOS tube (M27) is connected to the source of the twenty-eighth MOS tube (M28);

[0140] The drain of the twenty-eighth MOS tube (M28) and the drain of the twenty-ninth MOS tube (M29) are grounded;

[0141] The source of the 30th MOS tube (M30) is connected to the source of the 31st MOS tube (M31);

[0142] The drain of the thirty-first MOS tube (M31) is connected to the input terminal of the Schmitt trigger inverter;

[0143] The output end of the Schmitt trigger inverter is connected to the input end of the first NOT gate (N1);

[0144] The output end of the first NOT gate (N1) is connected to the input end of the second NOT gate (N2).

[0145] Figure 6 For the folded common source and common gate amplifier, the tail current source of the operational amplifier is controlled by VCAL_N and VCAL_P respectively. The main function of the circuit is to compare the difference between VCAL_N and VCAL_P to generate the RST signal. When VCAL_P>VCAL_N, RST=1, RSTZ=0; when VCAL_N>VCAL_P, RST=0, RSTZ=1.

[0146] Example 2

[0147] A method for controlling a dynamic adjustment and calibration circuit of a charge pump is applied to a dynamic adjustment and calibration circuit of a charge pump, comprising:

[0148] S100, controlling the transmission gates of the first transmission module and the second transmission module to open according to the output of the RST signal generating module;

[0149] The RST signal means reset or initialization, and is usually used in circuits with CPUs. The RST signal, full name Reset, is a common function, mainly used for reset operations in electronic devices, computer systems or networks. Its main function is to restore the device, system or network to the initial state or default settings. Through the RST function, some faults, errors or configuration problems can be solved and the device can work normally again. In electronic devices, the RST function is usually a physical button or switch used to restore the device to factory settings or restart the device. For example, network devices such as routers and switches usually have an RST button. When the device fails or has a configuration error, pressing the RST button can restore the device to the initial configuration to solve the problem. In addition, some portable devices such as smartphones and tablets can also perform soft or hard restarts through the RST function to solve problems such as device freezes and freezes. In computer systems, the RST function is usually used to reset or reset the system. For example, when the computer has a blue screen, freezes, and other faults, the computer can be restarted by pressing the RST button or performing the corresponding reset operation. In addition, in computer programming, the RST instruction is also often used to control the execution flow of the program to implement the reset or reset function of the program. This is very useful for debugging programs, handling exceptions, and other tasks. The role of the RST signal in the circuit is also very important, especially when the circuit is turned on and the circuit freezes abnormally, the RST signal is needed to initialize or restart the circuit. In network communications, such as the TCP protocol, the RST signal is used to close a data packet received on a closed connection or to handle request timeouts. In addition, the RST signal is also used to prevent certain network attacks, such as RST attacks, in which malicious users forge TCP packets to abnormally disconnect legitimate connections.

[0150] S200, controlling the power supply capability of the current source according to the opening or closing of the transmission gate;

[0151] A transmission gate is a controllable switch circuit that can transmit both digital and analog signals. It is composed of a PMOS and an NMOS tube in parallel. It has a very low on-resistance (hundreds of ohms) and a very high off-resistance), so it is classified as an analog switch. The CMOS transmission gate uses the complementarity of PMOS and NMOS to control the on and off of the circuit through the control signal. This circuit is not only used to control the on and off of signals in digital circuits, but also used to transmit analog signals in analog circuits.

[0152] S300, adaptively adjusting the opening of the transmission gate according to the change of the feedback clock.

[0153] In a clock system, the frequency and stability of the clock signal are very important because they directly affect the performance and accuracy of the system. By applying clock feedback technology, the frequency and waveform of the clock signal can be monitored and controlled to ensure that it always remains within the set frequency and stability range. This can effectively improve the stability and reliability of the device.

[0154] Preferably, in S100, controlling the opening of the transmission gates of the first transmission module and the second transmission module according to the output of the RST signal generation module includes:

[0155] When the RST signal is at a high level, VCAL_P > VCAL_N, the first transmission gate (T1) is opened, and the fifth transmission gate (T5) is closed;

[0156] The logic control signal switches the opening of the transmission gate as the feedback clock changes, the voltage of VCAL_N is raised, and the voltage of VBP increases;

[0157] When the RST signal is at a low level, VCAL_P < VCAL_N, the fifth transmission gate (T5) is opened, and the first transmission gate (T1) is closed;

[0158] The logic control signal switches the opening of the transmission gate as the feedback clock changes, the voltage of VCAL_P is raised, and the VBN voltage is pulled down.

[0159] When the RST signal is at a high level, from Figure 4 Analysis shows that at this time, VCAL_P > VCAL_N, the first transmission gate (T1) 130 is opened, and the fifth transmission gate (T5) 140 is closed. From Fig. 9 It can be seen from the control signal logic circuit that at this time, the logic control signal will switch the opening of the transmission gate as the feedback clock (DIV_CLK) changes. Due to the coupling effect of the capacitor, the voltage of VCAL_N will be slowly raised, and the voltage of VBP will increase.

[0160] When the RST signal is at a low level, from Figure 6 Analysis shows that at this time, VCAL_P < VCAL_N, the fifth transmission gate (T5) 140 is opened, and the first transmission gate (T1) 130 is closed. Similarly, according to Fig. 9From the control signal logic circuit, it can be seen that at this time, the logic control signal will switch on the transmission gate as the feedback clock (DIV_CLK) changes. Due to the coupling effect of the capacitor, the voltage of VCAL_P will be slowly raised and the voltage of VBN will be pulled down. From the above analysis, it can be seen that when the feedback clock signal frequency is faster than the reference clock frequency, the voltages of VCAL_N and VCAL_P will be raised, and then the VBP voltage will increase, the VBN voltage will decrease, and the power supply capacity of the current source will be weakened; when the feedback clock signal is slow, the coupling effect of the capacitor on VCAL_N and VCAL_P in the charge pump dynamic calibration module will decrease, and the voltages of VCAL_N and VCAL_P will decrease, and then the VBP voltage will decrease, the VBN voltage will increase, and the power supply capacity of the current source will be enhanced, thereby realizing that the power supply capacity of the charge pump is automatically adjusted according to the change of the feedback clock signal.

[0161] Example 3

[0162] An electronic device comprises: a processor and a memory, wherein the memory is used to store computer program codes, and the computer program codes include computer instructions. When the processor executes the computer instructions, the electronic device executes a dynamic adjustment calibration circuit control method for a charge pump.

[0163] refer to Figure 8 , the electronic device 2 includes a processor 21, a memory 22, an input device 23, and an output device 24. The processor 21, the memory 22, the input device 23, and the output device 24 are coupled via a connector, and the connector includes various interfaces, transmission lines, or buses, etc., which are not limited in the embodiments of the present invention. It should be understood that in various embodiments of the present invention, coupling refers to mutual connection in a specific manner, including direct connection or indirect connection through other devices, for example, through various interfaces, transmission lines, buses, etc.

[0164] The processor 21 may be one or more graphics processing units (GPUs). When the processor 21 is a GPU, the GPU may be a single-core GPU or a multi-core GPU. Optionally, the processor 21 may be a processor group consisting of multiple GPUs, and the multiple processors are coupled to each other via one or more buses. Optionally, the processor may also be other types of processors, etc., which are not limited in the embodiments of the present invention.

[0165] The memory 22 can be used to store computer program instructions and various computer program codes including program codes for executing the scheme of the present invention. Optionally, the memory includes but is not limited to random access memory (RAM), read-only memory (ROM), erasable programmable read only memory (EPROM), or portable read only memory (CD-ROM), which is used for related instructions and data.

[0166] The input device 23 is used to input data and / or signals, and the output device 24 is used to output data and / or signals. The output device 24 and the input device 23 may be independent devices or an integrated device.

[0167] The present invention can dynamically adjust the power supply capacity of the charge pump according to the feedback of the feedback clock signal in real time, reduce the mismatch of the charge pump, further improve the accuracy of the phase-locked loop, and thus improve the locking ability of the circuit. By adjusting the power supply capacity of the charge pump, the present invention further reduces the power consumption of the circuit, reduces the heating of the circuit, and improves the safety and stability of the circuit.

[0168] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A dynamic adjustment and calibration circuit for a charge pump, characterized in that: include: Charge pump operational amplifier module and charge pump dynamic calibration module; The charge pump operational amplifier module is connected to the charge pump dynamic calibration module; The charge pump dynamic calibration module is used to adjust the power supply capacity of the charge pump according to the feedback clock signal; The charge pump operational amplifier module is used to adjust the current output by the PMOS current source and the NMOS current source; The charge pump dynamic calibration module includes: a first transmission module, a second transmission module, a first capacitor, a first PMOS tube and a second NMOS tube; The first transmission module is connected to the upper plate of the first capacitor; The second transmission module is connected to the upper plate of the first capacitor; The drain of the first PMOS tube is connected to the drain of the second NMOS tube; The gate of the second NMOS tube is connected to the upper plate of the first capacitor; The drain of the first PMOS tube and the drain of the second NMOS tube are connected to the upper plate of the first capacitor; The charge pump operational amplifier module includes: an eleventh PMOS tube, a twelfth PMOS tube, a thirteenth PMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube and a nineteenth PMOS tube; The drain of the eleventh PMOS tube is connected to the source of the twelfth PMOS tube and the source of the thirteenth PMOS tube; The drain of the twelfth PMOS tube is connected to the drain of the fourteenth NMOS tube and the drain of the fifteenth NMOS tube; The gate of the fifteenth NMOS tube is connected to the drain of the fourteenth NMOS tube; The source of the sixteenth NMOS tube is connected to the drain of the thirteenth PMOS tube; The drain of the seventeenth NMOS tube is connected to the gate of the sixteenth NMOS tube and the drain of the thirteenth PMOS tube; The gate of the eighteenth NMOS tube is connected to the drain of the seventeenth NMOS tube; The drain of the eighteenth NMOS tube is connected to the drain of the nineteenth PMOS tube; Also includes: a RST signal generating module; The RST signal generating module is connected to the charge pump operational amplifier module and the charge pump dynamic calibration module, and is used to compare the difference between VCAL_N and VCAL_P to generate an RST signal; The RST signal generating module includes: a Schmitt trigger inverter, a first NOT gate, a second NOT gate, a twenty-fifth PMOS tube, a twenty-sixth PMOS tube, a twenty-seventh PMOS tube, a twenty-eighth NMOS tube, a twenty-ninth NMOS tube, a thirtieth PMOS tube and a thirty-first PMOS tube; The drain of the twenty-fifth PMOS tube is connected to the source of the twenty-sixth PMOS tube and the twenty-seventh PMOS tube; The drain of the twenty-sixth PMOS tube is connected to the source of the twenty-ninth NMOS tube; The drain of the twenty-seventh PMOS tube is connected to the source of the twenty-eighth NMOS tube; The drain of the twenty-eighth NMOS tube and the drain of the twenty-ninth NMOS tube are grounded; The source of the 30th PMOS tube is connected to the source of the 31st PMOS tube; The drain of the thirty-first PMOS tube is connected to the input end of the Schmitt trigger inverter; The output end of the Schmitt trigger inverter is connected to the input end of the first NOT gate; The output end of the first NOT gate is connected to the input end of the second NOT gate.

2. A charge pump dynamic adjustment calibration circuit according to claim 1, characterized in that: The first transmission module includes: a first transmission gate, a second transmission gate, a third transmission gate, a fourth transmission gate, a third PMOS transistor, a fourth NMOS transistor, a fifth PMOS transistor, a sixth NMOS transistor and a second capacitor; The first transmission gate, the second transmission gate and the third transmission gate are connected in series; The input end of the first transmission gate is connected to the drain of the third PMOS tube; The gate of the fourth NMOS tube is connected between the output end of the first transmission gate and the input end of the second transmission gate; The output end of the fourth transmission gate is connected to the drain of the fifth PMOS tube, the drain of the sixth NMOS tube and one end of the second capacitor; The other end of the second capacitor is connected between the output end of the second transmission gate and the input end of the third transmission gate; The output end of the third transmission gate is connected to the upper plate of the first capacitor.

3. The dynamic adjustment and calibration circuit of a charge pump according to claim 1, characterized in that: The second transmission module includes: a fifth transmission gate, a sixth transmission gate, a seventh transmission gate, an eighth transmission gate, a seventh PMOS transistor, an eighth NMOS transistor, a ninth PMOS transistor, a tenth NMOS transistor and a third capacitor; The fifth transmission gate, the sixth transmission gate and the seventh transmission gate are connected in series; The input end of the fifth transmission gate is connected to the drain of the seventh PMOS tube; The gate of the eighth NMOS tube is connected between the output end of the fifth transmission gate and the input end of the sixth transmission gate; The output end of the eighth transmission gate is connected to the drain of the ninth PMOS tube, the drain of the tenth NMOS tube and one end of the third capacitor; The other end of the third capacitor is connected between the output end of the sixth transmission gate and the input end of the seventh transmission gate; The output end of the seventh transmission gate is connected to the upper plate of the first capacitor.

4. The dynamic adjustment and calibration circuit of a charge pump according to claim 1, characterized in that: Also includes: Bias current generating module; The bias current generating module is connected to the charge pump operational amplifier module and is used to generate a bias current in the circuit; The bias current generating module comprises: a 20th NMOS tube, a 21st NMOS tube, a 22nd PMOS tube, a 23rd PMOS tube and a 24th PMOS tube; The gate of the 20th NMOS tube is connected to the gate of the 21st NMOS tube; The drain of the 20th NMOS tube is connected to the source of the 21st NMOS tube; The source of the 20th NMOS tube is connected to the drain and gate of the 22nd PMOS tube; The source of the twenty-second PMOS tube is connected to the source of the twenty-third PMOS tube; The gate of the twenty-third PMOS tube is connected to the drain of the twenty-first NMOS tube; The drain of the twenty-third PMOS tube is connected to the source of the twenty-fourth PMOS tube; The drain of the twenty-fourth PMOS transistor is connected to the drain of the twenty-first NMOS transistor.

5. A method for controlling a dynamic adjustment and calibration circuit of a charge pump, applied to a dynamic adjustment and calibration circuit of a charge pump according to any one of claims 1 to 4, characterized in that: Comprising: Controlling the opening of the transmission gates of the first transmission module and the second transmission module according to the output of the RST signal generation module; Controlling the power supply capacity of the current source according to the opening or closing of the transmission gates; Adapting and adjusting the opening of the transmission gates according to the change of the feedback clock.

6. The method for controlling a dynamic adjustment and calibration circuit of a charge pump according to claim 5, characterized in that: The controlling the opening of the transmission gates of the first transmission module and the second transmission module according to the output of the RST signal generation module includes: When the RST signal is at a high level, VCAL_P > VCAL_N, the first transmission gate is opened, and the fifth transmission gate is closed; The logic control signal switches the opening of the transmission gate along with the change of the feedback clock, the voltage of VCAL_N is raised, and the voltage of VBP is increased; When the RST signal is at a low level, VCAL_P < VCAL_N, the fifth transmission gate is opened, and the first transmission gate is closed; The logic control signal switches the opening of the transmission gate along with the change of the feedback clock, the voltage of VCAL_P is raised, and the voltage of VBN is pulled down.

7. An electronic device, characterized in that: Comprising: A processor and a memory, the memory is used to store computer program code, the computer program code includes computer instructions, when the processor executes the computer instructions, the electronic device executes a method for controlling a dynamic regulation and calibration circuit of a charge pump as described in any one of claims 5 to 6.

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