Discrete device idss test method

Abstract

The application discloses a discrete device IDSS testing method, comprising the following steps: connecting a superimposed power source formed by multiple floating sources to the source and drain of a discrete device and initializing each floating source; performing FV operation on each floating source; after the FV operation on each floating source is completed and a corresponding stable time is waited, inserting MV operation on each floating source; if the MV operation result of the corresponding floating source is abnormal, closing all floating sources to reduce the time in the abnormal state and avoid heat accumulation from burning the probe. The application can protect the probe during the testing process and reduce the frequency of burning the probe.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an IDSS test method for discrete devices. Background Technology

[0002] The source-drain leakage current (IDSS) is a parameter that must be measured statically for discrete devices. The test schematic is shown below. Figure 1 As shown, the gate (G) and source (S) of the discrete device 101 of the bare die (die) to be tested, i.e., MOSFET, are shorted. A specific voltage is applied between the drain (D) and S by the power supply 102. The leakage current between its two ends is measured by the current measuring instrument 103 to detect whether there is an abnormality between D and S.

[0003] When the die under test requires a relatively high voltage, one testing method is to use multiple floating sources stacked together to provide the voltage. For example, if four floating sources are used to provide the voltage, the voltage supplied to the die under test can be up to four times that of a single floating source, thus achieving the purpose of high-voltage testing. The test circuit for power supply by stacking multiple floating sources is further explained below:

[0004] like Figure 2A The diagram shown is an actual test circuit diagram in the existing discrete device IDSS test method; the chip under test is the discrete device 201 in common drain mode, with the gate and source of the discrete device 201 shorted. In common drain mode, on the same wafer, the drain of each discrete device 201 is located on the back side, while the gate and drain are located on the front side.

[0005] The back of the discrete device 201 is fixed to the chuck 204. The superimposed power supply 202 is electrically connected to the chuck 204 and connected to the drain of the discrete device 201 through the chuck 204. The superimposed power supply 202 is connected to the source of the discrete device 201 through the corresponding probe 203.

[0006] Figure 2A In this configuration, the superimposed power supply 202 is composed of a first floating source 202a, a second floating source 202b, a third floating source 202c, and a fourth floating source 202d. The first floating source 202a and the second floating source 202b are connected between the drain of the corresponding chuck 204 and ground; the third floating source 202c and the fourth floating source 202d are connected between the source and ground. The gate and source of the discrete device 201 are shorted. The magnitudes of the first floating source 202a, the second floating source 202b, the third floating source 202c, and the fourth floating source 202d are controlled by FV operation.

[0007] like Figure 2B The diagram shown is another actual test circuit diagram in the existing discrete device IDSS test method; the chip under test is the discrete device 201a in the top drain mode, in which the source, drain and gate are all located on the front side of the wafer.

[0008] The superimposed power supply 202 is connected to the drain of the discrete device 201a via the corresponding probe 203. The superimposed power supply 202 is also connected to the source of the discrete device 201a via the corresponding probe 203. The gate and source of the discrete device 201a are shorted. The first floating source 202a and the second floating source 202b are connected between the drain and ground; the third floating source 202c and the fourth floating source 202d are connected between the source and ground.

[0009] In existing methods, during the testing of high-voltage IDSS using multiple floating sources, taking a scenario with four floating sources as an example, three floating sources are first used to provide a base voltage, and then the last floating source is used for FV-MI measurement. FV represents the excitation voltage provided, MI represents the measured current, and FV-MI means providing the excitation voltage to measure the current. Figure 3 As shown in Figure 301, the current changes over time when measuring leakage current in the existing discrete device IDSS test method. It can be seen from the curve 301 that the IDSS is relatively large at the beginning, and gradually decreases and tends to stabilize as time increases.

[0010] Considering the product differences, sufficient force time must be allowed during mass production testing to ensure current stability. During this period, if the die being tested cannot withstand the high voltage, the current in the test circuit will increase. If there is aluminum shavings or other contaminants at the contact point between the probe tip and the PAD, causing increased resistance and voltage drop, the high voltage and high current will continue to heat up and melt more aluminum shavings and other contaminants, further increasing the resistance and voltage drop at the probe tip. Under this positive feedback, the resistance at the probe tip becomes larger and larger, and the voltage drop becomes higher and higher, accumulating more and more heat. The formula for calculating the accumulated heat is: Q = U * I * t, where Q represents heat, U represents voltage, I represents current, and t represents time. The increase in accumulated heat will eventually cause the probe tip of the test pin to melt and burn out.

[0011] like Figure 4 The diagram shows a flowchart of an existing IDSS test method for discrete devices; the existing IDSS test method for discrete devices includes the following steps:

[0012] Step S101: Floating source 1 / 2 / 3 / 4 init, where init indicates initialization. Floating source 1 / 2 / 3 / 4 represents four floating sources. Floating source 1 corresponds to... Figure 2AThe first floating source 202a is shown, the second floating source 202b is shown, the third floating source 202c is shown, and the fourth floating source 202d is shown.

[0013] Step S102, Floating Source 1 / 2 / 3FV. Floating Source 1 / 2 / 3FV indicates that the first to third floating sources are subjected to FV operation. The FV operation means providing an excitation voltage to the floating source.

[0014] Step S103, Floating Source 4FV. Floating Source 4FV indicates that an FV operation is performed on the fourth floating source.

[0015] Step S104, wait t0 ms, where t0 represents the settling time after floating source 4FV and before subsequent floating source 4MI. The settling time can be set according to the actual characteristics of the product being measured, for example, according to the settling time required by IDSS corresponding to curve 301.

[0016] Step S105, Floating Source 4MI, indicates that an MI operation is performed on the fourth floating source. The MI operation involves measuring the current of the fourth floating source.

[0017] Step S106, Floating source 1 / 2 / 3 / 4off, indicates that all the floating sources are turned off.

[0018] Step S107, output test value, means outputting the test result, which is the result of performing the MI operation on the fourth floating source.

[0019] As mentioned earlier, considering product variability, sufficient force time must be allowed during mass production testing to ensure current stability. During this period, if the tested die cannot withstand the high voltage, the test circuit current will increase, eventually leading to increased voltage drop at the probe tip and increased resistance. This creates a positive feedback loop, ultimately causing the probe tip to melt and burn out. Figure 5 The image shown is a photograph of the probe when the existing IDSS test method for discrete devices burns out. Figure 5 The probe in the middle is marked 203a, which shows that the probe in region 302 is burned. Summary of the Invention

[0020] The technical problem to be solved by the present invention is to provide an IDSS test method for discrete devices that can protect the probes during the test and reduce the frequency of probe burn-out.

[0021] To solve the above-mentioned technical problems, the discrete device IDSS testing method provided by the present invention includes the following steps:

[0022] A superimposed power supply formed by multiple floating sources is connected between the source and drain of a discrete device and each floating source is initialized. The connection structure between the superimposed power supply and the source or drain of the discrete device includes probes. The superimposed power supply is used to provide the source-drain voltage required for the IDSS test of the discrete device.

[0023] Perform an FV operation on each of the floating sources, whereby the FV operation represents providing an excitation voltage to the floating source.

[0024] After the FV operation of each floating source is completed and a corresponding stabilization time is waited, the MV operation of each floating source is inserted, which represents the measurement of the voltage of the floating source; if the MV operation result of the floating source of the corresponding block is abnormal, all floating sources are turned off to reduce the time in abnormal state and avoid heat accumulation that could burn out the probe.

[0025] A further improvement is that the settling time for each of the floating sources is less than or equal to 1 ms.

[0026] A further improvement is that the method for determining abnormal results of the MV operation of the floating source is as follows:

[0027] If the absolute value of (VF-VC) is greater than the first set value, the result of the MV operation of the floating source is considered abnormal.

[0028] Alternatively, if the absolute value of (VF-VC) is greater than the ratio of VF, the MV operation result of the floating source is considered abnormal.

[0029] VF represents the excitation voltage provided by the FV operation.

[0030] VC represents the measured voltage obtained by the MV operation.

[0031] A further improvement is that the first setting value is no greater than 10V; and the second setting value is no greater than 5%.

[0032] A further improvement is that the number of floating sources is N, where N is greater than or equal to 2.

[0033] The floating sources in blocks 1 through N-1 are used to provide a base voltage for the source drain voltage.

[0034] The Nth floating source is used to implement FV-MI measurement, where FV represents the excitation voltage and MI represents the current to be measured. FV-MI means providing an excitation voltage to measure the current.

[0035] A further improvement is that the Nth floating source is the last floating source to perform the FV operation.

[0036] After the MV operation of the Nth floating source is completed, if the MV operation of the Nth floating source is normal, then after waiting for a second stabilization time, the MI operation is performed, which is to measure the current of the Nth floating source.

[0037] A further improvement is that the process of performing the FV operation and the MV operation on the floating source in each of the 1st to N-1th blocks includes:

[0038] The FV operation is performed sequentially on each of the floating sources, and a corresponding MV operation is inserted after each FV operation is completed and a corresponding stabilization time is waited; if the MV operation result of the current block of floating sources is normal, the FV operation of the next block of floating sources is performed; if the MV operation result of the current block of floating sources is abnormal, all floating sources are turned off.

[0039] A further improvement is that the process of performing the FV operation and the MV operation on the floating source in each of the 1st to N-1th blocks includes:

[0040] After completing the FV operation on multiple floating sources and waiting for a corresponding stabilization time, the MV operation on each of the multiple floating sources is then inserted; if the MV operation of each of the floating sources is normal, the FV operation of the floating source in the subsequent block is performed; if the MV operation result of any of the multiple floating sources is abnormal, all the floating sources are turned off.

[0041] A further improvement is that the process of performing the FV operation and the MV operation on the floating source in each of the 1st to N-1th blocks includes:

[0042] After completing the FV operation on all floating sources from the 1st to the (N-1th)th blocks and waiting for a corresponding stabilization time, the MV operation is performed on each of the floating sources from the 1st to the (N-1th)th blocks. If the MV operation results of all floating sources from the 1st to the (N-1th)th blocks are normal, the FV operation on the Nth floating source is performed. If the MV operation results of any of the floating sources from the 1st to the (N-1th)th blocks are abnormal, all floating sources are shut down.

[0043] A further improvement is that when the MV operation result of the corresponding floating source is abnormal, the abnormal result of the MV operation is also assigned a value.

[0044] A further improvement is that the values ​​assigned to the abnormal results of the MV operation corresponding to the first to N-1th floating sources are different from the values ​​assigned to the abnormal results of the MV operation of the Nth floating source.

[0045] A further improvement is that the abnormal results of the MV operation corresponding to each of the floating sources in blocks 1 to N-1 are assigned the same or different values.

[0046] A further improvement is that the second stabilization time is 2ms to 2000ms.

[0047] A further improvement is that the base voltage provided by the floating sources in blocks 1 to N-1 is set as follows:

[0048] While ensuring that the source-drain voltage provided by the floating sources from the first to the Nth blocks meets the requirements, the base voltage is set in a manner close to the lower limit of the allowable range of the base voltage.

[0049] A further improvement is that, during the IDSS test, the gate and source of the discrete device are shorted.

[0050] The superimposed power supply is connected to the source of the discrete device through the corresponding probe;

[0051] The discrete device is in common-drain mode, with its back side fixed to a chuck. The superimposed power supply is electrically connected to the chuck and connected to the drain of the discrete device through the chuck; or, the discrete device is in top-drain mode, with the superimposed power supply connected to the drain of the discrete device through the corresponding probe.

[0052] A further improvement is that all the floating sources are turned off after the FV-MI measurement is completed.

[0053] After all floating sources are turned off, output the measured MI test results.

[0054] The MI test results include normal MI test results and abnormal MI test results; the normal MI test results are the results of the FV-MI measurement; the abnormal MI test results are the values ​​assigned to the abnormal results of the MV operation when the MV operation result is abnormal.

[0055] When using a superimposed power supply formed by multiple floating sources to provide the source-drain voltage required for IDSS testing of discrete devices, an MV operation is inserted after the FV operation of each floating source. The MV operation can promptly detect whether there is any abnormality in the corresponding floating source after the FV operation, and shut down all floating sources in time when an abnormality is detected. Since this invention can detect and eliminate abnormal states in time, it can prevent the heat generated by large current and large voltage from accumulating in the probe and burning it out when the abnormal state lasts for a long time or remains in an abnormal state throughout the entire IDSS test. Therefore, this invention can protect the probe during the test and reduce the frequency of probe burning. Attached Figure Description

[0056] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0057] Figure 1 This is the circuit schematic for IDSS testing of discrete components;

[0058] Figure 2A This is a practical test circuit diagram in the existing IDSS test method for discrete devices;

[0059] Figure 2B This is another practical test circuit diagram in the existing IDSS test method for discrete devices;

[0060] Figure 3 This is the curve of current change over time when measuring leakage current in the existing IDSS test method for discrete devices;

[0061] Figure 4 This is a flowchart of the existing IDSS test method for discrete devices;

[0062] Figure 5 These are probe photos taken when the probe burns out during the existing IDSS testing method for discrete devices.

[0063] Figure 6 This is a flowchart of the discrete device IDSS test method according to an embodiment of the present invention;

[0064] Figure 7 This is a flowchart of the discrete device IDSS test method according to a preferred embodiment of the present invention;

[0065] Figure 8 This is a flowchart of the discrete device IDSS test method according to a preferred embodiment of the present invention. Detailed Implementation

[0066] like Figure 6 The diagram shows a flowchart of the discrete device IDSS test method according to an embodiment of the present invention; the discrete device IDSS test method according to an embodiment of the present invention includes the following steps:

[0067] Step S1: Connect the superimposed power supply 202 formed by multiple floating sources to the source and drain of the discrete device 201 and initialize each floating source. The connection structure between the superimposed power supply 202 and the source or drain of the discrete device 201 includes a probe 203. The superimposed power supply 202 is used to provide the source and drain voltage required for the IDSS test of the discrete device 201.

[0068] In this embodiment of the invention, the number of floating sources is N, where N is greater than or equal to 2.

[0069] The floating sources in blocks 1 through N-1 are used to provide a base voltage for the source drain voltage.

[0070] The Nth floating source is used to implement FV-MI measurement, where FV represents the excitation voltage and MI represents the current to be measured. FV-MI means providing an excitation voltage to measure the current.

[0071] In some embodiments, N equals 4. Figure 7 In some preferred embodiments of the present invention, N is described as equal to 4.

[0072] Taking N=4 as an example, please refer to the same connection relationship between the superimposed power supply 202 and the discrete component 201. Figure 2A As shown or referenced Figure 2B As shown.

[0073] In some embodiments, such as Figure 2A As shown, the chip under test is the discrete device 201 in common-drain mode, and the gate and source of the discrete device 201 are shorted.

[0074] The back of the discrete device 201 is fixed to the chuck 204. The superimposed power supply 202 is electrically connected to the chuck 204 and connected to the drain of the discrete device 201 through the chuck 204. The superimposed power supply 202 is connected to the source of the discrete device 201 through the corresponding probe 203.

[0075] Figure 2A In this configuration, the superimposed power supply 202 is composed of a first floating source 202a, a second floating source 202b, a third floating source 202c, and a fourth floating source 202d. The first floating source 202a and the second floating source 202b are connected between the drain-corresponding chuck 204 and ground; the third floating source 202c and the fourth floating source 202d are connected between the source and ground. The gate and source of the discrete device 201 are shorted.

[0076] In some embodiments, it can also be: such as Figure 2BAs shown, the chip under test is the discrete device 201a in top-drain mode. The superimposed power supply 202 is connected to the drain of the discrete device 201a through the corresponding probe 203. The superimposed power supply 202 is also connected to the source of the discrete device 201a through the corresponding probe 203. The gate and source of the discrete device 201a are shorted. Specifically, the first floating source 202a and the second floating source 202b are connected between the drain and ground; the third floating source 202c and the fourth floating source 202d are connected between the source and ground.

[0077] exist Figure 7 In some preferred embodiments of the present invention shown, step S1 is implemented through step S201, which includes: `floating source 1 / 2 / 3 / 4init`, where `init` indicates initialization. Floating source 1 / 2 / 3 / 4 represents four floating sources. Floating source 1 corresponds to... Figure 2A The first floating source 202a is shown, the second floating source 202b is shown, the third floating source 202c is shown, and the fourth floating source 202d is shown.

[0078] exist Figure 8 In some preferred embodiments of the present invention shown, the same step S201 is also used.

[0079] Step S2: Perform an FV operation on each of the floating sources, whereby the FV operation means providing an excitation voltage to the floating source.

[0080] Step S3: After the FV operation of each floating source is completed and a corresponding stabilization time is waited, the MV operation of each floating source is inserted. The MV operation represents the measurement of the voltage of the floating source. If the MV operation result of the floating source of the corresponding block is abnormal, all floating sources are turned off to reduce the time in the abnormal state and avoid heat accumulation that could burn out the probe 203.

[0081] In this embodiment of the invention, the settling time corresponding to each floating source should be set according to the actual characteristics of the product being measured. In some specific embodiments, the settling time corresponding to each floating source is less than or equal to 1 ms.

[0082] In some embodiments, the method for determining anomalies in the MV operation result of the floating source is as follows:

[0083] If the absolute value of (VF-VC) is greater than a first set value, the MV operation result of the floating source is considered abnormal. VF represents the excitation voltage provided by the FV operation. VC represents the measured voltage obtained by the MV operation. The first set value can be selected according to the actual situation; for example, the first set value is not greater than 10V.

[0084] In some embodiments, the method for determining whether the MV operation result of the floating source is abnormal can be as follows: if the ratio of the absolute value of (VF-VC) to VF is greater than a second preset value, then the MV operation result of the floating source is considered abnormal. The second preset value can be selected according to the actual situation, for example, the second preset value is not greater than 5%.

[0085] In this embodiment of the invention, the Nth floating source is the last floating source to perform the FV operation.

[0086] After the MV operation of the Nth floating source is completed, if the MV operation of the Nth floating source is normal, an MI operation is performed after waiting for a second settling time. The MI operation involves measuring the current of the Nth floating source. The second settling time is the waiting time before the formal measurement, and the second settling time should be set according to the actual characteristics of the product being measured. In some specific embodiments, the second settling time is 2ms to 2000ms. Figure 7 In some preferred embodiments shown, steps S2 and S3 are implemented through steps S301 and S302, the specific steps of which will be described in detail later. Figure 8 In some preferred embodiments shown, steps S2 and S3 are implemented by steps S301a and S302, and the specific steps of steps S301a and S302 will be described in detail later.

[0087] In this embodiment of the invention, the base voltage provided by the floating source from the 1st to the (N-1th)th blocks is set as follows:

[0088] While ensuring that the source-drain voltages provided by the floating sources from Block 1 to Block N meet the requirements, the base voltage is set in a manner close to the lower limit of the allowable range of the base voltage. This lower base voltage helps reduce testing risks during the FV and MV operations of the floating sources from Block 1 to Block N-1, for example... Figure 7 Step S301 or Figure 8 The step S301a shown reduces testing risk.

[0089] In some embodiments, the process of performing the FV operation and the MV operation on the floating sources in blocks 1 to N-1 includes:

[0090] The FV operation is performed sequentially on each of the aforementioned floating sources, and after each FV operation is completed and a corresponding stabilization time is waited, a corresponding MV operation is inserted. If the MV operation result of the current block of floating sources is normal, the FV operation of the next block of floating sources is performed; if the MV operation result of the current block of floating sources is abnormal, all floating sources are shut down. This process can be implemented using... Figure 8 In the preferred embodiment shown, step S301a is implemented.

[0091] In some embodiments, the process of performing the FV operation and the MV operation on the floating sources in blocks 1 to N-1 includes:

[0092] After completing the FV operation on multiple floating sources (greater than or equal to 2 and less than or equal to N-1) and waiting for a corresponding stabilization time, the MV operation is then inserted for each of the multiple floating sources. If the MV operation of each floating source block is normal, the FV operation of the floating sources in subsequent blocks is performed. If the MV operation of any of the multiple floating sources is abnormal, all floating sources are shut down. Further, in some preferred embodiments, the process of performing the FV operation and the MV operation on each of the floating sources in blocks 1 to N-1 includes:

[0093] After completing the FV operation on all floating sources from the 1st to the (N-1th)th blocks and waiting for a corresponding stabilization time, the MV operation is performed on each of the floating sources from the 1st to the (N-1th)th blocks. If the MV operation results of all floating sources from the 1st to the (N-1th)th blocks are normal, then the FV operation on the Nth floating source is performed. If the MV operation result of any of the floating sources from the 1st to the (N-1th)th blocks is abnormal, then all floating sources are shut down. This process can be implemented using... Figure 7 In the preferred embodiment shown, step S301 is implemented.

[0094] In this embodiment of the invention, when the MV operation result of the corresponding floating source is abnormal, the method further includes assigning a value to the abnormal result of the MV operation. For the steps of assigning a value to the abnormal result of the MV operation, please refer to [reference needed]. Figure 7 In step S214, set the floating source 4MI to false value.

[0095] In some embodiments, the values ​​assigned to the abnormal results of the MV operation corresponding to the first to N-1 floating sources are different from the values ​​assigned to the abnormal results of the MV operation of the Nth floating source. This allows the basic condition of the product under test to be determined based on the different assigned values.

[0096] In some embodiments, the abnormal results of the MV operation corresponding to each of the floating sources in blocks 1 to (N-1) are assigned the same value. In this case, the floating sources in blocks 1 to (N-1) are assigned one value, and the floating source in block N is assigned another value, thus allowing the basic condition of the product under test to be determined. Alternatively, in some embodiments, the abnormal results of the MV operation corresponding to each of the floating sources in blocks 1 to (N-1) can be assigned different values.

[0097] In this embodiment of the invention, after the FV-MI measurement is completed, all floating sources are turned off. For the steps of turning off all floating sources, please refer to [link to relevant documentation]. Figure 7 Step S212, floating source 1 / 2 / 3 / 4off.

[0098] After all floating sources are turned off, output the MI test results. Please refer to the following steps for details. Figure 7 Step S213, output test value.

[0099] The MI test results include normal MI test results and abnormal MI test results; the normal MI test results are the results of the FV-MI measurement, i.e. Figure 7 The measurement result of step 211; the MI anomaly test result is the assigned value of the abnormal result of the MV operation when the MV operation result is abnormal, that is Figure 7 The result of the assignment in step S214.

[0100] When using a superimposed power supply 202 formed by multiple floating sources to provide the source-drain voltage required for IDSS testing of discrete device 201, an MV operation is inserted after the FV operation of each floating source. The MV operation can detect in a timely manner whether there is any abnormality in the corresponding floating source after the FV operation, and shut down all floating sources in a timely manner when an abnormality is detected. Since the embodiment of the present invention can detect and eliminate abnormal states in a timely manner when they occur, it can prevent the heat generated by large current and large voltage from accumulating in the probe 203 and burning out the probe 203 when the abnormal state lasts for a long time or remains in an abnormal state throughout the entire IDSS test. Therefore, the embodiment of the present invention can protect the probe 203 during the test and reduce the frequency of probe burning.

[0101] The following is combined Figure 7 The flowcharts illustrating some preferred embodiments of the discrete device IDSS test method of the present invention provide a further detailed description of the embodiments of the present invention:

[0102] like Figure 7 As shown, in some preferred embodiments, the discrete device IDSS test method includes the following steps:

[0103] Step S201, Floating source 1 / 2 / 3 / 4 init. This completes the process. Figure 6 Step S1 in the process. Figure 7 In the corresponding preferred embodiment, N equals 4 as an example for explanation.

[0104] Steps S301 and S302 are used to complete Figure 6 Steps S2 and S3 are explained in detail below:

[0105] Step S301 includes the following steps:

[0106] Step S202, Floating Source 1 / 2 / 3FV. Floating Source 1 / 2 / 3FV indicates that FV operation is performed on the first to third floating sources.

[0107] Step S203, wait t1 ms. This indicates that after the FV operation of the three floating sources is completed, a corresponding stabilization time is waited. wait means waiting, t1 means the stabilization time after the FV operation of floating sources 1 / 2 / 3, and ms is the unit of time.

[0108] Step S204, Floating Source 1 / 2 / 3MV, indicates that MV operation is performed on the first to third floating sources.

[0109] Step S205, "normal", indicates that the MV operation results of the first to third floating sources are normal. If the MV operation results of the first to third floating sources are normal, proceed to the next step S206. If the MV operation results of the first to third floating sources are abnormal (i.e., "no"), proceed to the next step S214.

[0110] Step S302 includes the following steps:

[0111] Step S206, Floating Source 4FV. Floating Source 4FV indicates that an FV operation is performed on the fourth floating source.

[0112] Step S207, wait t2 ms. This indicates the stabilization time after the FV operation of the fourth floating source is completed. t2 represents the stabilization time after the FV operation of the fourth floating source. t2 can be set using the same rules as t1.

[0113] Step S208, Floating Source 4MV, indicates that an MV operation is performed on the fourth floating source.

[0114] Step S209, "normal", indicates that the MV operation result of the fourth floating source is determined to be normal. If the MV operation result of the fourth floating source is normal, then proceed to the next step S210. If the MV operation result of the fourth floating source is abnormal, i.e., "no", then proceed to the next step S214.

[0115] After step S302 is completed, the MI measurement in the FV-MI measurement is then performed, including:

[0116] Step S210, wait t0 ms, means waiting for the second stabilization time, where t0 represents the second stabilization time.

[0117] Step S211, Floating Source 4MI, indicates that the MI operation is performed on the fourth floating source.

[0118] Step S212, Floating source 1 / 2 / 3 / 4off, indicates that all the floating sources are turned off.

[0119] Step S213, output test value, indicates the output test result. Under normal circumstances, step S214 will not be performed, so the test result output in step S213 is the result of performing the MI operation on the fourth floating source.

[0120] When an exception occurs during the MV operation, step S214, "set floating source 4MI false value", will be performed. This means that the MI test failure result of the floating source in the fourth block is set. This result is assigned based on the exception result of the MV operation of the floating source in the corresponding block.

[0121] Figure 7 In a preferred embodiment, the corresponding MV operation is performed after the floating sources 1 / 2 / 3 have completed the FV operation. This approach can be further adopted in products with a high risk of needle burn-in. Figure 8 The preferred embodiment of the present invention shown, and Figure 7 The difference between the corresponding preferred embodiment method and the following is that: Figure 8 The preferred embodiment of the present invention replaces step S301a with the method described above. Figure 7 Step S301 in the process is further explained as follows:

[0122] Step S301a includes:

[0123] Step S202a, Floating Source x FV. Floating Source x FV indicates that an FV operation is performed on the floating source described in the x-th block. x is one of 1 to 3.

[0124] Step S203a, wait tx ms. This indicates that the FV operation of the floating source in the x-th block is completed and a corresponding settling time is waited for. tx represents the settling time after the FV operation of the floating source in the x-th block.

[0125] Step S204a, Floating source x MV, indicates that an MV operation is performed on the floating source described in the xth block.

[0126] Step S205a, "normal", indicates that the MV operation result of the floating source in block x is determined to be normal. If the MV operation result of the floating source in block x is normal, the subsequent steps are performed. If the MV operation result of the floating source in block x is abnormal, i.e., "no", the subsequent step S214 is performed.

[0127] Step S303 indicates that the value of x is changed and steps S202a to S205a are repeated. Taking x changing from 1 to 3 as an example, in step S205a, if the MV operation result of the floating source in the xth block is normal, when x is 1 or 2, the subsequent step corresponds to step S202a after x is added by 1; if x is 3, the subsequent step is step S206.

[0128] In this embodiment of the invention, during the actual mass production test of high voltage IDSS, two detection steps are added to the program. After an anomaly is detected, the voltage source force is interrupted in time, which can reduce the force time in time and thus effectively reduce the frequency of needle burn-out.

[0129] Taking the use of 4 floating sources as an example, specifically, after the 3 floating sources force the base voltage, wait for a short time t1, and then measure whether the voltage of the 3 floating sources can be maintained. If it can be maintained, continue to the next step of FV-MI. If the voltage cannot be maintained, it means that there is an abnormality in the die under test. The test is interrupted in time, and a failure value, i.e. an abnormal value, is assigned to the die under test.

[0130] After the FV operation in FV-MI is completed, wait a very short time t2 and then check the voltage of the fourth floating source again. If an abnormality is detected, interrupt the test in time and assign a fail value to the die under test. If no abnormality is detected, continue to maintain the force value and wait for a sufficient time t0 to ensure that the leakage current is stable before taking the normal measurement value as the test value of the die under test.

[0131] In this embodiment of the invention, based on the heat formula: Q=U*I*t, it can be seen that when an IDSS test is performed with N floating sources providing high voltage (greater than or equal to 2), the time under abnormal conditions can be reduced by adding two detection steps in advance, thereby avoiding the continuous accumulation of heat that could cause the needle to burn.

[0132] If the product has particularly poor pressure resistance or the probe card tip is particularly fine, can it be used? Figure 8 The preferred embodiment method shown can measure the voltage after waiting for a short time (tx) each time a voltage is forced by a floating source and make a judgment according to the same logic, thereby avoiding leakage abnormalities under high voltage and further preventing needle burnout.

[0133] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. An integrated device small signal (IDSS) test method, comprising: The method comprises the following steps: connecting a plurality of floating sources to the source and drain of a discrete device and initializing each of the floating sources, wherein the connection between the superimposed source and the source or drain of the discrete device comprises a probe, and the superimposed source is used to provide a source-drain voltage required for IDSS testing of the discrete device; performing an FV operation on each of the floating sources, wherein the FV operation represents providing an excitation voltage to the floating source; after the FV operation on each of the floating sources is completed and a corresponding stabilization time is waited, an MV operation is inserted, wherein the MV operation represents measuring the voltage of the floating source; if the MV operation result of the corresponding floating source is abnormal, all the floating sources are turned off to reduce the time in the abnormal state and avoid the probe from being burned by heat accumulation; the number of the floating sources is N, and N is greater than or equal to 2; the first to the N-1 floating sources are used to provide a basic voltage for the source-drain voltage; the N floating source is used to implement FV-MI measurement, wherein FV represents providing an excitation voltage, MI represents measuring a current, and FV-MI represents providing an excitation voltage to measure a current; the N floating source is the last floating source to perform the FV operation; after the MV operation on the N floating source is completed, if the MV operation result of the N floating source is normal, an MI operation is performed after a second stabilization time is waited, wherein the MI operation represents measuring the current of the N floating source.

2. The discrete device IDSS test method of claim 1, wherein: The stabilization time corresponding to each of the floating sources is less than or equal to 1 ms.

3. The discrete device IDSS test method of claim 1, wherein: The method for judging whether the MV operation result of the floating source is abnormal comprises: if the absolute value of (VF-VC) is greater than a first set value, it is considered that the MV operation result of the floating source is abnormal; or if the ratio of the absolute value of (VF-VC) to VF is greater than a second set value, it is considered that the MV operation result of the floating source is abnormal; VF represents the excitation voltage provided by the FV operation; VC represents the measurement voltage measured by the MV operation.

4. The discrete device IDSS test method of claim 3, wherein: The first set value is not greater than 10 V, and the second set value is not greater than 5%.

5. The discrete device IDSS test method of claim 1, wherein: The flow of performing the FV operation and the MV operation on each of the first to the N-1 floating sources comprises: the FV operation is sequentially performed on each of the floating sources, and after the FV operation on each of the floating sources is completed and a corresponding stabilization time is waited, a corresponding MV operation is inserted; if the MV operation result of the current floating source is normal, the FV operation on the next floating source is performed; if the MV operation result of the current floating source is abnormal, all the floating sources are turned off.

6. The discrete device IDSS test method of claim 1, wherein: The flow of performing the FV operation and the MV operation on each of the first to the N-1 floating sources comprises: After the FV operation of each of the plurality of floating sources is completed and a corresponding stable time is waited, the MV operation of each of the plurality of floating sources is inserted; if the MV operation of each of the plurality of floating sources is normal, the FV operation of the next floating source is performed; if the MV operation of the plurality of floating sources is abnormal, all the floating sources are closed.

7. The discrete device IDSS test method of claim 6, wherein: The process of performing the FV operation and the MV operation on each of the first to the N-1th floating sources comprises: After the FV operation of each of the first to the N-1th floating sources is completed and a corresponding stable time is waited, the MV operation of each of the first to the N-1th floating sources is performed; if the MV operation of each of the first to the N-1th floating sources is normal, the FV operation of the Nth floating source is performed; if the MV operation of the first to the N-1th floating sources is abnormal, all the floating sources are closed.

8. The discrete device IDSS test method of claim 1 or 6 or 7, wherein: When the MV operation of the corresponding floating source is abnormal, the abnormal result of the MV operation is assigned.

9. The discrete device IDSS test method of claim 8, wherein: The abnormal result of the MV operation of the first to the N-1th floating sources and the abnormal result of the MV operation of the Nth floating source are assigned different values.

10. The discrete device IDSS test method of claim 9, wherein: The abnormal result of the MV operation of each of the first to the N-1th floating sources is assigned the same or different value.

11. The discrete device IDSS test method of claim 1, wherein: The second stable time is 2ms to 2000ms.

12. The discrete device IDSS test method of claim 1, wherein: The first to the N-1th floating sources provide the base voltage in the following manner: Under the condition that the source-drain voltage provided by the first to the Nth floating sources meets the requirements, the base voltage is set in a manner close to the lower limit of the allowed range of the base voltage.

13. The discrete device IDSS test method of claim 1, wherein: During the IDSS test, the gate and the source of the discrete device are shorted; The superimposed power supply connects the source of the discrete device through the corresponding probe; The discrete device is in a common-drain mode, the back of the discrete device is fixed on a chuck, the superimposed power supply is electrically connected to the chuck and connects the drain of the discrete device through the chuck; or, the discrete device is in a top-drain mode, the superimposed power supply connects the drain of the discrete device through the corresponding probe.

14. The discrete device IDSS test method as described in claim 8, characterized in that: After the FV-MI measurement is completed, all the floating sources are closed; After all the floating sources are closed, the measured MI test result is outputted; The MI test result comprises a normal MI test result and an abnormal MI test result; the normal MI test result is the result of the FV-MI measurement; the abnormal MI test result is the assignment of the abnormal result of the corresponding MV operation when the MV operation result is abnormal.

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