Data normalization RISC-V instruction set extension method and hardware acceleration device

Abstract

The present invention discloses a data normalization RISC‑V instruction set extension method and a hardware acceleration device. The NORM instruction directly and efficiently implements data normalization at the hardware level, avoiding the inefficiency of the basic instruction sequence. The extended instruction calculation device includes a comparator, an iteration module, a MAX / MIN module and an operation unit, and uses hardware acceleration to complete the calculation of the normalization formula. The iteration module simplifies the calculation process through extreme value registers. The invention significantly improves the data calculation efficiency, reduces the code complexity, power consumption and memory overhead, and enhances the versatility of the instruction set. Finally, the extended instruction calculation device is integrated into the RISC‑V processor core to achieve efficient data normalization acceleration.

Description

Technical Field

[0001] The present invention relates to the technical fields of machine learning, image processing and signal processing, and in particular to a data normalization RISC-V instruction set extension method and a hardware acceleration device for data normalization RISC-V instruction set extension. Background Art

[0002] In data-intensive fields such as machine learning, image processing, and signal processing, data normalization is a very common and important preprocessing step. The purpose of data normalization is to map the data to a smaller interval, such as [0,1] or [-1,1], thereby eliminating the influence of data of different dimensions and improving the accuracy and convergence speed of model training.

[0003] RISC-V is an open source instruction set architecture based on the principle of "reduced instruction set (RISC)". The instruction set is the operating specification that the CPU can perform, which defines how to perform operations and helps the CPU run more efficiently through optimized design. It is a set of program instruction sets between software and underlying hardware. Compared with most instruction sets, the RISC-V instruction set can be used freely for any purpose, allowing anyone to design, manufacture and sell RISC-V chips and software. In the existing RISC-V instruction set, there is a lack of instructions specifically for data normalization. This preprocessing operation usually needs to be completed through a series of basic instructions, including data loading, arithmetic calculations (such as subtraction and multiplication), conditional branches, etc.

[0004] This implementation method based on the basic instruction set has the following major problems: low execution efficiency, requiring multiple basic instruction sequences to complete normalization, resulting in too many processor execution cycles, especially when processing large-scale data sets, the inefficiency problem is more prominent. The code complexity is high, and programmers need to manually combine multiple basic instructions to achieve normalization, which increases the complexity of coding and maintenance. Multiple data loading, storage, and intermediate result calculations will result in additional power consumption, and additional storage space needs to be pre-allocated, increasing memory overhead. Therefore, it is urgent to develop a new method to efficiently support data normalization processing at the hardware level to improve the performance and energy efficiency of the RISC-V architecture in these data-intensive applications and meet the growing computing needs. Summary of the invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a data normalization RISC-V instruction set extension method, which can greatly improve the computational efficiency of data normalization while reducing code complexity, power consumption and memory overhead, and enhancing the versatility of the RISC-V instruction set.

[0006] The technical solution of the present invention is: this data normalization RISC-V instruction set extension method, the RISC-V processor adopts a five-stage pipeline structure, which mainly includes:

[0007] (1) In the instruction fetch stage, the RISC-V processor pre-fetches the instruction with the corresponding data normalization stored in the instruction register according to the address generated by the instruction counter PC;

[0008] (2) In the decoding stage, the instruction signal is parsed in the decoding module by analyzing the encoding of func7 and func3 to parse the corresponding instruction function and generate the corresponding control signal;

[0009] (3) In the execution phase, the data is first taken out from the data memory by the load storage unit LSU module, and then the data is passed to the data normalization extension instruction calculation module according to the control signal generated by the Nrom instruction in the decoding phase. Finally, according to the formula

[0010] ,

[0011] Execute the normalization process and write the normalization result back to the corresponding destination register.

[0012] The RISC-V processor of the present invention adopts a five-stage pipeline structure. In the instruction fetching stage, the processor pre-fetches the corresponding data normalization instruction stored in the instruction register according to the address generated by the instruction counter. In the decoding stage, the instruction signal is parsed out of the corresponding instruction function by analyzing the encoding of Opcode, func7 and func3 in the decoding module, and a corresponding control signal is generated to enter the execution stage. Before executing the normalization instruction Nrom, the data is first taken out from the data storage device through the loading storage unit LSU module, and then according to the control signal generated by the Nrom instruction, the data is transferred to the data normalization extension instruction calculation device to execute the normalization process, and finally the normalization result is written back to the corresponding register. The special instruction can greatly improve the calculation efficiency of data normalization, while reducing the code complexity, power consumption and memory overhead, and enhancing the versatility of the RISC-V instruction set.

[0013] The present invention also provides a data normalization RISC-V instruction set extension hardware acceleration device, which is integrated in the RISC-V processor core, including: a comparator, an iteration module, a MAX module, a MIN module, an operation unit, and a data normalization extension instruction calculation module;

[0014] The comparator is used to compare the input data, sending the larger value to the MAX module and the smaller value to the MIN module; the MAX module and the MIN module calculate the maximum and minimum values ​​of the input data respectively; the iteration module contains two extreme value registers, RMAX and RMIN, which are used to simplify the iterative update process of the maximum / minimum value; the operation unit includes a subtraction operation unit and a division operation unit, which reuses the operation unit in the RISC-V processor ALU to perform subtraction and division operations of the normalization formula; when the NORM instruction is executed, the RISC-V processor first retrieves the data to be normalized from the data memory through the load storage unit LSU, and sends it to the data normalization extension instruction calculation module; the data normalization extension instruction calculation module performs efficient calculation of the normalization formula and writes the result back to the target register. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Schematic diagram of the RISC-V processor core of the present invention.

[0016] Figure 2 It is a schematic diagram of the data normalization extension instruction calculation module in the present invention.

[0017] Figure 3 The iterative module block diagram of the hardware acceleration device for data normalization RISC-V instruction set extension of the present invention is shown.

[0018] Figure 4 This is a schematic diagram of the R-type instruction structure of the RISC-V instruction set adopted by the present invention.

[0019] Figure 5 It is a schematic diagram of the data normalization extension instruction of the present invention. DETAILED DESCRIPTION

[0020] like Figure 1 As shown in the figure, this data normalization RISC-V instruction set extension method, the RISC-V processor adopts a five-stage pipeline structure, and its main process includes:

[0021] (1) In the instruction fetch stage, the RISC-V processor pre-fetches the instruction with the corresponding data normalization stored in the instruction register according to the address generated by the instruction counter PC;

[0022] (2) In the decoding stage, the instruction signal is parsed in the decoding module by analyzing the encoding of Opcode, func7 and func3 to parse the corresponding instruction function and generate the corresponding control signal;

[0023] (3) In the execution phase, the data is first taken out from the data memory by the load storage unit LSU module, and then the data is passed to the data normalization extension instruction calculation module according to the control signal generated by the Nrom instruction. Finally, according to the formula

[0024] ,

[0025] Execute the normalization process and write the normalization result back to the corresponding register.

[0026] The RISC-V processor of the present invention adopts a five-stage pipeline structure. In the instruction fetching stage, the processor pre-fetches the corresponding data normalization instruction stored in the instruction register according to the address generated by the instruction counter. In the decoding stage, the instruction signal is parsed out of the corresponding instruction function by analyzing the encoding of Opcode, func7 and func3 in the decoding module, and a corresponding control signal is generated to enter the execution stage. Before executing the normalization instruction Nrom, the data is first taken out from the data storage device through the loading storage unit LSU module, and then according to the control signal generated by the Nrom instruction, the data is transferred to the data normalization extension instruction calculation device to execute the normalization process, and finally the normalization result is written back to the corresponding register, thereby greatly improving the calculation efficiency of data normalization, while reducing the code complexity, power consumption and memory overhead, and enhancing the versatility of the RISC-V instruction set.

[0027] Preferably, if Figure 2 As shown, the data normalization extension instruction calculation module includes: a comparator, an iteration module, a MAX module, a MIN module, a subtraction operation unit and a division operation unit; when the processor detects the Norm instruction, the register sends the data to be normalized to the data normalization extension instruction calculation module for data normalization calculation.

[0028] Preferably, in the data normalization extension instruction calculation module, the input data is first compared by a comparator, and the data is passed to the MAX module and the MIN module respectively according to the comparison results. These two modules calculate the maximum and minimum values ​​of the input data respectively, and temporarily store these values ​​in the maximum value register of the iteration module, and update these maximum value data through the iteration module.

[0029] Preferably, if Figure 3 As shown, the iteration module includes: an RMAX register, an RMIN register, and a comparator; the RMAX register is used to store the current maximum value, and the RMIN register is used to store the current minimum value. After the MAX and MIN modules calculate the current extreme values, these values ​​will be sent to the iteration module and compared with the values ​​in the extreme value register in the comparator. If the current maximum value exceeds the value in the RMAX register, the register is updated; if the current minimum value is lower than the value in the RMIN register, the RMIN register is updated; after the iteration process is completed, the iteration module outputs the maximum value stored in the RMAX register and the minimum value in the RMIN register.

[0030] Preferably, the data normalization extension instruction calculation module performs subtraction and division operations, and these basic operations are contained in the arithmetic logic unit ALU of the RISC-V processor.

[0031] Preferably, if Figure 4 As shown, the method adopts the R-type instruction of RISC-V as the custom instruction format, and the extended instructions include: rs1, rs2, rd, funct7, funct3 and opcode; the bit width of the register address of rs1, rs2 and rd is 5 bits, the bit width of funct7 is 7 bits, the bit width of funct3 is 3 bits, and the bit width of opcode is 7 bits; rs1 records the register address of the source operand 1, rs2 records the register address of the source operand 2, and the funct3 field and the funct7 field are used together to determine the data normalization instruction.

[0032] Preferably, if Figure 5 As shown, the opcode encoding of the normalization instruction is consistent with the opcode encoding of the R-type instruction, which is defined as 0110011; the funct3 field is 000, which is the same as the add and sub instructions in the R-type, and the funct7 field is 000110; the instruction form of this method is NROM rd,rs1; rs1 represents the data to be normalized, and rd represents the normalized data.

[0033] Those skilled in the art can understand that all or part of the steps in the above-mentioned implementation method can be realized by sending instructions through a program to control the relevant hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned implementation method, and the storage medium can be: ROM / RAM, disk, CD, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a hardware acceleration device for data normalization RISC-V instruction set extension, which is usually represented in the form of functional modules corresponding to the steps of the method. The device is integrated in the RISC-V processor core, including: a comparator, an iteration module, a MAX module, a MIN module, an operation unit, and a data normalization extension instruction calculation module;

[0034] The comparator is used to compare input data. The larger value is sent to the MAX module, and the smaller value is sent to the MIN module; the MAX module and the MIN module calculate the maximum and minimum values ​​of the input data respectively; the iteration module contains two extreme value registers, RMAX and RMIN, which are used to simplify the iterative update process of the maximum / minimum value; the operation unit includes a subtraction operation unit and a division operation unit, which reuses the operation unit in the RISC-V processor ALU to perform subtraction and division operations of the normalization formula; when the NORM instruction is executed, the RISC-V processor first takes out the data to be normalized from the data memory through the load storage unit LSU, and sends it to the data normalization extension instruction calculation module; the data normalization extension instruction calculation module performs efficient calculation of the normalization formula and writes the result back to the target register.

[0035] Preferably, the device adopts RISC-V's R-type instructions as the custom instruction format, and the extended instructions include: rs1, rs2, rd, funct7, funct3 and opcode; the rs1, rs2 and rd register address bit widths are 5 bits, the funct7 bit width is 7 bits, the funct3 bit width is 3 bits, and the opcode bit width is 7 bits; rs1 records the register address of source operand 1, rs2 records the register address of source operand 2, and the funct3 field and the funct7 field are used together to determine the data normalization instruction.

[0036] Preferably, the opcode encoding of the normalization instruction is consistent with the opcode encoding of the R-type instruction, which is defined as 0110011; the funct3 field is 000, which is the same as the Add and Sub instructions in the R-type, and the funct7 field is 000110; the instruction form of this method is NROM rd, rs1, rs1 represents the current data to be normalized, and rd represents the normalized data.

[0037] The present invention will be described in more detail below with reference to the accompanying drawings.

[0038] Figure 1 The RISC-V processor core schematic diagram of the data normalization extension instruction calculation module of the present invention is integrated with the RISC-V processor. The processor includes an instruction memory, an instruction counter, a decoding module, a branch module, an execution module (ALU), a data normalization extension instruction calculation device (NROM), and a load storage unit (LSU). In the process of integrating the instruction calculation device, the consistency of the hardware design and the efficient operation of the pipeline structure are guaranteed.

[0039] The RISC-V processor with integrated data normalization extension instruction computing device adopts a five-stage pipeline structure. In the instruction fetch stage, the processor pre-fetches the corresponding data normalization instruction stored in the instruction register according to the address generated by the instruction counter (PC). In the decoding stage, the instruction signal is analyzed in the decoding module by the encoding of func7 and func3 to parse the corresponding instruction function and generate the corresponding control signal. Entering the execution stage, before executing the normalization instruction (NROM), it is necessary to first fetch the data from the data memory through the loading storage unit LSU module, and then transfer the data to the data normalization extension instruction computing device according to the control signal generated by the Nrom instruction. Finally, according to the formula

[0040] ,

[0041] Execute the normalization process and finally write the normalization result back to the corresponding register.

[0042] Figure 2 The figure is a schematic diagram of the data normalization extended instruction calculation module in the present invention. The data normalization extended instruction calculation module includes a comparator, an iteration module, a MAX and MIN module, a subtraction operation unit and a division operation unit. The calculation device is to improve the efficiency of the processor in executing the extended instruction Norm instruction. When the processor detects the Norm instruction, the register sends the data to be normalized to the data normalization extended instruction calculation module for data normalization calculation.

[0043] In the data normalization extension instruction calculation module, the input data will first be compared by the comparator, and the data will be passed to the MAX and MIN modules respectively according to the comparison results. These two modules calculate the maximum and minimum values ​​of the input data respectively, and temporarily store these values ​​in the extreme value register of the iteration module, and update these extreme value data through the iteration module. Since the device performs data comparison and diversion in advance, the larger data is input into the MAX module to obtain the maximum value, and the smaller data is input into the MIN module to obtain the minimum value. This can not only greatly reduce the number of data comparisons in the process of finding the maximum and minimum values ​​in the MAX and MIN modules, but also there is no data dependency between the two modules and can be calculated in parallel, thereby improving the calculation efficiency. After iteration, the maximum and minimum values ​​of the data to be normalized are obtained. Next, the data normalization extension instruction calculation module performs subtraction and division operations. These basic operations are included in the existing arithmetic logic unit (Alu) of the RISC-V processor. Separately designing subtraction and division operations in the data normalization extension instruction calculation device will make the module design and verification more complicated. In order to reduce the design complexity and optimize the utilization of hardware resources, the present invention does not independently design these basic operations, but reuses the subtraction and division operation units in the existing arithmetic logic unit (Alu) of the RISC-V processor.

[0044] Figure 3 The block diagram of the iteration module of the data normalization extended instruction calculation module of the present invention is shown. The module includes two extreme value registers: RMAX and RMIN, and a comparator. The RMAX register is used to store the current maximum value, and the RMIN register is used to store the current minimum value. After the MAX and MIN modules calculate the current extreme values, these values ​​will be sent to the iteration module and compared with the values ​​in the extreme value registers in the comparator. If the current maximum value exceeds the value in the RMAX register, the register is updated; similarly, if the current minimum value is lower than the value in the RMIN register, the RMIN register is updated. After the iteration process is completed, the module outputs the final maximum and minimum values ​​stored in RMAX and RMIN. By utilizing the extreme value registers, the design of the iteration module simplifies the calculation process and reduces the need for global comparison of all data, significantly improving the efficiency when processing large data sets. In addition, the application of extreme value registers reduces the complexity and cost of hardware circuit design.

[0045] Figure 4 The present invention is a schematic diagram of the RISC-V instruction set R-type instruction structure, in which the instruction types in the RISC-V basic instruction set include R-type, I-type, S-type, B-type, U-type, and J-type. Since data normalization is a computationally intensive operation, it usually involves calculations between multiple registers. The R-type format is very suitable for such operations, and all operands are stored in registers, which can minimize the delay of accessing memory. The present invention adopts the R-type instruction of RISC-V as a custom instruction format, and the extended instructions include rs1, rs2, rd, funct7, funct3, and opcode. The register address bit widths of rs1, rs2, and rd are 5 bits, the bit width of funct7 is 7 bits, the bit width of funct3 is 3 bits, and the bit width of opcode is 7 bits. Rs1 is used to record the register address of source operand 1, and rs2 is used to record the register address of source operand 2. The funct3 field and the funct7 field are used together to distinguish the data normalization instruction.

[0046] Figure 5 The diagram of the data normalization extension instruction of the present invention is shown in FIG. The opcode encoding of the normalization instruction is consistent with the opcode encoding of the R-type instruction, which is defined as 0110011; the funct3 field is 000, which is the same as the add and sub instructions in the R-type, and the funct7 field is 000110, which is different from the two basic instructions. The instruction form of the present invention is NROM rd, rs1. rs1 represents the data to be normalized. rd represents the normalized data.

[0047] The beneficial technical effects of the present invention are as follows:

[0048] 1. Improve computing efficiency. By directly supporting data normalization at the hardware level, the number of instructions and computing time required for execution are greatly reduced, and the efficiency improvement is more significant when processing large-scale data sets.

[0049] 2. Reduce code complexity. Developers can directly use the NORM instruction to achieve data normalization without combining multiple basic instructions, which simplifies the programming process and reduces the complexity of code maintenance.

[0050] 3. Optimize power consumption and memory usage. Reduce the extra power consumption caused by multiple data loading, storage and intermediate result calculations, while reducing the demand for memory and improving memory usage efficiency.

[0051] 4. Enhance the versatility and reusability of the instruction set. The new instructions are not only used for data normalization, but also support other data processing tasks, increasing the flexibility and application scope of the RISC-V instruction set.

[0052] 5. Scalability. If you need to support other normalization operations, you can do so by combining and expanding existing instructions without having to redesign new instructions, which has good scalability.

[0053] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. Data normalization RISC-V instruction set extension method, Features: The RISC-V processor uses a five-stage pipeline structure, which includes: (1) In the instruction fetch stage, the RISC-V processor pre-fetches the instruction with the corresponding data normalization stored in the instruction register according to the address generated by the instruction counter PC; (2) In the decoding stage, the instruction signal is parsed in the decoding module by analyzing the encoding of Opcode, func7 and func3 to parse the corresponding instruction function and generate the corresponding control signal; (3) In the execution phase, the data is first taken out from the data memory by the load storage unit LSU module, and then the data is passed to the data normalization extension instruction calculation module according to the control signal generated by the Nrom instruction. Finally, according to the formula ， Execute the normalization process and write the normalization result back to the corresponding register.

2. The data normalization RISC-V instruction set extension method according to claim 1, Features: The data normalization extension instruction calculation module includes: a comparator, an iteration module, a MAX module, a MIN module, a subtraction operation unit and a division operation unit; when the processor detects the Norm instruction, the register sends the data to be normalized to the data normalization extension instruction calculation module for data normalization calculation.

3. The data normalization RISC-V instruction set extension method according to claim 2, Features: In the data normalization extension instruction calculation module, the input data is first compared by the comparator, and the data is passed to the MAX module and the MIN module according to the comparison results. These two modules calculate the maximum and minimum values ​​of the input data respectively, and temporarily store these values ​​in the maximum value register of the iteration module. These maximum value data are updated through the iteration module.

4. The data normalization RISC-V instruction set extension method according to claim 3, Features: The iteration module includes: an RMAX register, an RMIN register, and a comparator; the RMAX register is used to store the current maximum value, and the RMIN register is used to store the current minimum value. When the MAX and MIN modules calculate the current extreme values, these values ​​will be sent to the iteration module and compared with the values ​​in the registers in the comparator. If the current maximum value exceeds the value in the RMAX register, the register is updated; if the current minimum value is lower than the value in the RMIN register, the RMIN register is updated; after the iteration process is completed, the iteration module outputs the maximum value stored in the RMAX register and the minimum value in the RMIN register.

5. The data normalization RISC-V instruction set extension method according to claim 4, Features: The data normalization extension instruction calculation module performs subtraction and division operations, which are basic operations contained in the arithmetic logic unit ALU of the RISC-V processor.

6. The data normalization RISC-V instruction set extension method according to claim 1, Features: This method uses RISC-V's R-type instructions as the custom instruction format, and the extended instructions include: rs1, rs2, rd, funct7, funct3 and opcode; the register address widths of rs1, rs2 and rd are 5 bits, the bit width of funct7 is 7 bits, the bit width of funct3 is 3 bits, and the bit width of opcode is 7 bits; rs1 records the register address of source operand 1, rs2 records the register address of source operand 2, the Opcode field is used to determine the instruction type, and the funct3 field and the funct7 field are used together to identify the data normalization instruction.

7. The data normalization RISC-V instruction set extension method according to claim 6, Features: The opcode encoding of the normalized instruction is consistent with the opcode encoding of the R-type instruction, which is defined as 0110011; the funct3 field is 000, which is the same as the add and sub instructions in the R-type, and the funct7 field is 000110; The instruction form of this method is NROM rd,rs1, rs1 represents the data to be normalized, and rd represents the normalized data.

8. Data normalization hardware acceleration device for RISC-V instruction set extension, Features: It is integrated in the RISC-V processor core, including: comparator, iteration module, MAX module, MIN module, operation unit, data normalization extension instruction calculation module; The comparator is used to compare the input data, sending the larger value to the MAX module and the smaller value to the MIN module; the MAX module and the MIN module calculate the maximum and minimum values ​​of the input data respectively; the iteration module contains two extreme value registers, RMAX and RMIN, which are used to simplify the iterative update process of the maximum / minimum value; the operation unit includes a subtraction operation unit and a division operation unit, which reuses the operation unit in the RISC-V processor ALU to perform subtraction and division operations of the normalization formula; when the NORM instruction is executed, the RISC-V processor first retrieves the data to be normalized from the data memory through the load storage unit LSU, and sends it to the data normalization extension instruction calculation module; the data normalization extension instruction calculation module performs efficient calculation of the normalization formula and writes the result back to the target register.

9. The hardware acceleration device for data normalization RISC-V instruction set extension according to claim 8, Features: The device adopts RISC-V R-type instructions as the custom instruction format, and the extended instructions include: rs1, rs2, rd, funct7, funct3 and opcode; the bit width of the register addresses of rs1, rs2 and rd is 5 bits, the bit width of funct7 is 7 bits, the bit width of funct3 is 3 bits, and the bit width of opcode is 7 bits; rs1 records the register address of source operand 1, rs2 records the register address of source operand 2, and the funct3 field and the funct7 field are used together to determine the data normalization instruction.

10. The hardware acceleration device for data normalization RISC-V instruction set extension according to claim 9, Features: The opcode encoding of the normalized instruction is consistent with the opcode encoding of the R-type instruction, which is defined as 0110011; the funct3 field is 000, which is the same as the add and sub instructions in the R-type, and the funct7 field is 000110; The instruction form of this method is NROM rd,rs1; rs1 represents the data to be normalized, and rd represents the normalized data.

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