Integrated circuit network backbone wiring device method, device and related equipment

Abstract

The present disclosure proposes a method, device, and related equipment for an integrated circuit's wire network backbone wiring device. The method includes: obtaining signal wire network information and device location information of a target wiring layer on an integrated circuit layout; the signal wire network information includes the pins contained in each signal wire network; based on the signal wire network information and device location information, determining the devices whose centers are located on the same horizontal line and whose pins belong to different signal wire networks as the same horizontal group; and, based on the signal wire network information and device location information, determining the devices whose centers are located on the same vertical line and whose pins belong to different signal wire networks as the same vertical group; determining the minimum rectangle corresponding to the devices contained in each horizontal group and each vertical group; and using the horizontal center line of each minimum rectangle as a reference, evenly generating the backbone of each signal wire network along both sides of the horizontal center line of each minimum rectangle.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit wiring design, and in particular to a method, device and related equipment for wiring a wire network backbone of an integrated circuit. Background Art

[0002] Integrated circuits (ICs) in the related art typically include multiple signal lines. When routing these signal lines on the wiring layer of the IC, their backbones must meet relevant electrical requirements. However, routing these backbones in the related art is time-consuming and complex. Summary of the Invention

[0003] The present disclosure provides a method, apparatus, and related equipment for wiring the backbone of an integrated circuit network to solve the problems of long wiring time and high wiring complexity in the related art. The method includes:

[0004] A first embodiment of the present disclosure provides a method for wiring a network backbone of an integrated circuit, the method comprising:

[0005] Acquire signal line network information and device location information of a target wiring layer on an integrated circuit layout; the signal line network information includes pins included in each signal line network;

[0006] Based on the signal line network information and the device position information, the devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks are determined to be in the same horizontal group; and, based on the signal line network information and the device position information, the devices whose centers are located on the same vertical line and whose pins belong to different signal line networks are determined to be in the same vertical group;

[0007] Determine a minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups; wherein one of the horizontal groups or one of the vertical groups corresponds to one minimum rectangle;

[0008] Taking the horizontal center line of each of the minimum rectangles as a reference, the backbone of each signal line network is evenly generated along both sides of the horizontal center line of each of the minimum rectangles.

[0009] In one embodiment, determining the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups includes:

[0010] Traversing each of the Pins, determining at least one horizontal group and / or vertical group to which the current Pin belongs;

[0011] Based on at least one horizontal group or / and vertical group to which the current Pin belongs, obtain the number of Pins in the horizontal group or / and vertical group to which the current Pin belongs;

[0012] The group containing the largest number of pins in the horizontal group or / and vertical group to which the current pin belongs is used as the vertical group or horizontal group described by the currently traversed pin;

[0013] Determine the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups.

[0014] In one embodiment, the step of using the group containing the largest number of Pins in the horizontal group or / and vertical group to which the current Pin belongs as the vertical group or horizontal group of the currently traversed Pin includes:

[0015] If there are two or more groups with the largest number of pins in the horizontal group or / and vertical group to which the currently traversed Pin belongs, any horizontal group among the groups with the largest number of pins is selected as the group to which the current Pin belongs.

[0016] In one embodiment, determining the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups includes:

[0017] Determining whether projections of different horizontal groups on the X-axis and projections of different vertical groups on the Y-axis overlap, respectively; wherein the X-axis and the Y-axis refer to the X-axis and the Y-axis of a two-dimensional coordinate system having any vertex of the target wiring layer as an origin and edges of the target wiring layer associated with the origin;

[0018] According to the judgment result, the horizontal groups whose projections on the X-axis overlap are determined to be the same horizontal submodule, and the vertical groups whose projections on the Y-axis overlap are determined to be the same vertical submodule;

[0019] Determine the minimum rectangle corresponding to each of the horizontal sub-modules and each of the vertical sub-modules and including all devices in the sub-modules.

[0020] In one embodiment, determining the minimum rectangle corresponding to each of the horizontal submodules and each of the vertical submodules and including all devices in the submodules includes:

[0021] Traversing each of the horizontal submodules, determining the devices whose projections in the Y-axis direction overlap within the horizontal submodules as the same Pin group, and traversing each of the vertical submodules, determining the devices whose projections in the X-axis direction overlap within the vertical submodules as the same Pin group;

[0022] Determine the smallest rectangle corresponding to each pin group that contains all devices in the pin group.

[0023] In one embodiment, the step of generating the backbone of each signal line net evenly along both sides of the horizontal center line of each minimum rectangle based on the horizontal center line of each minimum rectangle includes:

[0024] Taking the horizontal center line of each of the minimum rectangles as a reference, the backbone of each signal network is generated evenly along the channels of the adjacent horizontal submodules or vertical submodules and along both sides of the horizontal center line of each of the minimum rectangles.

[0025] A second aspect of the present disclosure provides a network backbone wiring device for an integrated circuit, the device comprising:

[0026] An acquisition unit is used to acquire signal line network information and device position information of a target wiring layer on an integrated circuit layout; the signal line network information includes pins contained in each signal line network;

[0027] a grouping unit for determining, based on the signal line network information and the device position information, devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks as the same horizontal group; and, based on the signal line network information and the device position information, devices whose centers are located on the same vertical line and whose pins belong to different signal line networks as the same vertical group;

[0028] a determining unit, configured to determine a minimum rectangle corresponding to the devices included in each of the horizontal groupings and each of the vertical groupings; wherein one of the horizontal groupings or one of the vertical groupings corresponds to one of the minimum rectangles;

[0029] The generating unit is used to generate the backbone of each signal line network evenly along both sides of the horizontal center line of each minimum rectangle based on the horizontal center line of each minimum rectangle.

[0030] A third embodiment of the present disclosure provides an electronic device, including:

[0031] at least one processor; and

[0032] a memory communicatively connected to the at least one processor; wherein,

[0033] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

[0034] A fourth aspect of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute the method described in the first aspect of the present disclosure.

[0035] A fifth aspect of the present disclosure provides a computer program product, including a computer program, which implements the method described in the first aspect of the present disclosure when executed by a processor.

[0036] In summary, the present disclosure proposes a wire network backbone routing method for an integrated circuit, the method comprising: obtaining signal wire network information and device position information of a target wiring layer on an integrated circuit layout; the signal wire network information includes the pins contained in each signal wire network; based on the signal wire network information and device position information, the devices whose centers are located on the same horizontal line and whose pins belong to different signal wire networks are determined to be in the same horizontal group; and, based on the signal wire network information and device position information, the devices whose centers are located on the same vertical line and whose pins belong to different signal wire networks are determined to be in the same vertical group; determining the minimum rectangle corresponding to the devices contained in each horizontal group and each vertical group; wherein, one horizontal group or one vertical group corresponds to one minimum rectangle; taking the horizontal center line of each minimum rectangle as a reference, evenly generating the backbone of each signal wire network along both sides of the horizontal center line of each minimum rectangle.

[0037] The solution provided by the present disclosure simplifies the complexity and computational level of the signal line network trunk wiring, and effectively reduces the signal line network trunk wiring time by determining devices belonging to different signal line networks and whose device centers are on the same horizontal line or the same vertical line as the same horizontal group or the same vertical group, and then using the horizontal center line of the minimum rectangle corresponding to each group as a reference, uniformly generating the trunk of each signal line network along both sides of the horizontal center line of each minimum rectangle.

[0038] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute an improper limitation of the present disclosure.

[0040] Figure 1 A schematic diagram of a flow chart of a wire mesh backbone routing method for an integrated circuit provided in an embodiment of the present disclosure;

[0041] Figure 2 A schematic diagram of horizontal grouping and vertical grouping provided in an embodiment of the present disclosure;

[0042] Figure 3 A schematic flow chart of another integrated circuit network backbone routing method provided by an embodiment of the present disclosure;

[0043] Figure 4 A schematic flow chart of another integrated circuit network backbone routing method provided in an embodiment of the present disclosure;

[0044] Figure 5 A schematic diagram of devices with overlapping projections on the Y-axis in vertical groupings provided in an embodiment of the present disclosure;

[0045] Figure 6 A schematic diagram of devices with overlapping projections on the X-axis in horizontal grouping provided by an embodiment of the present disclosure;

[0046] Figure 7 A schematic diagram of generating a trunk of each signal line network along both sides of the horizontal center line of each minimum rectangle provided in an embodiment of the present disclosure;

[0047] Figure 8 A schematic diagram of a channel between adjacent horizontal submodules or vertical submodules provided in an embodiment of the present disclosure.

[0048] Figure 9 A schematic structural diagram of a wire network backbone wiring device for an integrated circuit provided in an embodiment of the present disclosure;

[0049] Figure 10 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] The following describes in detail embodiments of the present disclosure, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, and should not be construed as limiting the present disclosure.

[0051] In order to solve the defects in the related art, the present disclosure determines the devices belonging to different signal line networks and whose centers are on the same horizontal line or the same vertical line as the same horizontal group or the same vertical group, and then uses the horizontal center line of the minimum rectangle corresponding to each group as a reference to evenly generate the backbone of each signal line network along both sides of the horizontal center line of each minimum rectangle, thereby simplifying the complexity and calculation level of the signal line network backbone wiring and effectively reducing the signal line network backbone wiring time.

[0052] The present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] like Figure 1 As shown, Figure 1 The schematic diagram of the process flow of the integrated circuit network backbone routing method provided by the embodiment of the present disclosure. The integrated circuit network backbone routing method provided by the embodiment of the present disclosure includes the following steps:

[0054] Step 101, obtaining signal line network information and device location information of a target wiring layer on an integrated circuit layout; the signal line network information includes pins included in each signal line network;

[0055] In one embodiment, the signal net information refers to all nets included in the target wiring layer on the integrated circuit layout, the pins included in each net, and the device described by each pin.

[0056] In one embodiment, the process data contained in the target wiring layer, such as wiring design rules, etc., may be initialized, and the signal line net and wiring image may be read in to obtain the signal line net information.

[0057] In one embodiment, device location information on the target wiring layer may also be obtained based on the wiring image.

[0058] Step 102: Based on the signal line network information and the device position information, devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks are determined to be in the same horizontal group; and, based on the signal line network information and the device position information, devices whose centers are located on the same vertical line and whose pins belong to different signal line networks are determined to be in the same vertical group;

[0059] In one embodiment, if the outer frame of the device is rectangular, the center of the device is the center of the rectangle.

[0060] In one embodiment, if Figure 2 As shown, Figure 2 The left side is the horizontal grouping. Figure 2 On the right is the vertical grouping.

[0061] Step 103, determining a minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups; wherein one horizontal group or one vertical group corresponds to one minimum rectangle;

[0062] In one embodiment, the minimum rectangle refers to the smallest rectangle that can enclose all devices in the horizontal group or the vertical group.

[0063] Step 104 : Taking the horizontal center line of each of the minimum rectangles as a reference, evenly generate the backbone of each signal line network along both sides of the horizontal center line of each of the minimum rectangles.

[0064] In one embodiment, the trunk of each signal line network may be generated evenly along both sides of the horizontal center line of each minimum rectangle in the gaps between the minimum rectangles, taking the horizontal center line of the minimum rectangle as a reference.

[0065] In one embodiment, if the number of signal line nets in the target wiring layer is an even number, trunks equal in number to the signal line nets are generated along both sides of the horizontal center line of each of the minimum rectangles.

[0066] In one embodiment, if the number of signal line networks in the target wiring layer is an odd number, such as N, a trunk is first generated along the horizontal center line of each of the minimum rectangles, and then N-1 trunks are generated on both sides of the horizontal center line of each of the minimum rectangles.

[0067] The present disclosure proposes a wire network backbone routing method for an integrated circuit, the method comprising: obtaining signal wire network information and device position information of a target wiring layer on an integrated circuit layout; the signal wire network information includes the pins contained in each signal wire network; based on the signal wire network information and device position information, determining the devices whose centers are located on the same horizontal line and whose pins belong to different signal wire networks as the same horizontal group; and, based on the signal wire network information and device position information, determining the devices whose centers are located on the same vertical line and whose pins belong to different signal wire networks as the same vertical group; determining the minimum rectangle corresponding to the devices contained in each of the horizontal groups and each of the vertical groups; wherein one of the horizontal groups or one of the vertical groups corresponds to one of the minimum rectangles; and using the horizontal center line of each of the minimum rectangles as a reference, evenly generating the backbone of each signal wire network along both sides of the horizontal center line of each of the minimum rectangles.

[0068] The solution provided by the present disclosure simplifies the complexity and computational level of the signal line network trunk wiring, and effectively reduces the signal line network trunk wiring time by determining devices belonging to different signal line networks and whose device centers are on the same horizontal line or the same vertical line as the same horizontal group or the same vertical group, and then using the horizontal center line of the minimum rectangle corresponding to each group as a reference, uniformly generating the trunk of each signal line network along both sides of the horizontal center line of each minimum rectangle.

[0069] In one embodiment, if Figure 3 As shown, step 103 includes:

[0070] Step 301, traverse each of the Pins and determine at least one horizontal group and / or vertical group to which the current Pin belongs;

[0071] In one embodiment, the pins included in each signal line net may be traversed in sequence according to each signal line net.

[0072] In one embodiment, according to each device in the target wiring layer, the pins included in each device may be traversed in sequence.

[0073] Step 302: Based on at least one horizontal group or / and vertical group to which the current Pin belongs, obtain the number of Pins in the horizontal group or / and vertical group to which the current Pin belongs;

[0074] Step 303: The group containing the largest number of Pins among the horizontal group or / and vertical group to which the current Pin belongs is used as the vertical group or horizontal group of the currently traversed Pin;

[0075] Step 304: Determine the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups.

[0076] In one embodiment, the minimum rectangle refers to an outer bounding rectangle containing all devices in each group (horizontal group or vertical group).

[0077] In one embodiment, step 303 includes:

[0078] If there are two or more groups with the largest number of pins in the horizontal group or / and vertical group to which the currently traversed Pin belongs, any horizontal group among the groups with the largest number of pins is selected as the group to which the current Pin belongs.

[0079] In one embodiment, if the groups with the largest number of Pins are all vertical groups, any one of the vertical groups is selected as the group to which the current Pin belongs.

[0080] In one embodiment, if Figure 4 As shown, step 103 includes:

[0081] Step 401, determining whether the projections of different horizontal groups on the X-axis and the projections of different vertical groups on the Y-axis overlap; wherein the X-axis and the Y-axis refer to the X-axis and the Y-axis of a two-dimensional coordinate system having any vertex of the target wiring layer as an origin and edges of the target wiring layer associated with the origin;

[0082] like Figure 5 As shown, Figure 5 Schematic diagram of devices in vertical grouping with overlapping projections on the Y axis.

[0083] Step 402: According to the determination result, the horizontal groups whose projections on the X-axis overlap are determined to be the same horizontal submodule, and the vertical groups whose projections on the Y-axis overlap are determined to be the same vertical submodule;

[0084] like Figure 5 and Figure 6 As shown, Figure 6 Schematic diagram of devices in horizontal grouping with overlapping projections on the X-axis.

[0085] Step 403 : Determine the minimum rectangle corresponding to each horizontal submodule and each vertical submodule and including all devices in the submodule.

[0086] In one embodiment, Figure 5 and Figure 6 The bounding box in is considered as the minimum rectangle.

[0087] In one embodiment, step 403 includes:

[0088] Traversing each of the horizontal submodules, determining the devices whose projections in the Y-axis direction overlap within the horizontal submodules as the same Pin group, and traversing each of the vertical submodules, determining the devices whose projections in the X-axis direction overlap within the vertical submodules as the same Pin group;

[0089] Determine the smallest rectangle corresponding to each pin group that contains all devices in the pin group.

[0090] In one embodiment, the step of generating the backbone of each signal line net evenly along both sides of the horizontal center line of each minimum rectangle based on the horizontal center line of each minimum rectangle includes:

[0091] Taking the horizontal center line of each of the minimum rectangles as a reference, the backbone of each signal network is generated evenly along the channels of the adjacent horizontal submodules or vertical submodules and along both sides of the horizontal center line of each of the minimum rectangles.

[0092] like Figure 7 As shown, Figure 7 Generating a schematic diagram of the backbone of each signal line network along both sides of the horizontal center line of each of the minimum rectangles; Figure 8 Schematic diagram of the channel between adjacent horizontal submodules or vertical submodules.

[0093] In order to implement the wire mesh backbone wiring method of the integrated circuit provided by the embodiment of the present disclosure, the embodiment of the present disclosure also provides a wire mesh backbone wiring device of the integrated circuit, such as Figure 9 shown. Figure 9 This is a schematic structural diagram of a wire mesh backbone wiring device for an integrated circuit provided in an embodiment of the present disclosure. The wire mesh backbone wiring device 900 for an integrated circuit includes:

[0094] The acquisition unit 901 is used to acquire the signal line network information and device position information of the target wiring layer on the integrated circuit layout; the signal line network information includes the pins included in each signal line network;

[0095] The grouping unit 902 is configured to, based on the signal line network information and the device position information, group devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks into the same horizontal group; and, based on the signal line network information and the device position information, group devices whose centers are located on the same vertical line and whose pins belong to different signal line networks into the same vertical group;

[0096] A determining unit 903 is configured to determine a minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups; wherein one horizontal group or one vertical group corresponds to one minimum rectangle;

[0097] The generating unit 904 is configured to generate the backbone of each signal line network evenly along both sides of the horizontal center line of each minimum rectangle, taking the horizontal center line of each minimum rectangle as a reference.

[0098] In one embodiment, the determining unit 903 is specifically configured to:

[0099] Traversing each of the Pins, determining at least one horizontal group and / or vertical group to which the current Pin belongs;

[0100] Based on at least one horizontal group or / and vertical group to which the current Pin belongs, obtain the number of Pins in the horizontal group or / and vertical group to which the current Pin belongs;

[0101] The group containing the largest number of pins in the horizontal group or / and vertical group to which the current pin belongs is used as the vertical group or horizontal group described by the currently traversed pin;

[0102] Determine the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups.

[0103] In one embodiment, the determining unit 903 is further specifically configured to:

[0104] If there are two or more groups with the largest number of pins in the horizontal group or / and vertical group to which the currently traversed Pin belongs, any horizontal group among the groups with the largest number of pins is selected as the group to which the current Pin belongs.

[0105] In one embodiment, the determining unit 903 is further specifically configured to:

[0106] Determining whether projections of different horizontal groups on the X-axis and projections of different vertical groups on the Y-axis overlap, respectively; wherein the X-axis and the Y-axis refer to the X-axis and the Y-axis of a two-dimensional coordinate system having any vertex of the target wiring layer as an origin and edges of the target wiring layer associated with the origin;

[0107] According to the judgment result, the horizontal groups whose projections on the X-axis overlap are determined to be the same horizontal submodule, and the vertical groups whose projections on the Y-axis overlap are determined to be the same vertical submodule;

[0108] Determine the minimum rectangle corresponding to each of the horizontal sub-modules and each of the vertical sub-modules and including all devices in the sub-modules.

[0109] In one embodiment, the determining unit 903 is further specifically configured to:

[0110] Traversing each of the horizontal submodules, determining the devices whose projections in the Y-axis direction overlap within the horizontal submodules as the same Pin group, and traversing each of the vertical submodules, determining the devices whose projections in the X-axis direction overlap within the vertical submodules as the same Pin group;

[0111] Determine the smallest rectangle corresponding to each pin group that contains all devices in the pin group.

[0112] In one embodiment, the generating unit 904 is further specifically configured to:

[0113] Taking the horizontal center line of each of the minimum rectangles as a reference, the backbone of each signal network is generated evenly along the channels of the adjacent horizontal submodules or vertical submodules and along both sides of the horizontal center line of each of the minimum rectangles.

[0114] It should be noted that the aforementioned embodiments of the integrated circuit network backbone routing device, when performing integrated circuit network backbone routing, are merely exemplified by the division of the aforementioned program modules. In actual applications, the aforementioned processing can be distributed among different program modules as needed, i.e., the internal structure of the integrated circuit network backbone routing device can be divided into different program modules to complete all or part of the aforementioned processing. Furthermore, the integrated circuit network backbone routing device provided in the aforementioned embodiments and the integrated circuit network backbone routing method provided in the present disclosure are based on the same concept. The specific implementation process is detailed in the method embodiments and will not be further elaborated here.

[0115] Figure 10 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present disclosure is shown in FIG. Figure 10 As shown, the electronic device 1000 includes at least one processor 1002; and a memory 1001 communicatively connected to the at least one processor 1002; wherein the memory 1001 stores instructions that can be executed by the at least one processor 1002, and the instructions are executed by the at least one processor 1002 to implement the steps of the wire network backbone wiring method of the integrated circuit described in the embodiment of the present disclosure.

[0116] Optionally, the electronic device may specifically be a wire mesh backbone wiring device of an integrated circuit in an embodiment of the present application, and the electronic device may implement the corresponding processes implemented by the wire mesh backbone wiring device of the integrated circuit in each method of the embodiment of the present application. For the sake of brevity, they will not be repeated here.

[0117] It is understood that the electronic device also includes a communication interface 1003. The various components in the electronic device are coupled together through a bus system 1004. It is understood that the bus system 1004 is used to achieve connection and communication between these components. In addition to the data bus, the bus system 1004 also includes a power bus, a control bus, and a status signal bus. However, for the sake of clarity, Figure 10 Various buses are labeled as bus system 1004.

[0118] It is understood that the memory 1001 can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a magnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM); the magnetic surface memory can be a magnetic disk memory or a magnetic tape memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory 1001 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memories.

[0119] The methods disclosed in the above embodiments of the present disclosure can be applied to or implemented by processor 1002. Processor 1002 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in processor 1002 or by software instructions. Processor 1002 may be a general-purpose processor, a DSP, or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component. Processor 1002 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present disclosure. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of the present disclosure can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium located in memory 1001. Processor 1002 reads information from memory 1001 and, in conjunction with its hardware, completes the steps of the above method.

[0120] In an exemplary embodiment, the electronic device may be implemented by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), FPGAs, general-purpose processors, controllers, MCUs, microprocessors, or other electronic components to perform the aforementioned method.

[0121] The embodiment of the present disclosure further provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to implement the steps of the integrated circuit network backbone routing method described in the embodiment of the present disclosure when executed.

[0122] The embodiments of the present disclosure further provide a computer program product, characterized in that it includes a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the wire network backbone wiring method of the integrated circuit described in the embodiments of the present disclosure.

[0123] Optionally, the computer-readable storage medium can be applied to the wire mesh backbone wiring device of the integrated circuit in the embodiments of the present application, and the computer instructions enable the computer to execute the corresponding processes implemented by the wire mesh backbone wiring device of the integrated circuit in the various methods of the embodiments of the present application. For the sake of brevity, they will not be repeated here.

[0124] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0125] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0126] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0127] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, ROM, RAM, disks or optical disks, etc. Various media that can store program codes.

[0128] Alternatively, if the above-mentioned integrated unit of the present invention is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

[0129] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A method for wiring a wire network backbone of an integrated circuit, characterized in that: include: Obtain signal line network information and device location information of the target wiring layer on the integrated circuit layout; The signal line network information includes the pins contained in each signal line network; Based on the signal line network information and the device position information, the devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks are determined to be in the same horizontal group; and, based on the signal line network information and the device position information, the devices whose centers are located on the same vertical line and whose pins belong to different signal line networks are determined to be in the same vertical group; Determine a minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups; wherein one of the horizontal groups or one of the vertical groups corresponds to one minimum rectangle; Taking the horizontal center line of each of the minimum rectangles as a reference, the backbone of each signal line network is evenly generated along both sides of the horizontal center line of each of the minimum rectangles.

2. The method according to claim 1, characterized in that Determining the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups includes: Traversing each of the Pins, determining at least one horizontal group and / or vertical group to which the current Pin belongs; Based on at least one horizontal group or / and vertical group to which the current Pin belongs, obtain the number of Pins in the horizontal group or / and vertical group to which the current Pin belongs; The group containing the largest number of pins in the horizontal group or / and vertical group to which the current pin belongs is used as the vertical group or horizontal group described by the currently traversed pin; Determine the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups.

3. The method according to claim 2, characterized in that The step of taking the group containing the largest number of Pins in the horizontal group or / and vertical group to which the current Pin belongs as the vertical group or horizontal group of the currently traversed Pin includes: If there are two or more groups with the largest number of pins in the horizontal group or / and vertical group to which the currently traversed Pin belongs, any horizontal group among the groups with the largest number of pins is selected as the group to which the current Pin belongs.

4. The method according to claim 1, wherein Determining the minimum rectangle corresponding to the devices included in each of the horizontal groups and each of the vertical groups includes: Determining whether projections of different horizontal groups on the X-axis and projections of different vertical groups on the Y-axis overlap, respectively; wherein the X-axis and the Y-axis refer to the X-axis and the Y-axis of a two-dimensional coordinate system having any vertex of the target wiring layer as an origin and edges of the target wiring layer associated with the origin; According to the judgment result, the horizontal groups whose projections on the X-axis overlap are determined to be the same horizontal submodule, and the vertical groups whose projections on the Y-axis overlap are determined to be the same vertical submodule; Determine the minimum rectangle corresponding to each of the horizontal sub-modules and each of the vertical sub-modules and including all devices in the sub-modules.

5. The method according to claim 4, characterized in that The determining of the minimum rectangle corresponding to each of the horizontal submodules and each of the vertical submodules and including all devices in the submodules includes: Traversing each of the horizontal submodules, determining the devices whose projections in the Y-axis direction overlap within the horizontal submodules as the same Pin group, and traversing each of the vertical submodules, determining the devices whose projections in the X-axis direction overlap within the vertical submodules as the same Pin group; Determine the smallest rectangle corresponding to each pin group that contains all devices in the pin group.

6. The method according to claim 5, characterized in that The step of evenly generating the backbone of each signal line network along both sides of the horizontal center line of each minimum rectangle using the horizontal center line of each minimum rectangle as a reference includes: Taking the horizontal center line of each minimum rectangle as a reference, along the channels between adjacent horizontal submodules or vertical submodules, the backbone of each signal line network is evenly generated along both sides of the horizontal center line of each minimum rectangle.

7. A wire network backbone wiring device for an integrated circuit, characterized in that: include: An acquisition unit, used to acquire signal line network information and device position information of a target wiring layer on an integrated circuit layout; The signal line network information includes the pins contained in each signal line network; a grouping unit for determining, based on the signal line network information and the device position information, devices whose centers are located on the same horizontal line and whose pins belong to different signal line networks as the same horizontal group; and, based on the signal line network information and the device position information, devices whose centers are located on the same vertical line and whose pins belong to different signal line networks as the same vertical group; a determining unit, configured to determine a minimum rectangle corresponding to the devices included in each of the horizontal groupings and each of the vertical groupings; wherein one of the horizontal groupings or one of the vertical groupings corresponds to one of the minimum rectangles; The generating unit is used to generate the backbone of each signal line network evenly along both sides of the horizontal center line of each minimum rectangle based on the horizontal center line of each minimum rectangle.

8. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that A computer program is included which, when executed by a processor, implements the method according to any one of claims 1 to 6.

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