A micro light-emitting diode epitaxial wafer and its fabrication method

Abstract

This invention provides a micro-LED epitaxial wafer and its fabrication method. The fabrication method of the micro-LED epitaxial wafer provided in this application includes growing a composite transparent conductive film. The method comprises: in a reaction chamber, using a combination of radio frequency and DC sputtering, sequentially fabricating a low-resistivity ohmic contact layer, a buffer layer, a current-conducting layer, and a functional layer on the surface of a second-type semiconductor layer. This improves the density of the composite transparent conductive film and the ohmic contact between the composite transparent conductive film and the second-type semiconductor layer, thereby improving the ESD capability of the composite transparent conductive film. The low-resistivity ohmic contact layer, buffer layer, current-conducting layer, and functional layer are combined to achieve the purpose of fabricating a composite transparent conductive film with low resistivity, high transmittance, and high stability.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, and more specifically, relates to a micro light-emitting diode epitaxial wafer and its fabrication method. Background Technology

[0002] With technological advancements, fine-pitch displays, a crucial application of light-emitting diodes (LEDs) in the display industry, are gradually maturing. LED chips convert electrical energy into light energy. Specifically, the epitaxial structure of an LED chip includes at least sequentially stacked N-type semiconductor layers, an active region, and a P-type semiconductor layer. To enhance current spreading, a transparent conductive layer is also placed on the surface of the epitaxial structure. However, traditional fine-pitch displays still suffer from insufficient viewing distance and moiré patterns due to pixel pitch limitations and the inherent defects of discrete devices. To meet the ever-growing demands for superior display quality and to further expand application areas, fine-pitch displays are continuously evolving towards even smaller pixel pitches, which means the chip size is constantly decreasing.

[0003] As LED chip sizes shrink, the contact area between the transparent conductive layer and the epitaxial structure also gradually decreases. Currently, the transparent conductive layer is formed using a single-layer coating method in semiconductor processing, which can easily lead to insufficient density of the transparent conductive layer or poor ohmic contact of the epitaxial structure of the transparent conductive layer. This results in localized heat not being dissipated, causing a large thermal effect that leads to breakdown of the transparent conductive layer area, i.e., weak ESD (Electrostatic Discharge) capability, which in turn reduces the reliability of the chip. Summary of the Invention

[0004] In view of this, the present invention provides a micro light-emitting diode epitaxial wafer and its fabrication method to solve the problem in the prior art where insufficient density of the transparent conductive layer or poor ohmic contact between the transparent conductive layer and the epitaxial structure leads to local heat not being dissipated, resulting in a large thermal effect that causes the transparent conductive layer area to break down, i.e., weak ESD capability, and thus reduces the reliability of the chip.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A method for manufacturing a micro light-emitting diode epitaxial wafer includes:

[0007] Provide substrate;

[0008] An epitaxial structure and a composite transparent conductive film are sequentially grown on the substrate. The epitaxial structure includes a first type semiconductor layer, an active region, and a second type semiconductor layer sequentially stacked along the growth direction.

[0009] The growth of the composite transparent conductive film includes: in a reaction chamber, a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer and a functional layer are sequentially prepared on the surface of the second type semiconductor layer by a combination of radio frequency and DC sputtering. The current-conducting layer has a periodic structure, and each period includes a first transparent conductive layer, a nano metal layer and a second transparent conductive layer sequentially stacked along the growth direction.

[0010] Preferably, the low-resistance ohmic contact layer, buffer layer and current conduction layer are fabricated with a power ratio of RF / DC > 2:1.

[0011] The functional layer is fabricated using a power ratio of RF / DC < 1:3.

[0012] Preferably, the ratio of radio frequency (RF) power to DC power in the first transparent conductive layer is less than the ratio of RF power to DC power in the second transparent conductive layer.

[0013] Preferably, the radio frequency power of the low-resistance ohmic contact layer is no greater than 150W, and the DC power of the low-resistance ohmic contact layer is no greater than 50W.

[0014] Preferably, the light transmittance of the low-resistivity ohmic contact layer, buffer layer, first transparent conductive layer, and second transparent conductive layer is greater than 80%; the light transmittance of the nano-metal layer is greater than 70%; and the light transmittance of the functional layer is greater than 85%.

[0015] Preferably, the resistivity of the low-resistance ohmic contact layer, buffer layer, first transparent conductive layer, second transparent conductive layer, and functional layer is not greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer is not greater than 10 Ωcm. -6 Ωcm.

[0016] Preferably, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:95.

[0017] Preferably, a roughened interface is provided between the first transparent conductive layer and the second transparent conductive layer in each cycle of the current conducting layer, the nano metal layer is a discontinuous thin film and diffuses into the grooves of the roughened interface, and the nano metal layer is covered by the first transparent conductive layer and the second transparent conductive layer;

[0018] The nano-metal layer is formed by high-temperature annealing and recrystallization of a metal material layer, which increases the surface energy of the nano-metal layer by more than 40%. The total thickness of the metal material layer ranges from 0 nm to 5 nm, excluding the endpoint values.

[0019] Preferably, the first type semiconductor layer and the second type semiconductor layer are, respectively, an N-type semiconductor layer and a P-type semiconductor layer.

[0020] A micro LED epitaxial wafer is fabricated using any one of the above-described methods for fabricating micro LED epitaxial wafers, wherein the micro LED epitaxial wafer comprises:

[0021] Substrate;

[0022] An epitaxial structure and a composite transparent conductive film are sequentially stacked on the substrate. The epitaxial structure includes a first type semiconductor layer, an active region, and a second type semiconductor layer sequentially stacked along a first direction.

[0023] The composite transparent conductive film includes a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer, and a functional layer stacked sequentially along the first direction. The current-conducting layer has a periodic structure, and each period includes a first transparent conductive layer, a nano-metal layer, and a second transparent conductive layer stacked sequentially along the first direction. The first direction is perpendicular to the substrate and points from the substrate to the epitaxial structure.

[0024] Preferably, the resistivity of the low-resistance ohmic contact layer, buffer layer, first transparent conductive layer, second transparent conductive layer, and functional layer is not greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer is not greater than 10 Ωcm. -6 Ωcm.

[0025] Preferably, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:95.

[0026] The above technical solution achieves the following results:

[0027] The method for fabricating a micro LED epitaxial wafer provided by this invention, on the one hand, involves growing a composite transparent conductive film, which includes: in a reaction chamber, sequentially fabricating a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer, and a functional layer on the surface of a second-type semiconductor layer using a combination of radio frequency and DC sputtering. This improves the density of the composite transparent conductive film and the ohmic contact between the composite transparent conductive film and the second-type semiconductor layer, thereby enhancing the ESD capability of the composite transparent conductive film. This avoids the problem of insufficient density or poor ohmic contact between the transparent conductive layer and the epitaxial structure caused by the single-layer deposition method used in existing semiconductor processing, which leads to localized heat dissipation problems and significant thermal effects resulting in breakdown of the transparent conductive layer area; and the current conduction... The layer has a periodic structure, which can improve the conductivity of the composite transparent conductive film. Each period includes a first transparent conductive layer, a nano-metal layer, and a second transparent conductive layer stacked sequentially, which can improve the conductivity of the current conducting layer. At the same time, the low-resistance ohmic contact layer can reduce the contact resistance between the composite transparent conductive film and the second type semiconductor layer. The buffer layer can enable the island-shaped nano-metal layer to achieve very low resistance at a very thin thickness. Furthermore, the periodic structure of the buffer layer combined with the current conducting layer can increase the carrier concentration, thereby improving the current spreading effect and reducing the conduction resistance, which facilitates the formation of a high-transmittance film layer for the functional layer. The combination of the low-resistance ohmic contact layer, buffer layer, current conducting layer, and functional layer achieves the goal of preparing a composite transparent conductive film with low resistivity, high transmittance, and high stability.

[0028] On the other hand, the low-resistance ohmic contact layer, buffer layer and current conduction layer are prepared by using a power ratio of RF / DC > 2:1, which can increase the plasma concentration in the reaction chamber, further improve the light transmittance of the composite transparent conductive film, and the higher RF power can reduce the tip discharge caused by electron accumulation on the target surface, further improving the reliability of the composite transparent conductive film.

[0029] The functional layer is fabricated with a power ratio of RF / DC < 1:3. The functional layer increases the E intensity (electric field strength) by using higher DC power to improve the deposition rate of the functional layer, thereby improving the density and light transmittance of the composite transparent conductive film.

[0030] Furthermore, the power ratio of radio frequency (RF) to DC in the first transparent conductive layer is set to be smaller than that in the second transparent conductive layer. The smaller RF to DC power ratio in the first transparent conductive layer can form an amorphous thin film with a smaller lattice, which is more conducive to the formation of a low resistivity and high transmittance film layer in the subsequent nano metal layer.

[0031] Furthermore, the RF power of the low-resistivity contact layer is set to be no greater than 150W, and the DC power of the low-resistivity contact layer is set to be no greater than 50W. Low-power deposition of the low-resistivity contact layer is adopted to achieve a lower deposition rate, which can form an amorphous thin film and a thin film with a work function close to that of the type II semiconductor layer to form a good ohmic contact. The lower power can also reduce the tip discharge caused by electron accumulation on the target surface, thereby reducing damage to the type II semiconductor layer. This reduces the contact resistance between the composite transparent conductive film and the type II semiconductor layer and improves the ESD capability of the composite transparent conductive film.

[0032] Furthermore, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:95. Setting the thickness proportion of each layer not only enhances the current conduction capability of the composite transparent conductive film, but also matches the low-resistance ohmic contact layer formed by low power, thereby improving the ESD capability of the composite transparent conductive film. Moreover, by adjusting the thickness proportion of the low-resistance ohmic contact layer, the nano-metal layer, and the functional layer, the resistivity and light transmittance of the composite transparent conductive film can be adjusted.

[0033] Furthermore, in each cycle of the current-conducting layer, there is a roughened interface between the first and second transparent conductive layers. The nano-metal layer is a discontinuous thin film that diffuses into the grooves of the roughened interface. The nano-metal layer is covered by the first and second transparent conductive layers. The nano-metal layer is formed by high-temperature annealing and recrystallization of a metal material layer, which increases the surface energy of the nano-metal layer by more than 40%. The total thickness of the metal material layer ranges from 0 nm to 5 nm, excluding the endpoint values. The current-conducting layer can form an embedded structure. By controlling the thickness range of the metal material layer, a very thin metal material layer is formed into a nano-metal layer after high-temperature annealing. The roughened interface between the first and second transparent conductive layers allows the nano-metal layer to diffuse into the grooves of the roughened interface, enabling the nano-metal layer to expand the current laterally in the current-conducting layer, which can reduce the resistance and improve the conductivity of the current-conducting layer. The first and second transparent conductive layers can also prevent the metal ions of the nano-metal layer from diffusing to the PN junction and causing leakage, thus affecting the reliability and conductivity of the composite transparent conductive film.

[0034] The micro LED epitaxial wafer provided by this invention is fabricated using the aforementioned method for fabricating micro LED epitaxial wafers. This method can improve the density of the composite transparent conductive film and the ohmic contact between the composite transparent conductive film and the second-type semiconductor layer, thereby improving the ESD capability of the composite transparent conductive film. It avoids the problem of insufficient density of the transparent conductive layer or poor ohmic contact between the transparent conductive layer and the epitaxial structure, which would lead to local heat not being dissipated and thus generate a large thermal effect that causes the transparent conductive layer area to break down. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0036] Figure 1 A flowchart illustrating a method for fabricating a micro light-emitting diode epitaxial wafer according to an embodiment of the present invention;

[0037] Figures 2 to 3 for Figure 1 The process cross-sectional diagrams corresponding to each step of the manufacturing method shown;

[0038] Figure 4 A schematic diagram of the periodic structure of the current conduction layer provided in an embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of a single cycle of the current conduction layer provided in an embodiment of the present invention.

[0040] Explanation of symbols in the diagram:

[0041] 1. Substrate; 2. Epitaxial structure; 21. Type I semiconductor layer; 22. Active region; 23. Type II semiconductor layer; 3. Composite transparent conductive film; 31. Low-resistance ohmic contact layer; 32. Buffer layer; 33. Current conduction layer; 331. First transparent conductive layer; 332. Nanometal layer; 333. Second transparent conductive layer; 4. Functional layer. Detailed Implementation

[0042] To make the content of this invention clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0043] Many specific details are set forth in the following description in order to provide a full understanding of this application. However, this application may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of this application. Therefore, this application is not limited to the specific embodiments disclosed below.

[0044] Secondly, this application provides a detailed description in conjunction with schematic diagrams. When detailing the embodiments of this application, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged, not adhering to the usual scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of this application. In addition, actual fabrication should include three-dimensional spatial dimensions of length, width, and depth.

[0045] As described in the background section, as LED chip sizes shrink, the contact area between the transparent conductive layer and the epitaxial structure also gradually decreases. Currently, the transparent conductive layer is formed using a single-layer coating method in semiconductor processing, which can easily lead to insufficient density of the transparent conductive layer or poor ohmic contact between the transparent conductive layer and the epitaxial structure. This results in localized heat that cannot dissipate, causing a significant thermal effect that leads to breakdown in the transparent conductive layer area, i.e., weak ESD capability, which in turn reduces the reliability of the chip.

[0046] The inventors discovered that in the prior art, increasing the thickness of the transparent conductive layer improves its breakdown resistance and thus enhances the ESD capability of the micro LED. However, increasing the thickness of the transparent conductive layer not only increases the cost but also easily causes black spots on the transparent conductive layer.

[0047] In view of this, embodiments of this application provide a method for fabricating a micro light-emitting diode epitaxial wafer, such as... Figure 1 As shown, it includes:

[0048] Step S100, as follows Figure 2 As shown, substrate 1 is provided;

[0049] Step S200, as follows Figure 3 As shown, an epitaxial structure 2 and a composite transparent conductive film 3 are sequentially grown on a substrate 1. The epitaxial structure 2 includes a first type semiconductor layer 21, an active region 22 and a second type semiconductor layer 23 sequentially stacked along the growth direction.

[0050] The growth of the composite transparent conductive film 3 includes: within the reaction chamber, a low-resistance ohmic contact layer 31, a buffer layer 32, a current-conducting layer 33, and a functional layer 34 are sequentially fabricated on the surface of the second-type semiconductor layer 23 using a combination of radio frequency and direct current sputtering. Figure 4 As shown, the current conducting layer 33 has a periodic structure, and each period includes a first transparent conductive layer 331, a nano metal layer 332 and a second transparent conductive layer 333 stacked sequentially along the growth direction.

[0051] Based on the above embodiments, in one embodiment of this application, a low-resistance ohmic contact layer 31, a buffer layer 32, and a current conduction layer 33 are prepared, and the power ratio of radio frequency to DC is RF / DC > 2:1.

[0052] Functional layer 34 was fabricated with a power ratio of RF / DC < 1:3.

[0053] Based on the above embodiments, in one embodiment of this application, the power ratio of the radio frequency to the DC power of the first transparent conductive layer 331 is less than the power ratio of the radio frequency to the DC power of the second transparent conductive layer 333.

[0054] Based on the above embodiments, in one embodiment of this application, the RF power of the low-resistance ohmic contact layer 31 is no greater than 150W, and the DC power of the low-resistance ohmic contact layer 31 is no greater than 50W.

[0055] Optionally, in this embodiment, the RF power of the low-resistance ohmic contact layer 31 ranges from 100W to 150W, including the endpoint value; the DC power of the low-resistance ohmic contact layer 31 ranges from 10W to 50W, including the endpoint value.

[0056] Optionally, in this embodiment, the RF power of the buffer layer 32, the first transparent conductive layer 331, and the second transparent conductive layer 333 is no greater than 450W; the DC power of the buffer layer 32, the first transparent conductive layer 331, and the second transparent conductive layer 333 is no greater than 150W.

[0057] Optionally, in this embodiment, the RF power of the buffer layer 32 ranges from 100W to 450W, including the endpoint value; the DC power of the buffer layer 32 ranges from 50W to 150W, including the endpoint value.

[0058] Optionally, in this embodiment, the radio frequency power of the first transparent conductive layer 331 and the second transparent conductive layer 333 is in the range of 100W-450W, including the endpoint value; the DC power of the first transparent conductive layer 331 and the second transparent conductive layer 333 is in the range of 30W-150W, including the endpoint value.

[0059] Optionally, in this embodiment, the radio frequency power of the nano metal layer 332 is no greater than 900W; the DC power of the nano metal layer 332 is no greater than 300W.

[0060] Optionally, in this embodiment, the radio frequency power of the nano metal layer 332 ranges from 300W to 900W, including the endpoint value; the DC power of the nano metal layer 332 ranges from 100W to 300W, including the endpoint value.

[0061] It should be noted that in this embodiment, a buffer layer is set between the low-resistivity ohmic contact layer and the current conduction layer. This can avoid the problem of discharge caused by capacitor-resistance resonance when switching to higher RF power / DC power after growing the low-resistivity ohmic contact layer with lower RF power / DC power. The buffer layer can adjust the matching when switching RF power / DC power, which is conducive to the formation of low resistivity and high transmittance film layers in each layer of the current conduction layer.

[0062] Based on the above embodiments, in one embodiment of this application, the RF power of functional layer 34 is no greater than 300W; the DC power of functional layer 34 is no greater than 900W.

[0063] Optionally, in this embodiment, the RF power of functional layer 34 ranges from 50W to 300W; the DC power of functional layer 34 ranges from 50W to 900W.

[0064] Based on the above embodiments, in one embodiment of this application, the light transmittance of the low-resistivity ohmic contact layer 31, buffer layer 32, first transparent conductive layer 331, and second transparent conductive layer 333 is all greater than 80%; the light transmittance of the nano-metal layer 332 is greater than 70%; and the light transmittance of the functional layer 34 is greater than 85%. Light transmittance refers to the transmittance of light within the visible light wavelength range.

[0065] Based on the above embodiments, in one embodiment of this application, the resistivity of the low-resistance ohmic contact layer 31, buffer layer 32, first transparent conductive layer 331, second transparent conductive layer 333, and functional layer 34 is not greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer 332 ranges from no more than 10 Ωcm. -6 Ωcm.

[0066] Optionally, in this embodiment, the resistivity of the low-resistivity ohmic contact layer 31 ranges from 1.0 to 10⁻⁶. -3 -1.0*10 -2 Ωcm, including endpoint values.

[0067] Optionally, in this embodiment, the resistivity of the buffer layer 32, the first transparent conductive layer 331, the second transparent conductive layer 333, and the functional layer 34 are all in the range of 2.0*10⁻⁶. -3 -1.0*10 -2 Ωcm, including endpoint values.

[0068] Optionally, in this embodiment, the resistivity of the nano-metal layer 332 ranges from 0 to 10. -6 Ωcm, including endpoint values.

[0069] Based on the above embodiments, in one embodiment of this application, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio range of h1:h2:h3 is 3:0.1:80 to 18:5:95.

[0070] It should be noted that in this embodiment, the higher the proportion of the low-resistance ohmic contact layer thickness, the lower the contact resistance and the corresponding lower the light transmittance; the higher the proportion of the nano-metal layer thickness, the lower the conduction resistance and the better the current conduction effect, and the corresponding lower the light transmittance; the higher the proportion of the functional layer thickness, the higher the light transmittance and the corresponding higher conduction resistance. The resistivity and transmittance of the composite transparent conductive film 3 can be adjusted by adjusting the thickness proportions of the low-resistance ohmic contact layer 31, the nano-metal layer 332 and the functional layer 34.

[0071] Based on the above embodiments, in one embodiment of this application, such as Figure 5 As shown, in each cycle of the current conducting layer 33, there is a roughened interface between the first transparent conductive layer 331 and the second transparent conductive layer 333. The nano metal layer 332 is a discontinuous thin film that diffuses into the groove of the roughened interface. The nano metal layer 332 is covered by the first transparent conductive layer 331 and the second transparent conductive layer 333.

[0072] Among them, the nano metal layer 332 is formed by high-temperature annealing and recrystallization of the metal material layer, which increases the surface energy of the nano metal layer 332 by more than 40%. The total thickness of the metal material layer ranges from 0nm to 5nm, excluding the endpoint values.

[0073] Optionally, in this embodiment, the high-temperature annealing temperature of the nano-metal layer 332 is not less than 500℃.

[0074] Based on the above embodiments, in one embodiment of this application, the single-layer thickness of the first transparent conductive layer 331 and the second transparent conductive layer 333 is in the range of 0nm-15nm, excluding the endpoint values; the total thickness of the nano metal layer 332 is in the range of 0nm-5nm, excluding the endpoint values.

[0075] Based on the above embodiments, in one embodiment of this application, one of the first type semiconductor layer 21 and the second type semiconductor layer 23 is an N-type semiconductor layer and the other is a P-type semiconductor layer.

[0076] It should be noted that this application does not limit the specific doping type of the first type semiconductor layer 21 and the second type semiconductor layer 23. The first type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer, and the materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN. Optionally, in this embodiment, the first type semiconductor layer 21 is an N-type semiconductor layer, and the second type semiconductor layer 23 is a P-type semiconductor layer.

[0077] Based on the above embodiments, in one embodiment of this application, the materials of the low-resistivity ohmic contact layer 31, buffer layer 32, first transparent conductive layer 331, second transparent conductive layer 333, and functional layer 34 are all low-resistivity, high-transmittance materials.

[0078] Optionally, in this embodiment, the low-resistance, high-transmittance material includes, but is not limited to, one or more stacks of ZnO, In2O3, TiO2, SnO2, ITO (indium tin oxide), ATO (indium-doped tin oxide), FTO (fluorine-doped tin oxide), and IGZO (indium gallium-doped tin oxide).

[0079] Specifically, in one embodiment of this application, the fabrication of the low-resistivity ohmic contact layer 31 includes: forming the low-resistivity ohmic contact layer 31 on the surface of the second type semiconductor layer 23 using a single-target sputtering method; optionally, the low-resistivity ohmic contact layer 31 is fabricated using an ITO target; the distance between the target of the low-resistivity ohmic contact layer 31 and the epitaxial structure 2 is not less than 100 mm; optionally, the distance between the target of the low-resistivity ohmic contact layer 31 and the epitaxial structure 2 is 100 mm to 150 mm, including the endpoints; the deposition rate of the low-resistivity ohmic contact layer 31 is not greater than 1.5 A / s; optionally, the deposition rate of the low-resistivity ohmic contact layer 31 is 0.1 A / s to 1.5 A / s, including the endpoints; and the thickness of the low-resistivity ohmic contact layer 31 is 5 nm to 25 nm, including the endpoints.

[0080] Specifically, in one embodiment of this application, the preparation of the buffer layer 32 includes: forming the buffer layer 32 on the surface of the low-resistivity ohmic contact layer 31 by single-target sputtering. Optionally, the buffer layer 32 is prepared using an ITO target. The distance between the target of the buffer layer 32 and the epitaxial structure 2 ranges from 80mm to 100mm, including the endpoint value. The deposition rate of the buffer layer 32 is not greater than <5A / S. Optionally, the deposition rate of the buffer layer 32 ranges from 1A / S to 5A / S, including the endpoint value. The thickness of the buffer layer 32 ranges from 5nm to 25nm, including the endpoint value.

[0081] Specifically, in one embodiment of this application, the fabrication of the current-conducting layer 33 includes: forming the current-conducting layer 33 on the surface of the buffer layer 32 using a multi-target co-sputtering method. The multi-target includes a first dielectric target, a metal target, and a second dielectric target. Specifically, the first dielectric target, the metal target, and the second dielectric target are sequentially sputtered on the surface of the buffer layer 32 to form a stacked first transparent conductive layer 331, a nano-metal layer 332, and a second transparent conductive layer 333, constituting one cycle. Multiple cycles are repeated to form a periodic structure. Optionally, the first dielectric... The target material and the second dielectric target material are ITO targets. The distance between the target material of the current conducting layer 33 and the epitaxial structure 2 is 80mm-150mm, including the endpoint value. The deposition rate of the first transparent conductive layer 331 and the second transparent conductive layer 333 is 0.1A / S-5A / S, including the endpoint value. The deposition rate of the nano metal layer 332 is not greater than 0.5A / S. Optionally, the deposition rate of the nano metal layer 332 is 0.1A / S-0.5A / S, including the endpoint value.

[0082] Optionally, in this embodiment, the material of the nano metal layer 332 includes, but is not limited to, one or more stacks of Al, Ag, Al-Ag alloy, and Al-Cu alloy.

[0083] Specifically, in one embodiment of this application, the preparation of the functional layer 34 includes: sputtering the functional layer 34 on the surface of the current conducting layer 33 using a magnetron sputtering process. Optionally, the functional layer 34 is prepared using an ITO target. The distance between the target of the functional layer 34 and the epitaxial structure 2 ranges from 50mm to 150mm, including the endpoint value. The deposition rate of the functional layer 34 ranges from 0.1A / s to 5A / s, including the endpoint value.

[0084] Optionally, in this embodiment, the thickness of the functional layer 34 ranges from 20nm to 500nm, including the endpoint values.

[0085] This embodiment provides a miniature light-emitting diode epitaxial wafer, which is fabricated using the above-described method. (Refer to...) Figure 3 , Figure 4 As shown, the epitaxial wafer of the miniature light-emitting diode includes:

[0086] Substrate 1;

[0087] An epitaxial structure 2 and a composite transparent conductive film 3 are sequentially stacked on a substrate 1. The epitaxial structure 2 includes a first type semiconductor layer 21, an active region 22 and a second type semiconductor layer 23 sequentially stacked along a first direction.

[0088] The composite transparent conductive film 3 includes a low-resistance ohmic contact layer 31, a buffer layer 32, a current-conducting layer 33, and a functional layer 34 stacked sequentially along a first direction. The current-conducting layer 33 has a periodic structure, and each period includes a first transparent conductive layer 331, a nano-metal layer 332, and a second transparent conductive layer 333 stacked sequentially along the first direction. The first direction is perpendicular to the substrate 1 and points from the substrate 1 to the epitaxial structure 2.

[0089] Based on the above embodiments, in one embodiment of this application, the thickness of the low-resistivity ohmic contact layer 31 ranges from 5nm to 25nm, including the endpoint values.

[0090] Based on the above embodiments, in one embodiment of this application, the thickness of the buffer layer 32 ranges from 5nm to 25nm, including the endpoint values.

[0091] Based on the above embodiments, in one embodiment of this application, the single-layer thickness of the first transparent conductive layer 331 and the second transparent conductive layer 333 is in the range of 0nm-15nm, excluding the endpoint values; the total thickness of the nano metal layer 332 is in the range of 0nm-5nm, excluding the endpoint values.

[0092] Based on the above embodiments, in one embodiment of this application, the thickness of the functional layer 34 ranges from 20nm to 500nm, including the endpoint values.

[0093] Based on the above embodiments, in one embodiment of this application, the material of the nano metal layer 332 includes, but is not limited to, one or more stacks of Al, Ag, Al-Ag alloy, and Al-Cu alloy.

[0094] Based on the above embodiments, in one embodiment of this application, the materials of the low-resistivity contact layer, buffer layer 32, first transparent conductive layer 331, second transparent conductive layer 333 and functional layer 34 are all low-resistivity and high-transmittance materials.

[0095] Optionally, in this embodiment, the low-resistance, high-transmittance material includes, but is not limited to, one or more stacks of ZnO, In2O3, TiO2, SnO2, ITO (indium tin oxide), ATO (indium-doped tin oxide), FTO (fluorine-doped tin oxide), and IGZO (indium gallium-doped tin oxide).

[0096] Based on the above embodiments, in one embodiment of this application, the light transmittance of the low-resistivity ohmic contact layer 31, buffer layer 32, first transparent conductive layer 331, and second transparent conductive layer 333 is all greater than 80%; the light transmittance of the nano-metal layer 332 is greater than 70%; and the light transmittance of the functional layer 34 is greater than 85%. Light transmittance refers to the transmittance of light within the visible light wavelength range.

[0097] Based on the above embodiments, in one embodiment of this application, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio range of h1:h2:h3 is 3:0.1:80 to 18:5:95.

[0098] It should be noted that in this embodiment, the higher the proportion of the low-resistance ohmic contact layer thickness, the lower the contact resistance and the corresponding lower the light transmittance; the higher the proportion of the nano-metal layer thickness, the lower the conduction resistance and the better the current conduction effect, and the corresponding lower the light transmittance; the higher the proportion of the functional layer thickness, the higher the light transmittance and the corresponding higher conduction resistance. The resistivity and transmittance of the composite transparent conductive film 3 can be adjusted by adjusting the thickness proportions of the low-resistance ohmic contact layer 31, the nano-metal layer 332 and the functional layer 34.

[0099] Based on the above embodiments, in one embodiment of this application, the resistivity of the low-resistance ohmic contact layer 31, buffer layer 32, first transparent conductive layer 331, second transparent conductive layer 333, and functional layer 34 is not greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer 332 ranges from no more than 10 Ωcm. -6 Ωcm.

[0100] Optionally, in this embodiment, the resistivity of the low-resistivity ohmic contact layer 31 ranges from 1.0 to 10⁻⁶. -3 -1.0*10 -2 Ωcm, including endpoint values.

[0101] Optionally, in this embodiment, the resistivity of the buffer layer 32, the first transparent conductive layer 331, the second transparent conductive layer 333, and the functional layer 34 are all in the range of 2.0*10⁻⁶. -3 -1.0*10 -2 Ωcm, including endpoint values.

[0102] Optionally, in this embodiment, the resistivity of the nano-metal layer 332 ranges from 0 to 10. -6 Ωcm, including endpoint values.

[0103] Based on the above embodiments, in one embodiment of this application, one of the first type semiconductor layer 21 and the second type semiconductor layer 23 is an N-type semiconductor layer and the other is a P-type semiconductor layer.

[0104] It should be noted that this application does not limit the specific doping type of the first type semiconductor layer 21 and the second type semiconductor layer 23. The first type semiconductor layer 21 can be a P-type semiconductor layer or an N-type semiconductor layer, and the materials of the N-type semiconductor layer and the P-type semiconductor layer can be GaN. Optionally, in this embodiment, the first type semiconductor layer 21 is an N-type semiconductor layer, and the second type semiconductor layer 23 is a P-type semiconductor layer.

[0105] Based on the above embodiments, in one embodiment of this application, reference is made to... Figure 5 As shown, in each cycle of the current conducting layer 33, there is a roughened interface between the first transparent conductive layer 331 and the second transparent conductive layer 333. The nano metal layer 332 is a discontinuous thin film that diffuses into the groove of the roughened interface. The nano metal layer 332 is covered by the first transparent conductive layer 331 and the second transparent conductive layer 333.

[0106] In summary, the above technical solution achieves the following results:

[0107] The method for fabricating a micro LED epitaxial wafer provided in this embodiment includes, on the one hand, growing a composite transparent conductive film by: sequentially fabricating a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer, and a functional layer on the surface of a second-type semiconductor layer using a radio frequency combined with DC sputtering method within a reaction chamber. This improves the density of the composite transparent conductive film and the ohmic contact between the composite transparent conductive film and the second-type semiconductor layer, thereby enhancing the ESD capability of the composite transparent conductive film. This avoids the problem of insufficient density or poor ohmic contact between the transparent conductive layer and the epitaxial structure caused by the single-layer deposition method used in existing semiconductor processing, which results in localized heat dissipation and significant thermal effects leading to breakdown in the transparent conductive layer area; and the current conduction... The layer has a periodic structure, which can improve the conductivity of the composite transparent conductive film. Each period includes a first transparent conductive layer, a nano-metal layer, and a second transparent conductive layer stacked sequentially, which can improve the conductivity of the current conducting layer. At the same time, the low-resistance ohmic contact layer can reduce the contact resistance between the composite transparent conductive film and the second type semiconductor layer. The buffer layer can enable the island-shaped nano-metal layer to achieve very low resistance at a very thin thickness. Furthermore, the periodic structure of the buffer layer combined with the current conducting layer can increase the carrier concentration, thereby improving the current spreading effect and reducing the conduction resistance, which facilitates the formation of a high-transmittance film layer for the functional layer. The combination of the low-resistance ohmic contact layer, buffer layer, current conducting layer, and functional layer achieves the goal of preparing a composite transparent conductive film with low resistivity, high transmittance, and high stability.

[0108] On the other hand, the low-resistance ohmic contact layer, buffer layer and current conduction layer are prepared by using a power ratio of RF / DC > 2:1, which can increase the plasma concentration in the reaction chamber, further improve the light transmittance of the composite transparent conductive film, and the higher RF power can reduce the tip discharge caused by electron accumulation on the target surface, further improving the reliability of the composite transparent conductive film.

[0109] The functional layer is fabricated with a power ratio of RF / DC < 1:3. The functional layer increases the E intensity (electric field strength) by using higher DC power to improve the deposition rate of the functional layer, thereby improving the density and light transmittance of the composite transparent conductive film.

[0110] Furthermore, the power ratio of radio frequency (RF) to DC in the first transparent conductive layer is set to be smaller than that in the second transparent conductive layer. The smaller RF to DC power ratio in the first transparent conductive layer can form an amorphous thin film with a smaller lattice, which is more conducive to the formation of a low resistivity and high transmittance film layer in the subsequent nano metal layer.

[0111] Furthermore, the RF power of the low-resistivity contact layer is set to be no greater than 150W, and the DC power of the low-resistivity contact layer is set to be no greater than 50W. Low-power deposition of the low-resistivity contact layer is adopted to achieve a lower deposition rate, which can form an amorphous thin film and a thin film with a work function close to that of the type II semiconductor layer to form a good ohmic contact. The lower power can also reduce the tip discharge caused by electron accumulation on the target surface, thereby reducing damage to the type II semiconductor layer. This reduces the contact resistance between the composite transparent conductive film and the type II semiconductor layer and improves the ESD capability of the composite transparent conductive film.

[0112] Furthermore, the proportion of the thickness of the low-resistance ohmic contact layer to the total thickness of the composite transparent conductive film is h1, the proportion of the total thickness of the nano-metal layer to the total thickness of the composite transparent conductive film is h2, and the proportion of the thickness of the functional layer to the total thickness of the composite transparent conductive film is h3. Then, the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:95. Setting the thickness proportion of each layer not only enhances the current conduction capability of the composite transparent conductive film, but also matches the low-resistance ohmic contact layer formed by low power, thereby improving the ESD capability of the composite transparent conductive film. Moreover, by adjusting the thickness proportion of the low-resistance ohmic contact layer, the nano-metal layer, and the functional layer, the resistivity and light transmittance of the composite transparent conductive film can be adjusted.

[0113] Furthermore, in each cycle of the current-conducting layer, there is a roughened interface between the first and second transparent conductive layers. The nano-metal layer is a discontinuous thin film that diffuses into the grooves of the roughened interface. The nano-metal layer is covered by the first and second transparent conductive layers. The nano-metal layer is formed by high-temperature annealing and recrystallization of a metal material layer, which increases the surface energy of the nano-metal layer by more than 40%. The total thickness of the metal material layer ranges from 0 nm to 5 nm, excluding the endpoint values. The current-conducting layer can form an embedded structure. By controlling the thickness range of the metal material layer, a very thin metal material layer is formed into a nano-metal layer after high-temperature annealing. The roughened interface between the first and second transparent conductive layers allows the nano-metal layer to diffuse into the grooves of the roughened interface, enabling the nano-metal layer to expand the current laterally in the current-conducting layer, which can reduce the resistance and improve the conductivity of the current-conducting layer. The first and second transparent conductive layers can also prevent the metal ions of the nano-metal layer from diffusing to the PN junction and causing leakage, thus affecting the reliability and conductivity of the composite transparent conductive film.

[0114] The micro LED epitaxial wafer provided in this embodiment is fabricated using the aforementioned method for fabricating micro LED epitaxial wafers. This method can improve the density of the composite transparent conductive film and the ohmic contact between the composite transparent conductive film and the second type semiconductor layer, thereby improving the ESD capability of the composite transparent conductive film. It avoids the problem of insufficient density of the transparent conductive layer or poor ohmic contact between the transparent conductive layer and the epitaxial structure, which would lead to local heat not being dissipated and thus generate a large thermal effect that causes the transparent conductive layer area to break down.

[0115] Those skilled in the art should understand that, in the disclosure of this invention, the terms "lateral", "longitudinal", "upper", "lower", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting this invention.

[0116] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0117] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating a micro light-emitting diode epitaxial wafer, characterized in that, include: Provide substrate; An epitaxial structure and a composite transparent conductive film are sequentially grown on the substrate. The epitaxial structure includes a first type semiconductor layer, an active region, and a second type semiconductor layer sequentially stacked along the growth direction. The growth of the composite transparent conductive film includes: in the reaction chamber, a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer and a functional layer are sequentially prepared on the surface of the second type semiconductor layer by a combination of radio frequency and DC sputtering. The current-conducting layer is a periodic structure, and each period includes a first transparent conductive layer, a nano metal layer and a second transparent conductive layer sequentially stacked along the growth direction. In each cycle of the current-conducting layer, there is a roughened interface between the first transparent conductive layer and the second transparent conductive layer. The nano-metal layer is a discontinuous thin film that diffuses into the grooves of the roughened interface. The nano-metal layer is covered by the first transparent conductive layer and the second transparent conductive layer. The nano-metal layer is formed by high-temperature annealing and recrystallization of a metal material layer, which increases the surface energy of the nano-metal layer by more than 40%. The total thickness of the metal material layer ranges from 0 nm to 5 nm, excluding the endpoint values.

2. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: The low-resistance ohmic contact layer, buffer layer and current conduction layer are fabricated with a power ratio of RF / DC > 2:

1. The functional layer is fabricated using a power ratio of RF / DC < 1:

3.

3. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: The ratio of radio frequency (RF) power to DC power in the first transparent conductive layer is less than that in the second transparent conductive layer.

4. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: The radio frequency power of the low-resistance ohmic contact layer is no greater than 150W, and the DC power of the low-resistance ohmic contact layer is no greater than 50W.

5. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: The light transmittance of the low-resistivity ohmic contact layer, buffer layer, first transparent conductive layer, and second transparent conductive layer is greater than 80%; the light transmittance of the nano-metal layer is greater than 70%; and the light transmittance of the functional layer is greater than 85%.

6. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: The resistivity of the low-resistivity ohmic contact layer, buffer layer, first transparent conductive layer, second transparent conductive layer, and functional layer is no greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer is not greater than 10 Ωcm. -6 Ωcm.

7. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: If the thickness of the low-resistance ohmic contact layer accounts for h1 of the total thickness of the composite transparent conductive film, the thickness of the nano-metal layer accounts for h2 of the total thickness of the composite transparent conductive film, and the thickness of the functional layer accounts for h3 of the total thickness of the composite transparent conductive film, then the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:

95.

8. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 1, characterized in that: One of the first type semiconductor layer and the second type semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

9. A micro light-emitting diode epitaxial wafer, characterized in that, The micro LED epitaxial wafer is fabricated using the fabrication method of any one of claims 1 to 8, wherein the micro LED epitaxial wafer comprises: Substrate; An epitaxial structure and a composite transparent conductive film are sequentially stacked on the substrate. The epitaxial structure includes a first type semiconductor layer, an active region, and a second type semiconductor layer sequentially stacked along a first direction. The composite transparent conductive film includes a low-resistance ohmic contact layer, a buffer layer, a current-conducting layer, and a functional layer stacked sequentially along the first direction. The current-conducting layer has a periodic structure, and each period includes a first transparent conductive layer, a nano-metal layer, and a second transparent conductive layer stacked sequentially along the first direction. The first direction is perpendicular to the substrate and points from the substrate to the epitaxial structure.

10. The micro light-emitting diode epitaxial wafer according to claim 9, characterized in that: The resistivity of the low-resistivity ohmic contact layer, buffer layer, first transparent conductive layer, second transparent conductive layer, and functional layer is no greater than 1.0*10. -2 Ωcm; the resistivity of the nano-metal layer is not greater than 10 Ωcm. -6 Ωcm.

11. The method for fabricating a micro light-emitting diode epitaxial wafer according to claim 9, characterized in that: If the thickness of the low-resistance ohmic contact layer accounts for h1 of the total thickness of the composite transparent conductive film, the thickness of the nano-metal layer accounts for h2 of the total thickness of the composite transparent conductive film, and the thickness of the functional layer accounts for h3 of the total thickness of the composite transparent conductive film, then the ratio of h1:h2:h3 ranges from 3:0.1:80 to 18:5:95.

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