Photonic integrated chip structure and manufacturing method thereof

Abstract

The present invention discloses a photon integrated chip structure and a manufacturing method thereof, which belongs to the field of semiconductor laser technology and can effectively realize P\N electrical isolation between discrete devices in an integrated chip, thereby performing P\N double-sided RF driving on the device. The photon integrated chip structure includes: a substrate; a buffer layer formed on the substrate; a bottom conductive layer formed on the buffer layer, which includes a plurality of bottom conductive areas, a bottom isolation area is provided between two adjacent bottom conductive areas, and the bottom isolation area is used to isolate the two adjacent bottom conductive areas; the type of impurities doped in the bottom isolation area is opposite to that in the adjacent bottom conductive areas; a core layer, which includes a plurality of core areas, and the core areas correspond to the bottom conductive areas one by one; a top conductive layer, which includes a plurality of top conductive areas, and the top conductive areas correspond to the core areas one by one, and there is a top isolation area between two adjacent top conductive areas. The present invention is used for P\N electrical isolation between discrete devices in a photon integrated chip.

Description

Technical Field

[0001] The invention relates to a photon integrated chip structure and a manufacturing method thereof, belonging to the technical field of semiconductor lasers. Background Art

[0002] A photonic integrated chip is a device structure formed by integrating multiple independent photonic devices on the same substrate. It is common to integrate one or more of the lasers, modulators, optical amplifiers and detectors on semiconductor III-V materials or Si substrates. Most traditional photonic integrated chips are based on N-type substrate materials, and all devices share a common N pole. This type of photonic integrated chip can only perform P isolation on discrete photonic devices, but cannot achieve N isolation, so each device can only be driven by single-ended RF. If the P and N electrodes of each device in the photonic integrated chip can be electrically isolated at the same time, the crosstalk between devices can be significantly reduced, thereby achieving P\N double-sided RF drive of the photonic chip.

[0003] A common electrical isolation method in photonic integrated chips is to deeply etch the structure, completely or partially etching the P-type material between the two devices, greatly increasing the P isolation resistance between the devices, thereby blocking the crosstalk between the P electrodes of the devices. Although we can also etch the N-type material on one side of the substrate to achieve N isolation, the various optical devices on the integrated chip generally need to be dissipated through the substrate. Etching the N-type material on one side of the substrate will greatly increase the thermal resistance, causing the junction temperature of the optical device to rise significantly, which not only limits the operating current of the optical device, but also greatly increases the reliability risk of the device.

[0004] Electrical isolation between chips can also be achieved through ion implantation and diffusion. In order to avoid the impact of injected particles or diffused elements on epitaxial growth, both implantation and diffusion need to be performed after the epitaxy is completed. In this case, due to the deep implantation depth, high particle implantation energy is required. Not only is the equipment expensive, but high-energy particles will also have an uncontrollable impact on the optical properties of the epitaxial material. For diffusion schemes, especially those that require inverting the material type, in order to achieve electrical isolation, a deeper diffusion depth and a greater diffusion concentration are required, which will increase the diffusion time, and a large number of diffused elements will increase the loss of the optical waveguide. These diffused elements are unstable in subsequent processes and will also affect the reliability of the device. Summary of the invention

[0005] The present invention provides a photonic integrated chip structure and a manufacturing method thereof, which can effectively realize P\N electrical isolation between discrete devices in the integrated chip, thereby performing P\N double-side radio frequency driving on the devices.

[0006] In one aspect, the present invention provides a photonic integrated chip structure, comprising:

[0007] substrate;

[0008] a buffer layer formed on the substrate;

[0009] A bottom conductive layer is formed on the buffer layer, and includes a plurality of bottom conductive regions, wherein a bottom isolation region is provided between two adjacent bottom conductive regions, and the bottom isolation region is used to isolate the two adjacent bottom conductive regions; the type of impurities doped in the bottom isolation region is opposite to that in the adjacent bottom conductive regions;

[0010] A core layer, formed on the bottom conductive layer, comprising a plurality of core regions, wherein the core regions correspond one to one with the bottom conductive regions;

[0011] The top conductive layer is formed on the core layer and includes a plurality of top conductive regions. The top conductive regions correspond to the core regions one by one, and a top isolation region is provided between two adjacent top conductive regions.

[0012] Optionally, a light transmission area is provided between two adjacent core areas.

[0013] Optionally, the bottom conductive region is doped with impurities of opposite types to those in the buffer layer; and the substrate is of P-type, N-type or semi-insulating type.

[0014] Optionally, the top isolation region is formed by an etching process or a doping process; the width of the top isolation region is greater than the width of the light transmission region; the distance from the left edge of the top isolation region to the left edge of the light transmission region, and the distance from the right edge of the top isolation region to the right edge of the light transmission region are both greater than or equal to 1um.

[0015] Optionally, the bottom isolation region is a P-type doped or N-type doped semiconductor layer.

[0016] Optionally, the thickness of the bottom conductive region is greater than or equal to 500nm; the thickness difference between the bottom isolation region and the bottom conductive region is no more than 300nm; the distance from the left edge of the bottom isolation region to the left edge of the light transmission region, and the distance from the right edge of the bottom isolation region to the right edge of the light transmission region are both less than or equal to 10um.

[0017] Optionally, the material of the light transmission region is a multi-component semiconductor compound.

[0018] On the other hand, the present invention provides a method for manufacturing a photonic integrated chip structure based on any one of the above, the method comprising:

[0019] forming a buffer layer on a substrate;

[0020] forming a bottom isolation region on the buffer layer, and forming a bottom conductive region on both sides of the bottom isolation region;

[0021] forming a corresponding core region on the bottom conductive region;

[0022] A corresponding top conductive region is formed on the core region, and a top isolation region is formed between two adjacent top conductive regions.

[0023] Optionally, after forming a corresponding core region on the bottom conductive region, the method further includes:

[0024] A light transmission area is formed between two adjacent core areas.

[0025] Optionally, forming a bottom isolation region on the buffer layer, and forming a bottom conductive region on both sides of the bottom isolation region, specifically includes:

[0026] forming a bottom isolation layer on the buffer layer, and performing an etching process on the bottom isolation layer to obtain a bottom isolation region;

[0027] A bottom conductive region is epitaxially grown on the buffer layer in regions located on both sides of the bottom isolation region.

[0028] The beneficial effects that the present invention can produce include:

[0029] The photonic integrated chip structure provided by the present invention realizes bottom electrical isolation by setting a bottom isolation region between two adjacent bottom conductive regions, wherein the type of impurities doped in the bottom isolation region is opposite to that in the adjacent bottom conductive regions, thereby forming an inversion blocking junction; and electrical isolation is achieved between two adjacent top conductive regions through the top isolation region, thereby realizing P\N electrical isolation between discrete devices in the integrated chip, thereby enabling P\N double-sided RF driving of the device, and at the same time, no crosstalk to other devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 A schematic cross-sectional view of a photonic integrated chip structure provided by an embodiment of the present invention;

[0031] Figure 2 A schematic diagram of the structure of an epitaxial buffer layer and a bottom isolation layer on a substrate provided by an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of a structure after a mask is deposited on a bottom isolation layer and photolithography and etching are completed according to an embodiment of the present invention;

[0033] Figure 4 A schematic diagram of the structure behind the bottom conductive region of the epitaxial sub-device provided in an embodiment of the present invention;

[0034] Figure 5 A schematic diagram of the structure after epitaxy of the first core layer of the first sub-device provided in an embodiment of the present invention;

[0035] Figure 6 A schematic diagram of the structure after epitaxy of the second core region of the second sub-device provided in an embodiment of the present invention;

[0036] Figure 7 A schematic structural diagram of an epitaxial light transmission region after selective etching at the junction of the core regions of the first sub-device and the second sub-device provided in an embodiment of the present invention;

[0037] Figure 8 A schematic diagram of the structure after epitaxy of the top conductive regions of the first sub-device and the second sub-device provided in an embodiment of the present invention;

[0038] Fig. 9 A schematic diagram of the structure after forming a top isolation region provided by an embodiment of the present invention.

[0039] Reference numerals:

[0040] 100. First sub-device; 200. Second sub-device; 10. Substrate; 20. Buffer layer; 31. First bottom conductive region; 32. Second bottom conductive region; 33. Bottom isolation region; 34. Bottom isolation layer; 41. First core region; 42. Second core region; 43. Light transmission region; 44. First core layer; 51. First top conductive region; 52. Second top conductive region; 53. Top isolation region; 54. First conductive layer; 61. First mask. DETAILED DESCRIPTION

[0041] The present invention is described in detail below in conjunction with embodiments, but the present invention is not limited to these embodiments.

[0042] The embodiment of the present invention provides a photonic integrated chip structure, such as Figure 1 As shown, including:

[0043] Substrate 10.

[0044] The substrate 10 can be configured as a P-type, N-type or semi-insulating semiconductor; its P-type dopant can be Zn, its N-type dopant can be S or Si, and its semi-insulating dopant can be Fe.

[0045] The material of the substrate 10 may be InP or GaAs, etc., which is not limited in the embodiment of the present invention.

[0046] The buffer layer 20 is formed on the substrate 10 .

[0047] The buffer layer 20 can be set as a P-type, N-type, non-doped or semi-insulating semiconductor to achieve isolation between the sub-devices thereon and the substrate 10; its P-type dopant can be Zn, its N-type dopant can be S or Si, and its semi-insulating dopant can be Fe;

[0048] The material of the buffer layer 20 may be InP or GaAs, etc., which is not limited in the embodiment of the present invention.

[0049] The bottom conductive layer is formed on the buffer layer 20, and includes a plurality of bottom conductive regions. A bottom isolation region 33 is provided between two adjacent bottom conductive regions. The bottom isolation region 33 is used to isolate the two adjacent bottom conductive regions. The type of impurities doped in the bottom isolation region 33 is opposite to that in the adjacent bottom conductive regions.

[0050] The bottom isolation region 33 is a P-type doped or N-type doped semiconductor layer, and the type of doping impurities in the bottom conductive region is opposite to that in the buffer layer 20. The thickness of the bottom conductive region is generally greater than or equal to 500nm; the difference in thickness between the bottom isolation region 33 and the bottom conductive region is generally not more than 300nm.

[0051] The embodiment of the present invention is described by taking the formation of two sub-devices on the buffer layer 20 as an example. The two sub-devices are respectively denoted as a first sub-device 100 and a second sub-device 200. The first sub-device 100 and the second sub-device 200 can be lasers, modulators or optical amplifiers.

[0052] Taking two sub-devices as an example, two bottom conductive regions are formed on the buffer layer 20, which are respectively denoted as the first bottom conductive region 31 and the second bottom conductive region 32. The first bottom conductive region 31 and the second bottom conductive region 32 can be set to P-type doped or N-type doped semiconductors, then the bottom isolation region 33 set between the first bottom conductive region 31 and the second bottom conductive region 32 can be an N-type doped or P-type doped semiconductor. The bottom isolation region 33 has a different polarity from the bottom conductive region, so that an inversion blocking junction can be formed to achieve bottom electrical isolation.

[0053] In the actual manufacturing process, SiOx or SiNx can be deposited on the surface of the bottom isolation layer 34 as a mask, and other areas can be selectively etched to form a bottom isolation area 33, and then the first bottom conductive area 31 and the second bottom conductive area 32 are epitaxially grown on both sides of the bottom isolation area 33; etching the bottom isolation layer 34 can be achieved by dry etching or wet etching.

[0054] The core layer is formed on the bottom conductive layer and includes a plurality of core regions, and the core regions correspond to the bottom conductive regions one by one.

[0055] Taking two sub-devices as an example, two core areas are formed on the bottom conductive layer, which are respectively recorded as the first core area 41 and the second core area 42. The two core areas can be directly connected or butt-jointed in the middle to grow a light transmission area 43 of other materials; the relative position of the light transmission area 43 and the bottom isolation area 33 is not fixed, that is, the left end surface of the light transmission area 43 can be located on the left, middle or right side of the bottom isolation area 33. Preferably, the distance between the left edge of the bottom isolation area 33 and the left edge of the light transmission area 43, and the distance between the right edge of the bottom isolation area 33 and the right edge of the light transmission area 43 are both less than or equal to 10um.

[0056] The material of the light transmission region 43 may be a multi-component semiconductor compound. The first core region 41 and the second core region 42 may be made of the same or different epitaxial materials.

[0057] The first core region 41 and the second core region 42 both include a transition layer, a lower confinement layer, an active layer, an upper confinement layer and other structures from bottom to top; the active layer material may be a multiple quantum well of InGaAsP or InGaAlAs.

[0058] By epitaxially growing a light transmission region 43 of other materials between the first core region 41 and the second core region 42 , current crosstalk between the weakly doped confinement layers at the lower side of the core region can be blocked, thereby further improving the isolation effect.

[0059] After the core area of ​​the first sub-device 100 is epitaxially grown, part of the area can be selectively removed by dry etching or wet etching to further epitaxially grow the core area of ​​the second sub-device 200; then, the joint between the core areas of the first sub-device 100 and the second sub-device 200 is selectively etched, and then the light transmission area 43 is epitaxially grown.

[0060] The top conductive layer is formed on the core layer and includes a plurality of top conductive regions. The top conductive regions correspond to the core regions one by one, and a top isolation region 53 is provided between two adjacent top conductive regions.

[0061] The top isolation region 53 is formed by an etching process or a doping process. Specifically, the top isolation of the first sub-device 100 and the second sub-device 200 can be achieved by deep etching in a specific area to remove the top conductive region or by using ion implantation and diffusion.

[0062] Preferably, the width of the top isolation region 53 is greater than the width of the light transmission region 43; the distance from the left edge of the top isolation region 53 to the left edge of the light transmission region 43, and the distance from the right edge of the top isolation region 53 to the right edge of the light transmission region 43 are both greater than or equal to 1um.

[0063] Taking two sub-devices as an example, two top conductive regions are formed on the core layer, which are respectively recorded as a first top conductive region 51 and a second top conductive region 52. The materials of the first top conductive region 51 and the second top conductive region 52 can be InGaAs or InAlAs. The first top conductive region 51 and the second top conductive region 52 can use the same or different epitaxial materials.

[0064] In practical applications, the electrodes connected to the bottom conductive region in the first sub-device 100 and the second sub-device 200 are covered with metal in their respective bottom conductive regions and extend to the top surface to form a coplanar electrode structure with the top surface electrode.

[0065] The photon integrated chip structure provided by the present invention can form a pnp or npn inversion junction isolation on the bottom conductive layer. The epitaxial isolation method of the present invention can greatly reduce the concentration of doping elements and reduce the influence of impurity atoms on device performance and reliability.

[0066] Another embodiment of the present invention provides a method for manufacturing any of the above-mentioned photonic integrated chip structures, the method comprising:

[0067] S1 . Form a buffer layer 20 on a substrate 10 .

[0068] S2 . Form a bottom isolation region 33 on the buffer layer 20 , and form bottom conductive regions on both sides of the bottom isolation region 33 .

[0069] S3. Form a corresponding core region on the bottom conductive region.

[0070] S4. Form a corresponding top conductive region on the core region, and form a top isolation region 53 between two adjacent top conductive regions.

[0071] Furthermore, after forming the corresponding core region on the bottom conductive region, the method further includes: forming a light transmission region 43 between two adjacent core regions.

[0072] In an embodiment of the present invention, a bottom isolation region 33 is formed on the buffer layer 20, and a bottom conductive region is formed on both sides of the bottom isolation region 33, specifically comprising: firstly forming a bottom isolation layer 34 on the buffer layer 20, and performing an etching process on the bottom isolation layer 34 to obtain the bottom isolation region 33; and then epitaxially growing the bottom conductive region in the region on both sides of the bottom isolation region 33 on the buffer layer 20.

[0073] Another embodiment of the present invention provides a specific method for manufacturing a photonic integrated chip structure, the method comprising:

[0074] (1) The buffer layer 20 and the bottom isolation layer 34 are epitaxially grown on the substrate 10 .

[0075] refer to Figure 2 As shown, at this stage, the substrate 10 may be selected as a semi-insulating semiconductor, or may be replaced by an N-type doped or P-type doped semiconductor.

[0076] The buffer layer 20 can be a P-type InP (such as Zn doping, doping concentration>1E15 cm-3), N-type InP (such as S doping and Si doping, doping concentration>1E15 cm-3) that is anti-type to the bottom conductive layer, or a non-doped, semi-insulating InP (such as Fe doping, doping concentration>1E15 cm-3) semiconductor thin layer, which is used to achieve isolation between the two sub-devices and the substrate 10.

[0077] The bottom isolation layer 34 may be a P-type doped or N-type doped semiconductor (doping concentration>1E15 cm-3).

[0078] The epitaxial process used in this process can be MOCVD (metal organic chemical vapor deposition) or MBE (molecular beam epitaxy).

[0079] (2) Deposit a mask on the bottom isolation layer 34 and perform photolithography and etching.

[0080] refer to Figure 3 As shown, at this stage, the mask material can be selected as SiOx or SiNx, which is lattice-mismatched with III-V binary or multinary compound semiconductors, and the corresponding material will not grow in the subsequent epitaxial process, so selective regional growth can be achieved.

[0081] The process first performs a photolithography step on the first mask 61 (the aforementioned SiOx or SiNx), and then uses a patterned photoresist as a second mask to selectively etch the first mask 61 by ICP (inductively coupled plasma etching) or RIE (reactive ion etching). After the etching is completed, the second mask is removed, and only the bottom isolation region 33 and the first mask 61 in a specific area are retained on the buffer layer 20.

[0082] (3) Epitaxially growing the first bottom conductive region 31 of the first sub-device 100 and the second bottom conductive region 32 of the second sub-device 200.

[0083] refer to Figure 4 As shown, at this stage, the epitaxially grown bottom conductive region is an N-type or P-type semiconductor (such as N-InP or P-InP with a doping concentration greater than 1E18 cm-3), and is only grown to a certain thickness on the buffer layer 20 not covered by the first mask 61. After the epitaxy is completed, the first mask 61 remaining in the previous step can be removed by dry etching or wet etching. After the process is completed, an npn or pnp reverse junction isolation can be formed in the lateral direction.

[0084] The typical thickness of the bottom conductive region is greater than 500 nm, and the thickness of the bottom isolation region 33 may be greater than, less than, or equal to the thickness of the bottom conductive region.

[0085] (4) Epitaxially growing the first core layer 44 of the first sub-device 100 .

[0086] refer to Figure 5 As shown, the first core layer 44 may include a transition layer, a lower confinement layer, an active layer, an upper confinement layer and the like. The gain medium of the active layer may be a strained multi-quantum well (MQW) structure formed by multi-compound semiconductors such as InGaAsP or InGaAlAs, and its thickness is greater than 10 nm.

[0087] (5) Selectively etching a portion of the first core layer 44 of the first sub-device 100 and then epitaxially growing the second core region 42 of the second sub-device 200.

[0088] refer to Figure 6 As shown, the second core region 42 of the second sub-device 200 is similar to the first core region 41 of the first sub-device 100 , and its material composition and thickness may be the same as or different from those of the first core region 41 of the first sub-device 100 .

[0089] The process first Figure 5 The structure is subjected to a photolithography process to protect the portion of the first core layer 44 (i.e., the first core region 41) of the first sub-device 100 that needs to be retained, and then the first core layer 44 of the region corresponding to the second core region 42 of the second sub-device 200 is removed by dry etching or wet etching. Further, the second core region 42 of the second sub-device 200 can be epitaxially grown in the etched region.

[0090] (6) The joint between the first sub-device 100 and the second sub-device 200 is selectively etched, and then the light transmission region 43 is epitaxially grown.

[0091] refer to Figure 7 As shown, the material of the light transmission region 43 can be a multi-element semiconductor compound such as InGaAsP, which is used to improve the light coupling efficiency between the two sub-devices in the waveguide. Figure 6 The structure is subjected to a photolithography process, and the first core region 41 of the first sub-device 100 and the part of the second core region 42 of the second sub-device 200 that need to be retained are protected, and then the unprotected core region at the interface between the two is removed by dry etching or wet etching. Further, the light transmission region 43 can be epitaxially grown in the etched area.

[0092] The thickness of the light transmission region 43 may be greater than, less than, or equal to the thickness of the first core region 41 of the first sub-device 100 and the second core region 42 of the second sub-device 200 .

[0093] The relative positions of the light transmission region 43 and the bottom isolation region 33 are not fixed, that is, the left end surface of the light transmission region 43 can be located on the left side, the middle or the right side of the bottom isolation region 33 .

[0094] (7) Epitaxially growing the top conductive regions of the first sub-device 100 and the second sub-device 200 .

[0095] The top conductive regions of the first sub-device 100 and the second sub-device 200 can use the same or different epitaxial materials, and the corresponding processes use one epitaxial growth and two epitaxial growths respectively. When the top conductive regions of the first sub-device 100 and the second sub-device 200 use the same epitaxial material, one epitaxial growth is used, that is, the first conductive layer 54 is epitaxially grown on the core layer. For details, refer to Figure 8 shown.

[0096] (8) Selectively etching or ion implanting a portion of the top conductive region where the first sub-device 100 and the second sub-device 200 are connected to form a top isolation region 53 .

[0097] refer to Fig. 9 As shown, the top isolation region 53 realizes top electrical isolation of the first sub-device 100 and the second sub-device 200 .

[0098] The relative positions of the light transmission region 43 and the top isolation region 53 are not fixed, that is, the left end surface of the light transmission region 43 can be located on the left side, the middle or the right side of the top isolation region 53 .

[0099] At this point, the first bottom conductive region 31, the first core region 41 and the first top conductive region 51 constitute a first sub-device 100; the second bottom conductive region 32, the second core region 42 and the second top conductive region 52 constitute a second sub-device 200, and the first sub-device 100 and the second sub-device 200 are electrically isolated at the bottom by the bottom isolation region 33 and are electrically isolated at the top by the top isolation region 53.

[0100] The present invention sets a bottom isolation region 33 between two adjacent bottom conductive regions. The type of impurities doped in the bottom isolation region 33 is opposite to that in the adjacent bottom conductive region, thereby forming an inversion blocking junction, thereby realizing bottom electrical isolation; the two adjacent top conductive regions are electrically isolated by the top isolation region 53, thereby realizing P\N electrical isolation between the discrete devices in the integrated chip, so that the devices can be driven by P\N double-sided RF without crosstalk to other devices.

[0101] The above are only a few embodiments of the present application and do not constitute any form of limitation to the present application. Although the present application is disclosed as above with preferred embodiments, it is not intended to limit the present application. Any technician familiar with the profession, without departing from the scope of the technical solution of the present application, using the technical content disclosed above to make slight changes or modifications are equivalent to equivalent implementation cases and fall within the scope of the technical solution.

Claims

1. A photonic integrated chip structure, characterized in that: include: substrate; a buffer layer formed on the substrate; A bottom conductive layer is formed on the buffer layer, and includes a plurality of bottom conductive regions, wherein a bottom isolation region is provided between two adjacent bottom conductive regions, and the bottom isolation region is used to isolate the two adjacent bottom conductive regions; The bottom isolation region and the adjacent bottom conductive region have doping impurities of opposite types; A core layer is formed on the bottom conductive layer, and includes a plurality of core regions, wherein the core regions correspond to the bottom conductive regions one by one; and a light transmission region is arranged between two adjacent core regions; A top conductive layer is formed on the core layer, and includes a plurality of top conductive regions, each of which corresponds to the core region one by one, and a top isolation region is provided between two adjacent top conductive regions; A distance between a left edge of the bottom isolation region and a left edge of the light transmission region, and a distance between a right edge of the bottom isolation region and a right edge of the light transmission region are both less than or equal to 10 um.

2. The photonic integrated chip structure according to claim 1, characterized in that: The bottom conductive region and the buffer layer have doping impurities of opposite types; The substrate is of P type, N type or semi-insulating type.

3. The photonic integrated chip structure according to claim 1, characterized in that: The top isolation region is formed by an etching process or a doping process; The width of the top isolation region is greater than the width of the light transmission region; A distance between a left edge of the top isolation region and a left edge of the light transmission region, and a distance between a right edge of the top isolation region and a right edge of the light transmission region are both greater than or equal to 1 um.

4. The photonic integrated chip structure according to claim 1, characterized in that: The bottom isolation region is a P-type doped or N-type doped semiconductor layer.

5. The photonic integrated chip structure according to claim 1, characterized in that: The thickness of the bottom conductive region is greater than or equal to 500 nm; The thickness difference between the bottom isolation region and the bottom conductive region does not exceed 300 nm.

6. The photonic integrated chip structure according to claim 1, characterized in that: The material of the light transmission region is a multi-component semiconductor compound.

7. A method for manufacturing a photonic integrated chip structure according to any one of claims 1 to 6, characterized in that: The method comprises: forming a buffer layer on a substrate; forming a bottom isolation region on the buffer layer, and forming a bottom conductive region on both sides of the bottom isolation region; forming a corresponding core region on the bottom conductive region, and forming a light transmission region between two adjacent core regions; A corresponding top conductive region is formed on the core region, and a top isolation region is formed between two adjacent top conductive regions.

8. The method according to claim 7, characterized in that A bottom isolation region is formed on the buffer layer, and a bottom conductive region is formed on both sides of the bottom isolation region, specifically comprising: forming a bottom isolation layer on the buffer layer, and performing an etching process on the bottom isolation layer to obtain a bottom isolation region; A bottom conductive region is epitaxially grown on the buffer layer in regions located on both sides of the bottom isolation region.

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