Storage of bounding boxes at each level of the bottom layer

Abstract

Various aspects presented herein relate to methods and apparatus for graphics processing, including devices, such as GPUs. The device may configure a BVH structure comprising a plurality of levels and a plurality of nodes, the BVH structure being associated with geometric data for a plurality of primitives in a scene. The device may also identify an amount of storage in a GMEM that can be used to store at least some of the plurality of nodes in the BVH structure. In addition, the device may allocate the BVH structure into a first BVH segment comprising a plurality of first nodes and a second BVH segment comprising a plurality of second nodes. The device may also store first data associated with the plurality of first nodes in the GMEM, and store second data associated with the plurality of first nodes and the plurality of second nodes in system memory.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. patent application serial number 17 / 650,064, filed on February 4, 2022, entitled “STORAGE OF LEVELS FOR BOTTOM LEVELBOUNDING VOLUME HIERARCHY,” which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for graphics processing. Background Art

[0004] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, and each application may need to utilize the GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values ​​and can issue commands to the display panel to display visual content. Devices that provide content for visual presentation on a display may utilize a GPU and / or a display processor.

[0005] Currently, there is a need for improvements in graphics processing. For example, current node storage techniques in graphics processing may not be able to efficiently store acceleration structures. Therefore, there is an increasing need for improved node storage techniques to efficiently store acceleration structures. Summary of the Invention

[0006] The following presents a summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects and is neither intended to identify key or critical elements of all aspects nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that is presented later.

[0007] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device can be a graphics processing unit (GPU), a GPU, or any device that can perform graphics processing. The device can configure a hierarchical bounding box (BVH) structure, the BVH structure including multiple levels and multiple nodes, each level in the multiple levels including at least one node from the multiple nodes, the BVH structure being associated with geometric data of multiple primitives in a scene. The device can also identify a storage amount in a graphics memory (GMEM) that can be used to store at least some of the multiple nodes in the BVH structure. In addition, the device can allocate the BVH structure to a first BVH segment including multiple first nodes and a second BVH segment including multiple second nodes based on the storage amount in the GMEM, the BVH structure being allocated based on a hierarchy of multiple nodes including the multiple first nodes and the multiple second nodes. The device can also store first data associated with the multiple first nodes in the GMEM, and store second data associated with the multiple first nodes and the multiple second nodes in a system memory. The device may also calculate at least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address. In addition, the device may retrieve at least one of the first data from the GMEM or the second data from the system memory when storing the first data and the second data. The device may also perform at least one of ray-triangle intersection for a plurality of interior nodes in the plurality of nodes or ray-box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data.

[0008] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram illustrating an example content generation system in accordance with one or more techniques of this disclosure.

[0010] Figure 2 is an example graphics processing unit (GPU) in accordance with one or more techniques of this disclosure.

[0011] Figure 3 is a diagram illustrating an example ray tracing process in accordance with one or more techniques of this disclosure.

[0012] Figure 4A is a diagram illustrating an example rasterization process in accordance with one or more techniques of this disclosure.

[0013] Figure 4B is a diagram illustrating an example ray tracing process in accordance with one or more techniques of this disclosure.

[0014] Figure 5 is a diagram illustrating an example ray tracing process in accordance with one or more techniques of this disclosure.

[0015] Figure 6A is a diagram illustrating an example data structure in accordance with one or more techniques of this disclosure.

[0016] Figure 6B is a diagram illustrating an example data structure in accordance with one or more techniques of this disclosure.

[0017] Figure 7 is a diagram illustrating an example node storage structure in accordance with one or more techniques of this disclosure.

[0018] Figure 8A is a diagram illustrating an example node storage structure in accordance with one or more techniques of this disclosure.

[0019] Figure 8B is a diagram illustrating an example node storage structure in accordance with one or more techniques of this disclosure.

[0020] Figure 8C is a diagram illustrating an example node storage structure in accordance with one or more techniques of this disclosure.

[0021] Figure 9 is a diagram illustrating an example node storage call flow in accordance with one or more techniques of this disclosure.

[0022] Figure 10 is a diagram illustrating an example node storage call flow in accordance with one or more techniques of this disclosure.

[0023] Figure 11 is a communication flow diagram illustrating example communications between GPU components in accordance with one or more techniques of this disclosure.

[0024] Figure 12 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure.

[0025] Figure 13 is a flowchart of an example method of graphics processing in accordance with one or more techniques of this disclosure. DETAILED DESCRIPTION

[0026] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Based on the teachings of this article, those skilled in the art should understand that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such devices or methods implemented using other structures, functions, or structures and functions in addition to or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0027] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of this disclosure. Although some potential benefits and advantages of various aspects of this disclosure are mentioned, the scope of this disclosure is not intended to be limited to specific benefits, uses, or objectives. On the contrary, various aspects of this disclosure are intended to be broadly applicable to different wireless technologies, system configurations, networks, and transmission protocols, some of which are illustrated by way of example in the drawings and the following description. The detailed description and drawings merely illustrate the disclosure and do not limit it. The scope of this disclosure is defined by the appended claims and their equivalents.

[0028] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0029] For example, an element, or any part of an element, or any combination of elements can be implemented as a "processing system" including one or more processors (which can also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general-purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on a chip (SOCs), baseband processors, application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic components, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system can execute software. Software can be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, processes, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" can refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored on a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access code from a memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in this disclosure. In such examples, a component may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0030] Accordingly, in one or more examples described herein, the functions described can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available medium that can be accessed by a computer. As an example and not limitation, such computer-readable media can include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage, magnetic disk storage, other magnetic storage devices, a combination of the above-mentioned types of computer-readable media, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0031] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphical content and / or reduce the load on a processing unit (i.e., any processing unit configured to perform one or more of the techniques described herein, such as a GPU). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0032] As used herein, instances of the term "content" may refer to "graphics content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphics content" may refer to content generated by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphics content" may refer to content generated by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphics content" may refer to content generated by a graphics processing unit.

[0033] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform compositing on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to composite, blend, or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on a frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form the frame, i.e., the frame includes two or more layers, and the frame including the two or more layers may then be blended.

[0034] Aspects of graphics processing may store ray tracing data in different types of memory (e.g., system memory). However, one potential issue with ray tracing performance is the amount of available memory bandwidth, as accessing data from memory (e.g., system memory) may require a large number of access cycles. In some instances, geometry data may be stored in an acceleration structure (e.g., a bounding volume hierarchy (BVH) structure). For each ray in the ray tracing process, the GPU may need to traverse from a root node (i.e., the top node in the tree structure) to a leaf node. The BVH structure may be associated with a graphics processing scene that includes several primitives. Furthermore, each of these primitives may correspond to one of the nodes in the BVH structure. In some aspects of graphics processing, loading these acceleration structures (e.g., BVH structures) into on-chip graphics memory at the GPU can help achieve faster access to data and ultimately faster ray tracing performance. However, in some instances, the size of the acceleration structure (e.g., BVH structure) may be much larger than the size of the on-chip memory. To overcome this size difference, smaller acceleration structures may be loaded onto on-chip memory in a similar manner to the top-level acceleration structure. In addition, some small low-level acceleration structures (i.e., smaller in size compared to the top-level acceleration structures) may also be placed in on-chip memory. However, due to the organization of the low-level acceleration structures, it may be difficult to access these low-level acceleration structures from the on-chip memory. As such, these low-level acceleration structures may not be accessed frequently enough to meet ray tracing performance specifications. Various aspects of the present disclosure may optimize the storage of acceleration structures (e.g., BVH structures) associated with the ray tracing process. For example, various aspects of the present disclosure may store the low-level acceleration structures in certain types of memory to make these structures easily accessible. To do so, various aspects of the present disclosure may store the low-level BVH structures in on-chip graphics memory (GMEM) and store the low-level BVH structures in system memory (SYSMEM). By doing so, the various aspects presented herein may more easily access the BVH structures from the on-chip graphics memory. In some instances, various aspects of the present disclosure may store different levels of the low-level BVH structures in both on-chip graphics memory and system memory.

[0035] Figure 1is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of this disclosure. Content generation system 100 includes a device 104. Device 104 may include one or more components or circuits for performing the various functions described herein. In some examples, one or more components of device 104 may be components of a system-on-chip (SoC). Device 104 may include one or more components configured to perform one or more techniques of this disclosure. In the example shown, device 104 may include a processing unit 120, a content encoder / decoder 122, and system memory 124. In some aspects, device 104 may include several other components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to displays 131 may refer to one or more displays 131. For example, display 131 may include a single display or multiple displays. Display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first and second displays may receive different frames for presentation. In other examples, the first display and the second display may receive the same frame for rendering thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for rendering thereon. Instead, the frames or graphics processing results may be passed to the other device. In some aspects, this may be referred to as split rendering.

[0036] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head-mounted display, or any other type of display device.

[0037] Memory external to the processing unit 120 and the content encoder / decoder 122, such as system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0038] The content encoder / decoder 122 can be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 can be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 can be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 can be configured to encode or decode any graphics content.

[0039] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memory or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, optical storage media, or any other type of memory.

[0040] According to some examples, internal memory 121 or system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. However, the term "non-transitory" should not be interpreted as meaning that internal memory 121 or system memory 124 is non-removable or that its contents are static. As an example, system memory 124 may be removable from device 104 and moved to another device. As another example, system memory 124 may not be removable from device 104.

[0041] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or any other processing unit that can be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic elements, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute the instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered as one or more processors.

[0042] The content encoder / decoder 122 can be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 can be integrated into the mainboard of the device 104. The content encoder / decoder 122 can include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic components, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 can store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and can use one or more processors to execute the instructions in the hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) can be considered to be one or more processors.

[0043] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein for the device 104. In addition, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any transmitting functions described herein for the device 104. For example, the transmitter 130 may be configured to send information to another device, which information may include a request for content. The receiver 128 and transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or transmitting functions described herein for the device 104.

[0044] Reference again Figure 1 In certain aspects, the processing unit 120 may include a BVH storage structure 198 configured to configure a hierarchical bounding volume (BVH) structure, the BVH structure including a plurality of levels and a plurality of nodes, each level in the plurality of levels including at least one node from the plurality of nodes, the BVH structure being associated with geometric data for a plurality of primitives in a scene. The BVH storage structure 198 may also be configured to identify an amount of memory in graphics memory (GMEM) available for storing at least some of the plurality of nodes in the BVH structure. The BVH storage structure 198 may also be configured to allocate the BVH structure, based on the amount of memory in the GMEM, into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes, the BVH structure being allocated based on a hierarchy of the plurality of nodes including the plurality of first nodes and the plurality of second nodes. The BVH storage structure 198 may also be configured to store first data associated with the plurality of first nodes in the GMEM and store second data associated with the plurality of first nodes and the plurality of second nodes in system memory. The BVH storage structure 198 may also be configured to calculate at least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address. The BVH storage structure 198 may also be configured to retrieve at least one of the first data from the GMEM or the second data from the system memory when storing the first data and the second data. The BVH storage structure 198 may also be configured to perform at least one of ray-triangle intersection for a plurality of interior nodes in the plurality of nodes or ray-box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data. Although the following description may focus on graphics processing, the concepts described herein may be applicable to other similar processing technologies.

[0045] As described herein, a device such as device 104 can refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device can be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, an onboard computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein can be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments can be used to perform.

[0046] The GPU can process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU can process two types of data or data packets, such as context register packets and draw call data. The context register packet can be a set of global state information, such as information about global registers, shader programs, or constant data, which can regulate how the graphics context is processed. For example, the context register packet can include information about the color format. In some aspects of the context register packet, there may be a bit that indicates which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program can describe a certain operation, such as a color mode or color format. Thus, the context register can define multiple states of the GPU.

[0047] Context states can be used to determine how individual processing units (e.g., vertex extractors, vertex shaders (VS), shader processors, or geometry processors) operate and / or in what mode a processing unit operates. To do this, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in the pipeline based on context register definitions of modes or states. Certain processing units (e.g., vertex extractors) can use these states to determine certain functions, such as how vertices are assembled. Because these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state can follow the changed mode or state.

[0048] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a vertex fetcher 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine 226, a rasterizer 228, a Z processing engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering backend (RB) 236, a level 2 (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220-238, but GPU 200 may include several additional processing units. In addition, processing units 220-238 are merely examples, and a GPU according to the present disclosure may use any combination or order of processing units. GPU 200 also includes a command buffer 250, a context register group 260, and a context state 261.

[0049] like Figure 2 As shown, the GPU can utilize a CP (e.g., CP 210) or a hardware accelerator to parse the command buffer into context register packets (e.g., context register packet 260) and / or draw call data packets (e.g., draw call packet 212). CP 210 can then transmit context register packet 260 or draw call packet 212 to a processing unit or block in the GPU via separate paths. Furthermore, command buffer 250 can alternate between different states of context registers and draw calls. For example, the command buffer can be structured as follows: context registers for context N, draw calls for context N, context registers for context N+1, and draw calls for context N+1.

[0050] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or draw calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. In addition, some types of GPUs may allow both tile rendering and direct rendering.

[0051] Some aspects of graphics processing can utilize different types of rendering techniques, such as ray tracing. Ray tracing is a rendering technique for generating images by tracing the light path of pixels in the image plane and simulating the effects of their encounters with objects in the scene. By doing so, ray tracing can produce very realistic lighting effects. Ray tracing has several benefits, including: providing more realistic effects (e.g., reflections), improved global illumination, improved gloss effects, improved depth of field, etc. Ray tracing can also help generate different types of improved shadows, such as hard shadows and / or soft shadows. Some effects of ray tracing can include indirect lighting and the ability to depict caustics (i.e., the patterns of light and color that appear when light reflects or refracts from a surface). As a result, ray tracing can result in the generation of photo-realistic images. Ray tracing can be utilized by several different processors within graphics processing or data processing, such as a graphics processing unit (GPU) or a central processing unit (CPU).

[0052] Figure 3 A diagram 300 is illustrated that includes an example of a ray tracing process. Figure 3 As shown, diagram 300 includes camera 310 , image plane 320 including pixels 322 , scene objects 330 , light sources 340 , view rays 350 , and shadow rays 352 . Figure 3 View rays 350 are shown being traced from camera 310 and through image plane 320. After passing through image plane 320, view rays 350 are traced to scene objects 330. At least some of view rays 350 are traced off scene objects 330 and to light sources 340 as shadow rays 352. Thus, shadow rays 352 and view rays 350 may trace light from light source 340. Figure 3 Depicted is how ray tracing can generate an image by tracing the path of light (eg, from light source 340 ) to pixels in an image plane (eg, pixel 322 in image plane 320 ).

[0053] Ray tracing is distinguishable from several other rendering techniques utilized in graphics processing, such as rasterization. In the rasterization process, for each pixel in each primitive in the scene, the pixel may be shaded if a portion of the pixel is covered by the primitive. In contrast, in the ray tracing process, for each pixel corresponding to a primitive in the scene, a ray is generated. If the generated ray is determined to hit or intersect a primitive, the pixel is shaded. In some instances of graphics processing, ray tracing algorithms may be performed in conjunction with rasterization (such as via a hybrid ray tracing / rasterization model).

[0054] Figure 4A and Figure 4BGraphs 400 and 450 illustrate an example process including rasterization and ray tracing, respectively. Figure 4A As shown, diagram 400 includes scene objects 410 and pixels 420 . Figure 4A It is depicted that for each pixel 420 in a scene including a scene object 410, the rasterization process determines that the pixel is shaded if a portion of the pixel is covered by a primitive. Figure 4B As shown, diagram 450 includes scene objects 460 , pixels 470 , light sources 480 , shadow rays 482 , and primary rays 484 . Figure 4B The process of ray tracing is depicted as determining that a pixel is shaded if a generated ray (eg, shadow ray 482 ) would hit or intersect a primitive in scene object 460 corresponding to one of pixels 470 via primary ray 484 .

[0055] As indicated herein, the process of ray tracing can be performed by determining whether a ray will hit / intersect any primitive(s) in the scene. For example, a ray tracing algorithm can perform a simple query operation: does a given ray hit / intersect any primitive in the scene? The process of ray tracing is computationally intensive because a large number of rays can be traced for a large number of primitives / triangles, which can utilize a large number of ray-triangle intersection tests. For example, in one ray tracing procedure, approximately 1 million rays can be traced for approximately 1 million primitives / triangles, which can utilize approximately 1 trillion ray-triangle intersection tests. In some aspects of the ray tracing procedure, the origin of a given ray can be represented by O(N). In addition, there can be several values ​​calculated for a ray, such as the minimum time (t min ), the maximum time of intersection with the primitives in the scene (t max ) and the calculated distance to the intersection with primitives in the scene.

[0056] Figure 5 A diagram 500 is illustrated that includes an example of a ray tracing process. Figure 5 As shown, diagram 500 includes the origin of the ray (O(N) 510), the minimum time to intersect a primitive in the scene (t min 520), the maximum time of intersection with the primitives in the scene (t max 522 ), a calculated distance (distance 530 ) intersecting with a primitive in the scene, and several primitives in the scene (primitive 540 , primitive 541 , and primitive 542 ). Figure 5 It is shown that ray tracing techniques can use several values ​​to determine whether a ray will hit a primitive. For example, to determine whether a ray will intersect a primitive, the ray tracing technique can use the ray's origin (O(N) 510), the minimum time to intersect the primitive (tmin 520), the maximum time of intersection with the primitive (t max 522 ), a calculated distance (distance 530 ) intersecting with a primitive, and several primitives (primitive 540 , primitive 541 , and primitive 542 ).

[0057] Ray tracing can utilize various data structures to speed up the computation process, such as a bounding box hierarchy (BVH). In a bounding box hierarchy, primitives are stored in leaf nodes. In addition, internal nodes can maintain access to aligned bounding boxes (AABBs) that enclose certain leaf node geometries. The data structures used for ray tracing can also use ray box intersection for internal nodes and / or ray-triangle tests for leaf nodes. These types of data structures can reduce the computational complexity (N) of the ray tracing process, for example, reducing the computational complexity (N) by log(N).

[0058] Figure 6A and 6B Graphs 600 and 650, respectively, illustrate example data structure techniques utilized in ray tracing. Figure 6A As shown, the diagram 600 includes several nodes (internal nodes N 611 -N 617 ) and several primitives (primitive O 621 -O 628 ). Figure 6A Depicts the internal node N 611 -N 617 and element O 621 -O 628 The ray boxes of . Figure 6B As shown, the diagram 650 includes several nodes (N 661 -N 667 ) and several primitives (primitive O 671 -O 678 ). Figure 6B Depicts the leaf node N 661 -N 667 and element O 671 -O 678 The ray-triangle test. Figure 6A and 6B Two data structure techniques in

[15] (e.g., ray-box intersection and ray-triangle testing) are designed to reduce the computational complexity of ray tracing.

[0059] As indicated herein, there are several different stages during the ray tracing process. For example, the stages of ray tracing may include: hierarchy bounding box construction and refinement, ray generation, hierarchy bounding box traversal, ray-triangle intersection, and ray box intersection. There may also be different steps during hierarchy bounding box construction, including partitioning the triangles into clusters, forming a bounding box around each cluster, and recursively partitioning each cluster. Additionally, during hierarchy bounding box construction, there may be several ways of partitioning, which may result in a certain number of possible solutions, for example, 2 n log n As a result, these improved solutions can produce improved ray tracing performance.

[0060] Aspects of ray tracing can also utilize several hierarchical bounding box algorithms, such as segmented hierarchical bounding box (SBVH) and linear hierarchical bounding box (LBVH). In some instances, SBVH may result in slower build times and better quality than LBVH. Similarly, LBVH may result in faster build times and worse quality than SBVH. In addition, some aspects of ray tracing can utilize hierarchical bounding box refinement. In hierarchical bounding box refinement, given a binary BVH with one triangle per leaf, ray tracing techniques can permute the tree topology. Hierarchical bounding box refinement can utilize different algorithms, such as treelet reconstruction BVH (TRBVH) and parallel reinsertion BVH (PRBVH). Some aspects of ray tracing can also utilize BVH widening, which can convert a binary tree (i.e., an initial BVH) into a wide BVH that is wider than the binary tree or the initial BVH. For example, a hierarchy in the initial BVH may include three levels, where primitives are included in the third level of the hierarchy. The hierarchy in a wide BVH may include two levels, with primitives included in the second level of the hierarchy. In some examples of BVH widening, the wide BVH may include interior nodes with a certain number of AABBs (e.g., up to eight AABBs) and leaf nodes with a certain number of primitives / triangles (e.g., up to four primitives / triangles).

[0061] Some aspects of ray tracing can utilize hierarchical bounding box compression. For example, ray tracing techniques can compress wide nodes to accommodate a fixed size (e.g., 64 bytes). BVH compression can include compressing a certain amount of AABBs (e.g., eight AABBs) and / or internal node compression of the first sub-index. BVH compression can also include compressing a certain amount of primitives / triangles (e.g., up to four primitives / triangles) and leaf node compression of the corresponding index. In addition, ray tracing techniques can utilize hierarchical bounding box traversals, such as breadth-first search traversals and / or depth-first search traversals of wide BVHs. Some aspects of ray tracing generation can utilize operations that generate rays in the air. For example, several different types of rays can be generated, such as primary rays, shadow rays, and / or secondary rays.

[0062] In addition, there may be several different ray tracing stages utilized in hardware or software (e.g., GPU / CPU hardware or software). For example, in some stages, the driver may build the BVH on the CPU or GPU (e.g., a BVH construction stage and a BVH node compression stage). In the BVH traversal stage, the BVH traversal may occur in the shader on the GPU. Furthermore, certain stages may be implemented in GPU hardware (e.g., a BVH node decompression stage, a ray-bounding box intersection stage, and a ray-triangle intersection stage).

[0063] Various aspects of graphics processing may store ray tracing data in different types of memory (e.g., system memory). However, one potential issue with ray tracing performance is the amount of available memory bandwidth, as accessing data from memory (e.g., system memory) may require a large number of access cycles. In some instances, geometry data may be stored in an acceleration structure (e.g., a bounding volume hierarchy (BVH) structure). An acceleration structure or BVH structure is a tree structure (e.g., a binary tree structure or an n-ary tree structure) comprising a plurality of nodes, wherein primitive data is stored in leaf nodes (i.e., nodes in the branches of the tree structure). For each ray in the ray tracing process, the GPU may need to traverse from the root node (i.e., the top node in the tree structure) to the leaf node. The BVH structure may be associated with a graphics processing scene comprising several primitives. Furthermore, each of these primitives may correspond to one of the nodes in the BVH structure. For example, for some scenes, the BVH structure associated with the scene may hold millions of primitives.

[0064] In some aspects of graphics processing, loading these acceleration structures (e.g., BVH structures) into on-chip graphics memory at the GPU can help achieve faster access to data and ultimately faster ray tracing performance. However, in some instances, the size of the acceleration structure (e.g., BVH structure) can be much larger than the size of the on-chip memory. To overcome this size difference, smaller acceleration structures can be loaded onto on-chip memory in a similar manner to the top-level acceleration structure. In addition, some small low-level acceleration structures (i.e., smaller in size compared to the top-level acceleration structure) can also be placed in on-chip memory. However, due to the organization of these types of low-level acceleration structures, accessing these types of low-level acceleration structures from on-chip memory may not be beneficial. As such, these low-level acceleration structures may not be accessed frequently enough to meet ray tracing performance specifications. Based on the above, it may be beneficial to optimize the storage of acceleration structures (e.g., BVH structures) associated with the ray tracing process. It may also be beneficial to store the low-level acceleration structures in certain types of memory (e.g., on-chip graphics memory) that are easily accessible.

[0065] Aspects of the present disclosure may optimize the storage of acceleration structures (e.g., BVH structures) associated with the ray tracing process. For example, aspects of the present disclosure may store the underlying acceleration structures in certain types of memory to make them easily accessible. To do so, aspects of the present disclosure may store the underlying BVH structures in on-chip graphics memory (GMEM) and store the underlying BVH structures in system memory (SYSMEM). By doing so, the aspects presented herein may more easily access the BVH structures from the on-chip graphics memory. In some instances, aspects of the present disclosure may store different levels of the underlying BVH structures in both on-chip graphics memory and system memory.

[0066] In some instances of node storage including a BVH structure, internal nodes at higher levels may be accessed more frequently than nodes at lower levels. Therefore, if these higher-level nodes of the underlying acceleration structure (e.g., a BVH structure that does not include a root node) are stored on-chip graphics memory, this may help improve ray tracing performance. For example, the higher-level nodes may be the first or second level in the underlying acceleration structure. Various aspects presented herein may store the top level of the underlying acceleration structure (e.g., a BVH structure that does not include a root node) in on-chip memory or graphics memory (GMEM). These top levels of the underlying acceleration structure may be stored based on the availability of on-chip graphics memory or GMEM. The GPU driver may then determine the number of levels of the BVH structure to be loaded into the graphics memory based on the graphics memory availability and the total number of underlying acceleration structures. In some instances, the remaining levels of the BVH structure may be stored in system memory.

[0067] In some aspects, the driver or GPU driver may program the GPU with the number of levels of the BVH structure loaded into graphics memory for each underlying BVH structure. The GPU driver may also determine which levels of the BVH structure to load into system memory. After storing different levels of the BVH structure into graphics memory or system memory, the GPU may attempt to access different individual nodes from graphics memory or system memory. Based on the level of the node in the BVH structure, the GPU may determine whether the node is stored in graphics memory or system memory, and then fetch (i.e., retrieve) the node accordingly.

[0068] Figure 7 Schematic diagram 700 is illustrated that includes an example of a node storage structure (eg, a tree structure). More specifically, diagram 700 includes a BVH structure for storing different nodes of the structure in a graphics memory or a system memory. Figure 7 As shown, diagram 700 includes nodes in a first level of a BVH structure (eg, node N 710 ), nodes in the second level of the BVH structure (e.g., node N 720 and N 721 ), nodes in the third level of the BVH structure (e.g., node N 730 、N 731 、N 732 and N 733 ), nodes in the fourth level of the BVH structure (e.g., node N 740 、N 741 、N 742 and N 743 ) and the nodes in the fifth level of the BVH structure (e.g., node N 750 、N 751 、N 752 and N 753 ). The nodes shown in diagram 700 may be in the bottom layer of the BVH structure. Figure 7 As depicted, the higher level nodes of the BVH structure (e.g., node N 710 、N 720 、N 721 、N 730 、N 731 、N 732 and N 733 ) can be stored in the graphics memory or GMEM. In addition, the lower level nodes of the BVH structure (e.g., node N 740 、N 741 、N 742 、N 743 、N 750 、N 751 、N 752 and N753 ) may be stored in system memory or SYSMEM. In some instances, both the higher level nodes and the lower level nodes of the BVH structure may be stored in system memory. Additionally, in some cases, as described in further detail below, the driver or GPU driver may determine which nodes / levels of the BVH structure are stored in graphics memory or GMEM, and which nodes / levels of the BVH structure are stored in system memory. For example, the driver or GPU driver may search graphics memory or GMEM to identify the nodes / levels of the BVH structure stored therein. Additionally, the driver or GPU driver may search system memory to identify the nodes / levels of the BVH structure stored therein.

[0069] The driver or GPU driver may include several responsibilities for node storage of the BVH structure. For example, the GPU driver may identify which nodes can be stored in graphics memory or system memory. In addition, based on the available on-chip memory and the amount of underlying BVH, the GPU driver may determine the number of nodes / levels to be stored in the on-chip graphics memory (GMEM) for each BVH. The GPU driver may also assign the GMEM base address and the number of levels to be stored in the GMEM. In addition, the GPU driver may update the GMEM base address and the maximum storage level (e.g., the maximum storage level in GMEM) as a hardware descriptor or acceleration structure (AS) descriptor. The AS descriptor is a structure that can be programmed into the GPU hardware with certain information corresponding to the BVH (e.g., system address, GMEM address, number of levels in GMEM, starting level in GMEM, etc.). The GPU driver may also pack / store all nodes until the maximum storage level in contiguous memory is reached.

[0070] The GPU hardware may also include several responsibilities for node storage of the BVH structure. For example, the GPU hardware may identify or track the level of each node stored in the BVH structure. Additionally, based on the level of the node in the BVH structure, the GPU hardware may transmit a fetch request (i.e., a retrieval request) to a memory (e.g., GMEM or SYSMEM) to retrieve the node from the memory. In some instances, the most frequently accessed nodes may be stored in graphics memory rather than system memory because retrieving nodes from graphics memory may be faster than from system memory.

[0071] Figure 8A A diagram 800 is illustrated that includes an example of a node storage structure (eg, a tree structure). For example, the diagram 800 includes a BVH structure for storing different nodes of the structure in a graphics memory or a system memory. Figure 8AAs shown, diagram 800 includes nodes in a first level of a BVH structure (e.g., node 801), nodes in a second level of the BVH structure (e.g., nodes 802 and 803), nodes in a third level of the BVH structure (e.g., nodes 804, 805, 806, and 807), nodes in a fourth level of the BVH structure (e.g., nodes 808, 809, 810, and 811), and nodes in a fifth level of the BVH structure (e.g., nodes 812, 813, 814, and 815). As indicated herein, Figure 8A The nodes shown in diagram 800 may be in the bottom layer of a BVH structure.

[0072] like Figure 8A and 8B As illustrated in FIG, the higher level nodes (e.g., nodes 801, 802, 803, 804, 805, 806, and 807) of the underlying BVH structure may be stored in a graphics memory or GMEM. Figure 8B As shown in diagram 830 , nodes 801 , 802 , 803 , 804 , 805 , 806 , and 807 may be stored in a graph memory 832 . Figure 8B It is also shown that nodes can be stored in graphics memory 832 based on an offset within memory, such as GMEM offset 834. This offset can be a GMEM start offset based on the base address of the GMEM and a start node offset.

[0073] like Figure 8A and 8C As depicted in FIG, the lower level nodes of the BVH structure (e.g., nodes 808, 809, 810, 811, 812, 813, 814, and 815) may be stored in system memory or SYSMEM. For example, Figure 8C As shown in diagram 860 of FIG, nodes 808, 809, 810, 811, 812, 813, 814, and 815 may be stored in system memory 862. Figure 8C As shown, both the higher level nodes and the lower level nodes of the BVH structure can be stored in the system memory. For example, nodes 801, 802, 803, 804, 805, 806, 807, 808, 809, 810, 811, 812, 813, 814, and 815 can be stored in the system memory 862. Figure 8CIt is also shown that nodes can be stored in system memory 862 based on an offset within the memory (e.g., SYSMEM offset 864). The offset can be a SYSMEM start offset based on the base address of SYSMEM and a start node offset. In addition, the driver or GPU driver can determine which nodes / levels of the BVH structure are stored in graphics memory 832 and which nodes / levels of the BVH structure are stored in system memory 862. For example, the driver or GPU driver can search graphics memory 832 to identify the nodes / levels of the BVH structure stored therein. In addition, the driver or GPU driver can search system memory 862 to identify the nodes / levels of the BVH structure stored therein.

[0074] like Figure 8A 、 8B As indicated by 8C , after the nodes are stored in GMEM (e.g., graphics memory 832) or SYSMEM (e.g., system memory 862), the nodes may be extracted or retrieved from GMEM or SYSMEM. In some instances, most of the higher-level nodes (e.g., nodes 801-807) may be stored in graphics memory 832 rather than system memory because the higher-level nodes may be accessed more frequently than the lower-level nodes (e.g., nodes 808-815). In fact, it may be faster to retrieve nodes from graphics memory 832 than from system memory 862, so the more frequently accessed nodes (e.g., higher-level nodes 801-807) may be stored in graphics memory 832. The lower-level nodes (e.g., nodes 808-815) may be stored in system memory 862 because these nodes may be accessed less frequently than the higher-level nodes, and accessing system memory 862 may take longer than graphics memory 832. As Figure 8C As shown, in some instances, both higher-level nodes (eg, nodes 801 - 807 ) and lower-level nodes (eg, nodes 808 - 815 ) may be stored in system memory 862 .

[0075] Aspects presented herein may also include different methods for partitioning / allocating different levels of a BVH structure, such as methods for determining which levels are stored in GMEM and which levels are stored in SYSMEM. For example, aspects of the present disclosure may include an algorithm for partitioning a node storage structure (e.g., a tree structure), such as identifying which levels are stored in GMEM or SYSMEM. In one aspect, the algorithm may partition / allocate the node storage structure to determine the top multiple levels (e.g., n top levels) to be loaded / stored in GMEM. For example, the top / high level may be the top two levels in the node storage structure, so the algorithm may allocate the top two levels to be stored in GMEM. The algorithm may determine that the remaining levels (i.e., the levels not stored in GMEM) will be stored in SYSMEM. In addition, the algorithm may perform a depth-first traversal up to a certain number of levels (e.g., n levels) and place the nodes of these levels in contiguous memory, while adding nodes of another number of levels (e.g., n+1 levels) in a queue or storage. For example, the algorithm can perform a depth-first traversal on the top two levels in the node storage structure and place the top two levels of nodes in contiguous memory while adding another three levels in the queue or storage. The various aspects presented herein can then store the number of nodes packed during the first pass of the algorithm. In addition, the various aspects presented herein can dequeue (i.e., remove) each of the n+1 layer nodes and perform a depth-first traversal on each of these dequeued nodes. After doing so, these dequeued nodes can be placed in contiguous memory. In some cases, top-level nodes can receive improved cache hits compared to lower-level nodes, and in this case, it may be advantageous to also load / store middle-level nodes.

[0076] In addition, the various aspects presented herein may include an algorithm for partitioning a BVH structure so as to store a range of node levels (e.g., from level m to level n of the BVH structure) in GMEM. The various aspects presented herein may perform a depth-first traversal up to a first number of levels (e.g., m levels) and place these levels in contiguous memory. At the same time, a second number of node levels (e.g., m+1 levels) may be added to a queue. In addition, the various aspects presented herein may store the number of nodes packed during the first pass of the algorithm. The various aspects presented herein may also dequeue each of the second number of node levels (e.g., m+1 levels) from the queue and perform a depth-first traversal on each of these dequeued nodes until a certain number of levels (e.g., n levels) is reached and the levels are placed in contiguous memory. At the same time, the various aspects presented herein may place multiple node levels (e.g., n+1 levels) in the queue. The various aspects of the present disclosure may also store the number of nodes packed during the second pass of the algorithm. In addition, each of the n+1 level nodes can be dequeued from the queue, and a depth-first traversal can then be performed on each dequeued node. The dequeued nodes can be placed in a continuous memory while the n+1 level nodes are placed in the queue.

[0077] In some aspects, the driver or GPU driver can determine the number of levels of each BVH structure to be loaded / stored in memory (e.g., GMEM or SYSMEM). For example, the GPU driver can determine the number of levels based on heuristics and / or storage availability in GMEM. During the ray tracing process, the GPU driver can load specified levels of the BVH structure into GMEM. These specified levels of the BVH structure can be loaded dynamically, and the hardware descriptors can be programmed accordingly. During the construction of the top-level acceleration structure, the driver can determine or ultimately determine which BVH structure is partially loaded into GMEM, fully loaded into GMEM, or skipped entirely. This determination can be based on heuristics and / or storage availability in GMEM.

[0078] In addition, the GPU driver can use certain information to program the GPU hardware for each acceleration structure (AS) descriptor or hardware descriptor. For example, the GPU driver can program the GPU hardware with a GMEM start offset value (i.e., an offset from the GMEM base address). For example, the GMEM start offset value can be an offset of two or three addresses from the GMEM base address. The GPU driver can also program the GPU hardware with a start node offset (i.e., an offset from the start node). In addition, the GPU driver can use the BVH start level in GMEM (i.e., the start level of the BVH from which nodes exist in GMEM). In addition, the GPU driver can use the BVH end level in GMEM (i.e., the end point of the last level of the BVH in GMEM) to program the GPU hardware. The GPU driver can also program the GPU hardware with a system memory address.

[0079] Figure 9 900 is illustrated including an example of a call flow for a node storage procedure. More specifically, the diagram 900 includes a call flow for a driver or GPU driver to store a high node level of a BVH structure in graphics memory and / or system memory. Figure 9 As shown, diagram 900 includes several steps of a node storage call flow (e.g., steps 910, 920, 930, 940, 950, 960, and 970). At step 910, the application may transmit a request to the driver to create or construct a BVH structure for a certain geometry in the scene (e.g., a geometry provided to the driver by the application). At step 920, the driver may determine the number of levels to be placed in GMEM based on the available GMEM size and the number of BVHs in the scene. At step 930, the driver may construct the BVH using the constraint that the BVH nodes placed in GMEM are placed in contiguous memory locations. At step 940, the driver may allocate a portion of GMEM to the BVH structure and determine the offset and size. The driver may also add information / details to the BVH descriptor, such as the GMEM start offset, the start node offset, the BVH start level in GMEM, and the BVH end level in GMEM. At step 950, before starting ray tracing on the BVH, the driver may load data from contiguous memory (corresponding to the start and end levels) into GMEM at a predetermined GMEM start offset. At step 960, the driver may program the GPU with a BVH descriptor containing the GMEM address, the SYSMEM address, and the GMEM start and end level information. At step 970, the driver may start ray tracing on the GPU by scheduling rays traversing the BVH structure.

[0080] Figure 101000 illustrates an example of a call flow for a node storage procedure. More specifically, diagram 1000 includes a call flow for a GPU or GPU hardware to store a high node level of a BVH structure in graphics memory and / or system memory. Figure 10 As shown, diagram 1000 includes several steps (e.g., steps 1010, 1020, 1030, 1040, 1050, 1060, and 1070) of a node storage call flow. At step 1010, the GPU may trace a specific ray associated with a ray tracing process. At step 1020, the GPU may extract (i.e., retrieve) a BVH node corresponding to a level ID and / or a node ID. At step 1030, the GPU may determine whether the level ID is between the GMEM start level and the GMEM end level. If the level ID is between the GMEM start level and the GMEM end level, then at step 1040, the GPU may extract data associated with the node from GMEM. To extract the data, at step 1050, the GPU may calculate a node address based on the node ID and the GMEM offset. For example, the node address may be calculated based on the node ID present in the parent node (i.e., the parent node holds the child node ID). After doing so, the GPU may issue a fetch for the data associated with the node. If the level ID is not between the GMEM start level and the GMEM end level, then at step 1042, the GPU may extract the data associated with the node from SYSMEM. To extract the data, at step 1052, the GPU may calculate the node address based on the node ID and the SYSMEM base address. After doing so, the GPU may issue a fetch for the data associated with the node. At step 1060, the GPU may determine whether the node is an internal node. If the node is an internal node, then at step 1070, the GPU may perform a ray-box intersection. If the node is not an internal node, then at step 1072, the GPU may perform a ray-triangle intersection.

[0081] Figure 10 Describes the details of the node storage call flow at the GPU or GPU hardware. Figure 10 As shown, the GPU can implement level IDs in the GPU. The level ID can be initialized to a certain value (e.g., a value of 0) at the root node, and then incremented (e.g., incremented by 1) when accessing a child node of the current level node. Thus, the GPU can maintain the level ID of a node while traversing the BVH structure.

[0082] Various aspects of the present disclosure may include several benefits or advantages. For example, various aspects of the present disclosure may optimize the storage of acceleration structures (e.g., BVH structures) associated with the ray tracing process. To optimize the storage process, various aspects of the present disclosure may store certain nodes in the underlying acceleration structure in certain types of memory (e.g., GMEM) to make these nodes easier to access. By doing so, the various aspects presented herein may more easily access the BVH structure from on-chip graphics memory, which may in turn optimize or improve ray tracing performance.

[0083] Figure 11 FIG1 is a communication flow diagram 1100 of a graphical process according to one or more techniques of this disclosure. Figure 11 As shown, diagram 1100 includes example communications between components of a GPU (or other graphics processor), such as GPU component 1102 , GPU component 1104 , and memory 1106 (eg, GMEM or SYSMEM), according to one or more techniques of this disclosure.

[0084] At 1110, GPU component 1102 may obtain a bounding volume hierarchy (BVH) structure comprising a plurality of levels and a plurality of nodes, each level in the plurality of levels comprising at least one node from the plurality of nodes, the BVH structure being associated with geometric data for a plurality of primitives in a scene (e.g., primitive 1112). The primitives in the scene (e.g., primitive 1112) may be received from another component or portion of a GPU (e.g., GPU component 1104). The plurality of nodes may include a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes may be associated with a plurality of bounding boxes for the plurality of primitives, and wherein the plurality of leaf nodes may be associated with geometric data for the plurality of primitives. The BVH structure may be a data structure associated with a ray tracing process for the plurality of primitives in the scene, and the ray tracing process may include a plurality of rays associated with the geometric data for the plurality of primitives.

[0085] At 1120 , the GPU component 1102 can identify an amount of memory in the first memory that can be used to store at least some of the plurality of nodes in the BVH structure.

[0086] At 1130, GPU component 1102 may allocate the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on an amount of storage in the first memory, the BVH structure being allocated based on a hierarchy of a plurality of nodes including the plurality of first nodes and the plurality of second nodes. The plurality of first nodes may be associated with a first number of rays in a ray tracing process for a plurality of primitives in a scene, and the plurality of second nodes may be associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays. The hierarchy of the plurality of nodes may be associated with a node identifier (ID) of each of the plurality of nodes in the BVH structure and a level ID of each of a plurality of levels, wherein the plurality of first nodes may correspond to a first segment of the plurality of levels, and the plurality of second nodes may correspond to a second segment of the plurality of levels. The BVH structure may be allocated based on the first segment of the plurality of levels and the second segment of the plurality of levels, and each level in the plurality of levels may include a different level ID than other levels in the plurality of levels. In addition, the plurality of first nodes may correspond to high-level nodes in the BVH structure, and the plurality of second nodes may correspond to low-level nodes in the BVH structure. The high-level node may include a root node in the BVH structure, and the low-level node may include a plurality of leaf nodes.

[0087] At 1140, GPU component 1102 may store first data associated with the plurality of first nodes (e.g., data 1142) in a first memory. In some aspects, GPU component 1102 may also store second data associated with the plurality of first nodes and the plurality of second nodes (e.g., data 1142) in a second memory at 1140. The first data associated with the plurality of first nodes may be equal to the amount of memory identified in the first memory.

[0088] At 1150, the GPU component 1102 may calculate at least one of a first address of the plurality of first nodes or a second address of the plurality of second nodes before retrieving at least one of the first data or the second data. The first addresses of the plurality of first nodes may be calculated based on an offset value of the first memory and a node identifier (ID) of each first node in the plurality of first nodes, and the second addresses of the plurality of second nodes may be calculated based on a base address of the second memory and a node ID of each second node in the plurality of second nodes.

[0089] At 1160, GPU component 1102 may retrieve at least one of the first data from the first memory or the second data (e.g., data 1142) from the second memory after storing the first data and the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address. At least one of the first data or the second data may be retrieved based on a node identifier (ID) of each of a plurality of nodes in a BVH structure or a level ID of each of a plurality of levels. Furthermore, at least one of the first data or the second data may be retrieved based on a hierarchy of the plurality of first nodes. The first memory may be graphics memory, and the second memory may be system memory. Furthermore, GPU component 1102 may perform extraction of at least one of the first data from the first memory or the second data from the second memory. For example, retrieving at least one of the first data or the second data may include extracting the first data from the first memory or extracting at least one of the second data from the second memory.

[0090] At 1170 , the GPU component 1102 may perform at least one of a ray-triangle intersection for a plurality of interior nodes in the plurality of nodes or a ray-box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data.

[0091] Figure 12 1200 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method may be performed by a GPU (such as a device for graphics processing), a graphics processor, a CPU, a wireless communication device, and / or a combination thereof. Figure 1-11 The examples are performed using any device that can perform graphics processing. The methods described herein may provide several benefits, such as improved resource utilization and / or power savings.

[0092] At 1202, the GPU may obtain a BVH structure, the BVH structure including a plurality of levels and a plurality of nodes, each level in the plurality of levels including at least one node in the plurality of nodes, the BVH structure being associated with geometric data of a plurality of primitives in a scene, such as in combination with Figure 1-11 For example, as described in Figure 11 As described in step 1110, the GPU component 1102 may obtain a BVH structure, the BVH structure including multiple levels and multiple nodes, each level in the multiple levels including at least one node in the multiple nodes, and the BVH structure being associated with geometric data of multiple primitives in the scene. Further, step 1202 may be performed by Figure 1The plurality of nodes may include a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes may be associated with a plurality of bounding boxes for a plurality of primitives, and wherein the plurality of leaf nodes may be associated with geometric data for the plurality of primitives. The BVH structure may be a data structure associated with a ray tracing process for a plurality of primitives in a scene, and the ray tracing process may include a plurality of rays associated with the geometric data for the plurality of primitives.

[0093] At 1204, the GPU may identify an amount of memory in the first memory that can be used to store at least some of the plurality of nodes in the BVH structure, such as in conjunction with Figure 1-11 For example, as described in Figure 11 As described in step 1120, the GPU component 1102 may identify the amount of storage in the first memory that can be used to store at least some of the multiple nodes in the BVH structure. Further, step 1204 may be performed by Figure 1 The processing unit 120 in the processor is used to execute the above operations.

[0094] At 1206, the GPU may allocate the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the amount of storage in the first memory, the BVH structure being allocated based on a hierarchy of a plurality of nodes including the plurality of first nodes and the plurality of second nodes, as combined with Figure 1-11 For example, as described in Figure 11 As described in step 1130, the GPU component 1102 may allocate the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the amount of storage in the first memory, wherein the BVH structure is allocated based on a hierarchy of a plurality of nodes including the plurality of first nodes and the plurality of second nodes. Further, step 1206 may be performed by Figure 1The processing unit 120 in the embodiment of the present invention is executed. The plurality of first nodes may be associated with a first number of rays in a ray tracing process for a plurality of primitives in a scene, and the plurality of second nodes may be associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays. The hierarchy of the plurality of nodes may be associated with a node identifier (ID) of each of the plurality of nodes in the BVH structure and a level ID of each of a plurality of levels, wherein the plurality of first nodes may correspond to a first segment of the plurality of levels, and the plurality of second nodes may correspond to a second segment of the plurality of levels. The BVH structure may be allocated based on the first segment of the plurality of levels and the second segment of the plurality of levels, and each level in the plurality of levels may include a different level ID than other levels in the plurality of levels. In addition, the plurality of first nodes may correspond to high-level nodes in the BVH structure, and the plurality of second nodes may correspond to low-level nodes in the BVH structure. The high-level node may include a root node in the BVH structure, and the low-level node may include a plurality of leaf nodes.

[0095] At 1208, the GPU may store first data associated with the plurality of first nodes in a first memory, such as in conjunction with Figure 1-11 In some aspects, at 1208, the GPU component may further store second data associated with the plurality of first nodes and the plurality of second nodes in a second memory. For example, Figure 11 As described in step 1140, the GPU component 1102 may store the first data associated with the plurality of first nodes in a first memory, and store the second data associated with the plurality of first nodes and the plurality of second nodes in a second memory. Further, step 1208 may be performed by Figure 1 The first data associated with the plurality of first nodes may be equal to the storage amount identified in the first memory.

[0096] Figure 13 1300 is a flowchart of an example method of graphics processing according to one or more techniques of the present disclosure. The method may be performed by a GPU (such as a device for graphics processing), a graphics processor, a CPU, a wireless communication device, and / or a combination thereof. Figure 1-11 The examples are performed using any device that can perform graphics processing. The methods described herein may provide several benefits, such as improved resource utilization and / or power savings.

[0097] At 1302, the GPU may obtain a BVH structure, the BVH structure including a plurality of levels and a plurality of nodes, each level in the plurality of levels including at least one node in the plurality of nodes, the BVH structure being associated with geometric data of a plurality of primitives in a scene, such as in combination with Figures 1 to 11For example, as described in Figure 11 As described in step 1110, the GPU component 1102 may obtain a BVH structure, the BVH structure including multiple levels and multiple nodes, each level in the multiple levels including at least one node in the multiple nodes, and the BVH structure being associated with geometric data of multiple primitives in the scene. Further, step 1302 may be performed by Figure 1 The plurality of nodes may include a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes may be associated with a plurality of bounding boxes for a plurality of primitives, and wherein the plurality of leaf nodes may be associated with geometric data for the plurality of primitives. The BVH structure may be a data structure associated with a ray tracing process for a plurality of primitives in a scene, and the ray tracing process may include a plurality of rays associated with the geometric data for the plurality of primitives.

[0098] At 1304, the GPU may identify an amount of memory in the first memory that can be used to store at least some of the plurality of nodes in the BVH structure, such as in conjunction with Figures 1 to 11 For example, as described in Figure 11 As described in step 1120, the GPU component 1102 may identify the amount of storage in the first memory that can be used to store at least some of the multiple nodes in the BVH structure. Further, step 1304 may be performed by Figure 1 The processing unit 120 in the processor is used to execute the above operations.

[0099] At 1306, the GPU may allocate the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the amount of storage in the first memory, the BVH structure being allocated based on a hierarchy of a plurality of nodes including the plurality of first nodes and the plurality of second nodes, as combined with Figures 1 to 11 For example, as described in Figure 11 As described in step 1130, the GPU component 1102 may allocate the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the amount of storage in the first memory, wherein the BVH structure is allocated based on a hierarchy of a plurality of nodes including the plurality of first nodes and the plurality of second nodes. Further, step 1306 may be performed by Figure 1The processing unit 120 in the embodiment of the present invention is executed. The plurality of first nodes may be associated with a first number of rays in a ray tracing process for a plurality of primitives in a scene, and the plurality of second nodes may be associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays. The hierarchy of the plurality of nodes may be associated with a node identifier (ID) of each of the plurality of nodes in the BVH structure and a level ID of each of a plurality of levels, wherein the plurality of first nodes may correspond to a first segment of the plurality of levels, and the plurality of second nodes may correspond to a second segment of the plurality of levels. The BVH structure may be allocated based on the first segment of the plurality of levels and the second segment of the plurality of levels, and each level in the plurality of levels may include a different level ID than other levels in the plurality of levels. In addition, the plurality of first nodes may correspond to high-level nodes in the BVH structure, and the plurality of second nodes may correspond to low-level nodes in the BVH structure. The high-level node may include a root node in the BVH structure, and the low-level node may include a plurality of leaf nodes.

[0100] At 1308, the GPU may store first data associated with the plurality of first nodes in a first memory, such as in conjunction with Figures 1 to 11 In some aspects, at 1308, the GPU component may further store second data associated with the plurality of first nodes and the plurality of second nodes in a second memory. For example, Figure 11 As described in step 1140, the GPU component 1102 may store the first data associated with the plurality of first nodes in a first memory, and store the second data associated with the plurality of first nodes and the plurality of second nodes in a second memory. Further, step 1308 may be performed by Figure 1 The first data associated with the plurality of first nodes may be equal to the storage amount identified in the first memory.

[0101] At 1310, the GPU may calculate at least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes before retrieving at least one of the first data or the second data, such as in conjunction with Figure 1-11 For example, as described in the example Figure 11 As described in step 1150, the GPU component 1102 may calculate at least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes before retrieving at least one of the first data or the second data. Further, step 1310 may be performed by Figure 1The first addresses of the plurality of first nodes may be calculated based on an offset value of the first memory and a node identifier (ID) of each of the plurality of first nodes, and the second addresses of the plurality of second nodes may be calculated based on a base address of the second memory and a node ID of each of the plurality of second nodes.

[0102] At 1312, the GPU may perform at least one of retrieving the first data from the first memory or retrieving the second data from the second memory after storing the first data and the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address, as described in conjunction with Figure 1-11 For example, as described in the example Figure 11 As described in 1160, the GPU component 1102 may retrieve at least one of the first data from the first memory or the second data from the second memory when storing the first data and the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address. Further, step 1312 may be performed by Figure 1 The processing unit 120 in the BVH structure may be executed. At least one of the first data or the second data may be retrieved based on a node identifier (ID) of each of a plurality of nodes in the BVH structure or a level ID of each of a plurality of levels. In addition, at least one of the first data or the second data may be retrieved based on a hierarchy of the plurality of first nodes. The first memory may be a graphics memory (e.g., GMEM), and the second memory may be a system memory. In addition, the GPU may perform extraction of the first data from the first memory or extraction of at least one of the second data from the second memory. For example, retrieving at least one of the first data or the second data may include extracting the first data from the first memory or extracting at least one of the second data from the second memory.

[0103] At 1314, the GPU may perform at least one of ray-triangle intersection for a plurality of interior nodes in the plurality of nodes or ray-box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data, as in combination with Figure 1-11 For example, as described in the example Figure 11 As described in step 1170, the GPU component 1102 may perform at least one of ray triangle intersection for a plurality of internal nodes in the plurality of nodes or ray box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data. Further, step 1314 may be performed by Figure 1 The processing unit 120 in the processor is used to execute the above operations.

[0104] In a configuration, a method or apparatus for graphics processing is provided. The apparatus may be a GPU, a graphics processor, or some other processor capable of performing graphics processing. In various aspects, the apparatus may be a processing unit 120 within a device 104, or may be some other hardware within the device 104 or another device. The apparatus (e.g., processing unit 120) may include means for configuring a hierarchical bounding volume (BVH) structure, the BVH structure comprising a plurality of levels and a plurality of nodes, each level of the plurality of levels comprising at least one of the plurality of nodes, the BVH structure being associated with geometric data for a plurality of primitives in a scene. The apparatus (e.g., processing unit 120) may also include means for identifying a memory capacity in a first memory that can be used to store at least some of the plurality of nodes in the BVH structure. The apparatus (e.g., processing unit 120) may also include means for allocating the BVH structure, based on the memory capacity in the first memory, into a first BVH segment comprising a plurality of first nodes and a second BVH segment comprising a plurality of second nodes, the BVH structure being allocated based on a hierarchy of the plurality of nodes comprising the plurality of first nodes and the plurality of second nodes. The device (e.g., processing unit 120) may further include means for storing first data associated with the plurality of first nodes in a first memory, and second data associated with the plurality of first nodes and the plurality of second nodes in a second memory. The device (e.g., processing unit 120) may further include means for retrieving at least one of the first data from the first memory or the second data from the second memory when storing the first data and the second data. The device (e.g., processing unit 120) may further include means for calculating at least one of first addresses of the plurality of first nodes or second addresses of the plurality of second nodes before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address. The device (e.g., processing unit 120) may further include means for performing at least one of ray-triangle intersection for a plurality of interior nodes in the plurality of nodes or ray-box intersection for a plurality of leaf nodes in the plurality of nodes based on at least one of the first data or the second data.

[0105] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the described graphics processing techniques can be used by a GPU, a graphics processor, or some other processor that can perform graphics processing to implement the node storage techniques described herein. This can also be implemented at a low cost compared to other graphics processing techniques. In addition, the graphics processing techniques herein can improve or accelerate data processing or execution. In addition, the graphics processing techniques herein can improve resource or data utilization and / or resource efficiency. In addition, various aspects of the present disclosure can utilize node storage techniques to improve memory bandwidth efficiency and / or increase processing speed at the GPU.

[0106] It should be understood that the specific order or hierarchy of blocks in the disclosed process / flowchart is merely illustrative of an exemplary method. It should be understood that the specific order or hierarchy of blocks in the process / flowchart may be rearranged based on design preferences. In addition, some blocks may be combined or omitted. The accompanying method claims provide elements of each block in a sample order, but are not intended to be limited to the specific order or hierarchy provided.

[0107] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein, unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "serving as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be construed as being preferred or having advantages over other aspects.

[0108] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” unless the context dictates otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C and may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A, B, and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents to the elements of the various aspects described in this disclosure that are known or later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be disclosed to the public, regardless of whether such disclosure is explicitly recited in the claims. Words such as "module," "mechanism," "element," and "device" are not intended to be substituted for the word "component." Therefore, no claim element will be construed as a component-plus-function unless the element is explicitly stated using the phrase "component for..."

[0109] In one or more examples, the functionality described herein can be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit can be implemented in hardware, software, firmware, or any combination thereof. If any functionality, processing unit, technique, or other module described herein is implemented in software, the functionality, processing unit, technique, or other module described herein can be stored or transmitted as one or more instructions or codes on a computer-readable medium.

[0110] According to the present disclosure, the term "or" can be understood as "and / or" unless the context dictates otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used with some features disclosed herein and not with others, features that do not use such language can be understood to have such implicit meanings unless the context dictates otherwise.

[0111] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of a computer program from one place to another. In this manner, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described herein. By way of example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage, or other magnetic storage devices. Disk and disc, as used herein, include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc. Disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0112] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Thus, the term "processor" as used herein may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. Additionally, these techniques may be fully implemented in one or more circuits or logic elements.

[0113] The techniques of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless handsets, integrated circuits (ICs) or groups of ICs (e.g., chipsets). Various components, modules or units are described in this disclosure to emphasize the functional aspects of devices configured to perform the disclosed techniques, but do not necessarily need to be implemented by different hardware units. Specifically, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the techniques described herein. Similarly, these techniques can be fully implemented in one or more circuits or logic elements.

[0114] The following aspects are merely illustrative and may be combined without limitation with other aspects or teachings described herein.

[0115] Aspect 1 is a device for graphics processing, the device comprising at least one processor, the at least one processor being coupled to a memory and being configured to: obtain a hierarchical bounding box (BVH) structure, the hierarchical bounding box (BVH) structure comprising multiple levels and multiple nodes, each level in the multiple levels comprising at least one node in the multiple nodes, the BVH structure being associated with geometric data of multiple primitives in a scene; identify a storage amount in a first memory that can be used to store at least some of the multiple nodes in the BVH structure; allocate the BVH structure to a first BVH segment comprising multiple first nodes and a second BVH segment comprising multiple second nodes based on the storage amount in the first memory, the BVH structure being allocated based on a hierarchy of the multiple nodes comprising the multiple first nodes and the multiple second nodes; and store first data associated with the multiple first nodes in the first memory.

[0116] Aspect 2 is a device according to aspect 1, wherein the at least one processor is further configured to: store second data associated with the multiple first nodes and the multiple second nodes in a second memory; and after storing the first data and the second data, perform at least one of retrieving the first data from the first memory or retrieving the second data from the second memory.

[0117] Aspect 3 is an apparatus according to any one of Aspects 1 or 2, wherein the at least one processor is further configured to: calculate at least one of the first addresses of the multiple first nodes or the second addresses of the multiple second nodes before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address.

[0118] Aspect 4 is an apparatus according to any one of Aspects 1 to 3, wherein the first addresses of the multiple first nodes are calculated based on an offset value of a first memory and a node identifier (ID) of each first node in the multiple first nodes, and wherein the second addresses of the multiple second nodes are calculated based on a base address of the second memory and a node ID of each second node in the multiple second nodes.

[0119] Aspect 5 is an apparatus according to any one of aspects 1 to 4, wherein the at least one processor is further configured to: perform at least one of ray triangle intersection for multiple internal nodes among the multiple nodes or ray box intersection for multiple leaf nodes among the multiple nodes based on at least one of the first data or the second data.

[0120] Aspect 6 is a device according to any one of aspects 1 to 5, wherein at least one of the first data or the second data is retrieved based on a node identifier (ID) of each of a plurality of nodes in the BVH structure or a level ID of each of a plurality of levels.

[0121] Aspect 7 is an apparatus according to any one of aspects 1 to 6, wherein at least one of the first data or the second data is retrieved based on a hierarchy of the plurality of first nodes, wherein the first memory is a graphics memory, and the second memory is a system memory.

[0122] Aspect 8 is an apparatus according to any one of aspects 1 to 7, wherein in order to retrieve at least one of the first data or the second data, the at least one processor is configured to perform at least one of extracting the first data from the first memory or extracting the second data from the second memory.

[0123] Aspect 9 is an apparatus according to any one of aspects 1 to 8, wherein the plurality of first nodes are associated with a first number of rays in a ray tracing process for a plurality of primitives in a scene, and wherein the plurality of second nodes are associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays.

[0124] Aspect 10 is a device according to any one of aspects 1 to 9, wherein the hierarchy of the multiple nodes is associated with a node identifier (ID) of each of the multiple nodes in the BVH structure and a level ID of each of the multiple levels, wherein the multiple first nodes correspond to first segments of the multiple levels, and the multiple second nodes correspond to second segments of the multiple levels.

[0125] Aspect 11 is a device according to any one of aspects 1 to 10, wherein the BVH structure is allocated based on the first segments of the multiple levels and the second segments of the multiple levels, and wherein each level of the multiple levels includes a different level ID compared to other levels of the multiple levels.

[0126] Aspect 12 is an apparatus according to any one of aspects 1 to 11, wherein the plurality of first nodes correspond to high-level nodes in the BVH structure, and the plurality of second nodes correspond to low-level nodes in the BVH structure.

[0127] Aspect 13 is an apparatus according to any one of aspects 1 to 12, wherein the high-level node comprises a root node in the BVH structure, and the low-level node comprises a plurality of leaf nodes.

[0128] Aspect 14 is an apparatus according to any one of Aspects 1 to 13, wherein the plurality of nodes includes a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes are associated with a plurality of bounding boxes for the plurality of primitives, and wherein the plurality of leaf nodes are associated with the geometric data for the plurality of primitives.

[0129] Aspect 15 is an apparatus according to any one of aspects 1 to 14, wherein the first data associated with the plurality of first nodes is equal to the storage amount identified in the first memory.

[0130] Aspect 16 is an apparatus according to any one of aspects 1 to 15, wherein the apparatus is a wireless communication device, the apparatus further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

[0131] Aspect 17 is a method for implementing the graphics processing according to any one of aspects 1 to 16.

[0132] Aspect 18 is an apparatus for performing graphics processing, the apparatus comprising means for implementing any one of aspects 1 to 16.

[0133] Aspect 19 is a non-transitory computer-readable medium storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 16.

Claims

1. A device for graphics processing, comprising: Memory; as well as at least one processor coupled to the memory and configured to: Obtaining a bounding volume hierarchy (BVH) structure, the BVH structure comprising a plurality of levels and a plurality of nodes, each level in the plurality of levels comprising at least one node in the plurality of nodes, the BVH structure being associated with geometric data of a plurality of primitives in a scene; identifying an amount of memory in a first memory available for storing at least some of the plurality of nodes in the BVH structure; allocating the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the storage amount in the first memory, the BVH structure being allocated based on a hierarchy of the plurality of nodes including the plurality of first nodes and the plurality of second nodes; as well as First data associated with the plurality of first nodes is stored in the first memory.

2. The device according to claim 1, wherein The at least one processor is further configured to: storing second data associated with the plurality of first nodes and the plurality of second nodes in a second memory; as well as After storing the first data and the second data, at least one of retrieving the first data from the first memory or retrieving the second data from the second memory is performed.

3. The device according to claim 2, wherein The at least one processor is further configured to: At least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes is calculated before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address.

4. The device according to claim 3, wherein The first addresses of the multiple first nodes are calculated based on the offset value of the first memory and the node identifier (ID) of each first node in the multiple first nodes, and wherein the second addresses of the multiple second nodes are calculated based on the base address of the second memory and the node ID of each second node in the multiple second nodes.

5. The device according to claim 2, wherein The at least one processor is further configured to: At least one of ray-triangle intersection for a plurality of interior nodes among the plurality of nodes or ray-box intersection for a plurality of leaf nodes among the plurality of nodes is performed based on at least one of the first data or the second data.

6. The device according to claim 2, wherein At least one of the first data or the second data is retrieved based on a node identifier (ID) of each of the plurality of nodes in the BVH structure or a level ID of each of the plurality of levels.

7. The device according to claim 2, wherein At least one of the first data or the second data is retrieved based on the hierarchy of the plurality of first nodes, wherein the first memory is a graphics memory and the second memory is a system memory.

8. The device according to claim 2, wherein To retrieve at least one of the first data or the second data, the at least one processor is configured to perform at least one of extracting the first data from the first memory or extracting the second data from the second memory.

9. The device according to claim 1, wherein The plurality of first nodes are associated with a first number of rays in a ray tracing process for the plurality of primitives in the scene, and wherein the plurality of second nodes are associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays.

10. The device according to claim 1, wherein The hierarchy of the plurality of nodes is associated with a node identifier (ID) of each of the plurality of nodes and a level ID of each of the plurality of levels in the BVH structure, wherein the plurality of first nodes corresponds to a first segment of the plurality of levels and the plurality of second nodes corresponds to a second segment of the plurality of levels.

11. The device according to claim 10, wherein The BVH structure is allocated based on the first sections of the plurality of levels and the second sections of the plurality of levels, and wherein each level of the plurality of levels includes a different level ID compared to other levels of the plurality of levels.

12. The device according to claim 1, wherein The plurality of first nodes correspond to high-level nodes in the BVH structure, and the plurality of second nodes correspond to low-level nodes in the BVH structure.

13. The device according to claim 12, wherein The high-level node includes a root node in the BVH structure, and the low-level node includes a plurality of leaf nodes.

14. The device according to claim 1, wherein The plurality of nodes includes a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes are associated with a plurality of bounding boxes for the plurality of primitives, and wherein the plurality of leaf nodes are associated with the geometric data for the plurality of primitives.

15. The device according to claim 1, wherein The first data associated with the plurality of first nodes is equal to an amount of storage identified in the first memory.

16. The device according to claim 1, wherein The apparatus is a wireless communication device further comprising at least one of an antenna or a transceiver coupled to the at least one processor.

17. A method for graphics processing, the method comprising: Obtaining a bounding volume hierarchy (BVH) structure, the BVH structure comprising a plurality of levels and a plurality of nodes, each level in the plurality of levels comprising at least one node in the plurality of nodes, the BVH structure being associated with geometric data of a plurality of primitives in a scene; identifying an amount of memory in a first memory available for storing at least some of the plurality of nodes in the BVH structure; allocating the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the storage amount in the first memory, the BVH structure being allocated based on a hierarchy of the plurality of nodes including the plurality of first nodes and the plurality of second nodes; as well as First data associated with the plurality of first nodes is stored in the first memory.

18. The method according to claim 17, further comprising: storing second data associated with the plurality of first nodes and the plurality of second nodes in a second memory; as well as After storing the first data and the second data, at least one of retrieving the first data from the first memory or retrieving the second data from the second memory is performed.

19. The method according to claim 18, further comprising: At least one of the first addresses of the plurality of first nodes or the second addresses of the plurality of second nodes is calculated before retrieving at least one of the first data or the second data, wherein the first data or the second data is retrieved based on the calculated first address or the calculated second address.

20. The method according to claim 19, wherein The first addresses of the multiple first nodes are calculated based on the offset value of the first memory and the node identifier (ID) of each first node in the multiple first nodes, and wherein the second addresses of the multiple second nodes are calculated based on the base address of the second memory and the node ID of each second node in the multiple second nodes.

21. The method according to claim 18, further comprising: At least one of ray-triangle intersection for a plurality of interior nodes among the plurality of nodes or ray-box intersection for a plurality of leaf nodes among the plurality of nodes is performed based on at least one of the first data or the second data.

22. The method according to claim 18, wherein At least one of the first data or the second data is retrieved based on a node identifier (ID) of each of the plurality of nodes in the BVH structure or a level ID of each of the plurality of levels.

23. The method according to claim 18, wherein At least one of the first data or the second data is retrieved based on the hierarchy of the plurality of first nodes, wherein the first memory is a graphics memory and the second memory is a system memory.

24. The method according to claim 18, wherein Retrieving at least one of the first data or the second data includes performing at least one of extracting the first data from the first memory or extracting the second data from the second memory.

25. The method according to claim 17, wherein The plurality of first nodes are associated with a first number of rays in a ray tracing process for the plurality of primitives in the scene, and wherein the plurality of second nodes are associated with a second number of rays in the ray tracing process, wherein the first number of rays is different from the second number of rays.

26. The method according to claim 17, wherein The hierarchy of the plurality of nodes is associated with a node identifier (ID) of each of the plurality of nodes and a level ID of each of the plurality of levels in the BVH structure, wherein the plurality of first nodes corresponds to a first segment of the plurality of levels and the plurality of second nodes corresponds to a second segment of the plurality of levels, wherein the BVH structure is allocated based on the first segment of the plurality of levels and the second segment of the plurality of levels, and wherein each of the plurality of levels includes a different level ID compared to other levels of the plurality of levels.

27. The method according to claim 17, wherein The plurality of first nodes correspond to high-level nodes in the BVH structure, and the plurality of second nodes correspond to low-level nodes in the BVH structure, wherein the high-level nodes include a root node in the BVH structure, and the low-level nodes include a plurality of leaf nodes.

28. The method according to claim 17, wherein The plurality of nodes includes a plurality of internal nodes and a plurality of leaf nodes, wherein the plurality of internal nodes are associated with a plurality of bounding boxes for the plurality of primitives, and wherein the plurality of leaf nodes are associated with the geometric data for the plurality of primitives.

29. The method according to claim 17, wherein The first data associated with the plurality of first nodes is equal to an amount of storage identified in the first memory.

30. A non-transitory computer-readable medium storing computer-executable code for graphics processing, the code, when executed by a processor, causing the processor to: Obtaining a bounding volume hierarchy (BVH) structure, the BVH structure comprising a plurality of levels and a plurality of nodes, each level in the plurality of levels comprising at least one node in the plurality of nodes, the BVH structure being associated with geometric data of a plurality of primitives in a scene; identifying an amount of memory in a first memory available for storing at least some of the plurality of nodes in the BVH structure; allocating the BVH structure into a first BVH segment including a plurality of first nodes and a second BVH segment including a plurality of second nodes based on the storage amount in the first memory, the BVH structure being allocated based on a hierarchy of the plurality of nodes including the plurality of first nodes and the plurality of second nodes; as well as First data associated with the plurality of first nodes is stored in the first memory.

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