Asic readout circuit for a diamond nitrogen-vacancy center based vector magnetometer

Abstract

The application discloses an ASIC readout circuit of a vector magnetometer based on a diamond nitrogen vacancy center, belongs to the technical field of circuits, and comprises a current-to-voltage module TIA, a secondary amplification module PGA, an ADC driving module ADC_Driver, an analog-to-digital converter SAR ADC, a low-temperature drift input reference Reference, a digital-to-analog conversion module, and a digital module DIG_TOP.

Description

TECHNICAL FIELD

[0001] The application relates to an ASIC readout circuit of a diamond nitrogen-vacancy center-based vector magnetometer and belongs to the technical field of circuits. BACKGROUND

[0002] At present, quantum system-based magnetometers include superconducting quantum interference devices (SQUIDs), Hall magnetometers and atomic magnetometers. Nitrogen-vacancy (N-V) centers in diamonds can also be used to realize magnetic field sensors. N-V center-based magnetometers have natural advantages in measuring vector magnetic fields. Nitrogen-vacancy color centers are a kind of point defects in diamonds, which belong to a kind of solid-state spins. The spin concentration of the solid-state system is higher than that of the gaseous system, the spin environment is more complex, the coherence time is usually shorter, and a larger detection bandwidth can be realized. Moreover, the four crystal axes of the diamond N-V center can simultaneously measure the magnetic field direction. Therefore, the N-V center-based magnetometer has rapidly developed into a current research hotspot, but lacks research on readout ASIC circuits.

[0003] The sensitivity in magnetic measurement is the minimum magnetic field that can be detected by the detector in unit time, and has:

[0004] ;

[0005] Where T is the measurement time, is the minimum detectable magnetic field. We can extend this formula to the shot noise limit sensitivity that is more concerned in the field. The shot noise limit sensitivity calculation formula based on the continuous wave method is:

[0006] ;

[0007] Where, is the line width correction coefficient, which is related to the spectral line type.

[0008] In the prior art, a continuous wave scheme system structure (reference: Schloss J M, Barry J F, Turner M J, et al. Simultaneous Broadband Vector Magnetometry Using Solid-State Spins [J]. Physical Review Applied, 2018, 10) includes laser excitation, microwave generation and magnetic field detection. The diamond crystal is a 4 mm x 4 mm x 0.5 mm chip with 110 edges and 100 front faces, and the N to NV- conversion efficiency is about 10%. The diamond is adhered to a 2-inch diameter, 330-µm thick semi-insulating silicon carbide (SiC) wafer for thermal and mechanical stabilization. About 3.3 W, 400-µm Gaussian 1 / e2width light beam is irradiated at ≈73° to the normal of the 100 faces of the diamond chip to excite NV. A non-spherical, non-spherical capacitor collects photoluminescence (PL) and directs it through a 633-nm long-pass filter, and then about 52 mW of PL is imaged onto a photodiode and digitized. The picked-up portion (about 135 mW) of the green excitation light is collected onto a second photodiode and digitized for software-based laser intensity noise cancellation.

[0009] Four independent microwave sources generate four carrier signals with frequencies νλ, νχ, νϕand νκ. Laser and microwave excitation of NV centers in a diamond sensor crystal and PL collection scheme. The diamond is attached to one side of a silicon carbide (SiC) wafer for stabilization and heat dissipation. The microwave loop on the back of the SiC provides a modulated microwave drive for NV integration. Excitation light at 532 nm enters the diamond at ≈73° to the normal, and the PL is collected by the aspheric apla natural condenser shown below the diamond. A digital-to-analog converter (DAC) outputs a microwave frequency modulation (FM) waveform. The microwave is generated by four sources and mixed with a 2.158-MHz radio frequency (RF) signal to produce a modulated carrier and sidebands, which are amplified, combined, and radiated by the microwave loop. Separate microwave amplifiers are used to avoid intermodulation. The excitation laser beam passes through a polarizer, a half-wave plate (HWP), and a focusing lens. After passing through the mirror, the beam passes through a beam sampler, where a portion is imaged onto a photodiode and digitized at an analog-to-digital converter (ADC); the rest of the beam illuminates the diamond. The diamond PL is collected by an aspheric condenser, long-pass filtered at 633 nm, imaged onto a photodiode, and digitized.

[0010] This technique has high sensitivity and wide vector magnetic measurement, but requires complex microwave components to cooperate with the readout circuit, and is only for a single optical detector using modulated continuous wave (CW)-optical detection of magnetic resonance (ODMR). SUMMARY

[0011] The technical problem to be solved by the present application is to overcome the defects of the prior art and provide an ASIC readout circuit of a diamond nitrogen vacancy center-based vector magnetometer.

[0012] To solve the above technical problems, the present application is implemented by using the following technical solutions.

[0013] The present application provides an ASIC readout circuit of a diamond nitrogen vacancy center-based vector magnetometer, comprising: a current-to-voltage module TIA, a two-stage amplification module PGA, an ADC driver module ADC_Driver, a digital module DIG_TOP, an analog-to-digital converter SAR ADC, and a low-temperature drift input reference Reference integrated in a chip.

[0014] The current-to-voltage module TIA converts the current signal collected and converted by the front-end quantum probe into a proportional voltage signal and filters out the DC component, and inputs the voltage signal into the two-stage amplification module PGA.

[0015] The two-stage amplification module PGA performs low-pass filtering on the input signal twice and sends the signal to the analog-to-digital converter SAR ADC via the ADC driver module ADC_Driver.

[0016] The analog-to-digital converter SAR ADC performs analog-to-digital conversion on the input signal and outputs a digital signal.

[0017] The low-temperature drift input reference Reference is used to drive the digital-to-analog conversion module of the analog-to-digital converter SAR ADC.

[0018] The digital module DIG_TOP provides the required digital signal for the entire ASIC readout circuit.

[0019] Further, the current-to-voltage module TIA comprises a transimpedance amplifier and a built-in feedback resistor circuit, the built-in feedback circuit comprising a feedback resistor R1 and a feedback capacitor C1.

[0020] The positive input end of the transimpedance amplifier is connected to the positive input end AIN_P of the chip and the two-stage amplification module PGA, respectively, and the positive input end AIN_P is used to input a common-mode signal.

[0021] The inverting input end of the operational amplifier is connected to the negative input port AIN_N of the chip, one end of the first feedback resistor R1, and one end of the first feedback capacitor C1, respectively, and the negative input port AIN_N is used to input the current signal converted after the quantum probe collects the optical signal.

[0022] The other end of the feedback resistor R1 and the other end of the feedback capacitor C1 are connected to the output end of the trans-impedance amplifier through the switch S1, and the output end of the trans-impedance amplifier is also connected to the lead-out end RF_0 of the chip, which is used to externally connect an external feedback resistor R5 or an external AC coupling capacitor C2.

[0023] Further, the external feedback resistor R5 is connected in parallel with an external feedback capacitor C5 to form an external feedback resistor circuit, one end of the external feedback resistor circuit is connected to the lead-out end RF_0 through the switch S2, and the other end of the external feedback resistor circuit is connected to the negative input port AIN_N.

[0024] Further, the switch S1 and the switch S2 are not closed at the same time, which is used to select to enable the built-in feedback resistor circuit and the external feedback resistor circuit according to the size of the input current signal.

[0025] Further, the determination condition for closing the switch S1 or the switch S2 is:

[0026] According to the required resistance value calculated according to different current input ranges, if the first feedback resistor R1 cannot meet the required resistance value, the switch S1 is disconnected, the switch S2 is closed, and the external feedback resistor circuit is turned on; otherwise, the switch S1 is closed and the switch S2 is disconnected, and the built-in feedback resistor circuit is turned on.

[0027] Further, one end of the external AC coupling capacitor C2 is connected to the lead-out end RF_0, and the other end of the external AC coupling capacitor C2 is connected to the secondary amplification module PGA.

[0028] Further, the secondary amplification module PGA includes: a programmable gain amplifier, a negative phase first resistor R2, a negative phase second resistor R3, a positive phase third resistor R4´, a positive phase first resistor R2´, a positive phase second resistor R3´, a positive phase third resistor R4´, and an adjustable capacitor C4.

[0029] The positive phase input end of the programmable gain amplifier is respectively connected to one end of the positive phase first resistor R2´ and one end of the positive phase second resistor R3´, and the other end of the positive phase first resistor R2´ is connected to the other end of the external AC coupling capacitor C2.

[0030] The first output end of the programmable gain amplifier is respectively connected to the other end of the positive phase second resistor R3´ and one end of the positive phase third resistor R4´, and the other end of the positive phase third resistor R4´ is respectively connected to one end of the adjustable capacitor C4 and the ADC driving module ADC_Driver.

[0031] The negative phase input end of the programmable gain amplifier is respectively connected to one end of the negative phase first resistor R2 and one end of the negative phase second resistor R3, and the other end of the negative phase first resistor R2 is connected to the other end of the external AC coupling capacitor C2.

[0032] The second output end of the programmable gain amplifier is connected to the other end of the negative phase second resistor R3 and the one end of the negative phase third resistor R4 respectively, and the other end of the negative phase third resistor R4 is connected to the one end of the adjustable capacitor C4 and the ADC driving module ADC_Driver respectively.

[0033] Further, the negative phase first capacitor C3 and the positive phase first capacitor C3' are further included.

[0034] The negative phase first capacitor C3 is connected to the negative phase second resistor R3 in parallel, and the positive phase first capacitor C3' is connected to the positive phase second resistor R3' in parallel.

[0035] Further, the ADC driving module ADC_Driver includes the first ADC driving module ADC_Driver and the second ADC driving module ADC_Drive.

[0036] The positive phase input end of the first ADC driving module ADC_Driver is connected to the other end of the positive phase third resistor R4', and the negative phase input end of the first ADC driving module ADC_Driver is connected to the output end of the first ADC driving module ADC_Driver and then connected to the analog-to-digital converter SAR ADC.

[0037] The positive phase input end of the second ADC driving module ADC_Driver is connected to the other end of the negative phase third resistor R4, and the negative phase input end of the second ADC driving module ADC_Driver is connected to the output end of the second ADC driving module ADC_Driver and then connected to the analog-to-digital converter SAR ADC.

[0038] Further, the calculation formula of the bandwidth of the ADC driving module ADC_Driver is as follows:

[0039] ;

[0040] Wherein, BW The bandwidth of the ADC driving module ADC_Driver is represented, N The preset voltage establishment accuracy is represented, T s The sampling time is represented.

[0041] The beneficial effects achieved by the present application are as follows:

[0042] The readout circuit of the present application realizes the effect of second-order low-pass filtering through the second amplification module PGA, so that the circuit has good noise performance; the present application can greatly reduce power consumption and noise, without increasing circuit complexity, and can well achieve the effect of ensuring gain accuracy. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1 The schematic diagram of the ASIC readout circuit described in the application is shown.

[0044] Figure 2 The structure block diagram of the readout circuit SAR ADC described in the application is shown. DETAILED DESCRIPTION

[0045] The application will be further described below in conjunction with the drawings. The following examples are only used to more clearly illustrate the technical solutions of the application, and cannot be used to limit the protection scope of the application.

[0046] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to facilitate the description of the application and simplify the description, and therefore cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the application. In addition, the terms "first", "second" and the like are only used for description purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include one or more features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0047] In the description of the present application, it should be noted that unless otherwise specified and limited, the terms "mounting", "connection", "connection" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0048] Example 1, this embodiment introduces an ASIC readout circuit of a vector magnetometer based on diamond nitrogen vacancy center, as shown in Figure 1 The schematic diagram of the ASIC readout circuit described in the application is shown. It includes: a current-to-voltage module TIA, a two-stage amplification module PGA, an ADC driver module ADC_Driver, a digital module DIG_TOP, an analog-to-digital converter SAR ADC, and a low-temperature drift input reference Reference integrated in a chip.

[0049] The current-voltage conversion module TIA converts the collected current signal into a proportional voltage signal and filters out the DC component, and then inputs the signal into the secondary amplification module PGA.

[0050] The secondary amplification module PGA performs second-order low-pass filtering on the input signal and then transmits the signal to the analog-to-digital converter SAR ADC through the ADC driver module ADC_Driver.

[0051] The analog-to-digital converter SAR ADC performs analog-to-digital conversion on the input signal and outputs a digital signal.

[0052] The low-temperature drift input reference Reference is used to drive the digital-to-analog conversion module of the analog-to-digital converter SAR ADC.

[0053] The digital module DIG_TOP provides the required digital signal for the entire ASIC readout circuit.

[0054] The current-voltage conversion module TIA includes a transimpedance amplifier and a built-in feedback resistor circuit, which includes a feedback resistor R1, a feedback capacitor C1, and a selection switch S1.

[0055] The positive input end of the transimpedance amplifier is connected to the positive input end AIN_P of the chip and the secondary amplification module PGA, respectively, and the positive input end AIN_P is used to input a common-mode signal.

[0056] The inverting input end of the operational amplifier is connected to the negative input port AIN_N of the chip, one end of the first feedback resistor R1, and one end of the first feedback capacitor C1, respectively, and the negative input port AIN_N is used to input the current signal converted after the quantum probe collects the light signal.

[0057] The other end of the feedback resistor R1 and the other end of the feedback capacitor C1 are connected to the switch S1 and then connected to the output end of the transimpedance amplifier, and the output end of the transimpedance amplifier is also connected to the lead-out end RF_0 of the chip, which is used to externally connect an external feedback resistor R5 or an external AC coupling capacitor C2.

[0058] One end of the external AC coupling capacitor C2 is connected to the lead-out end RF_0, and the other end of the external AC coupling capacitor C2 is connected to the secondary amplification module PGA.

[0059] Wide DC dynamic range: When the received light signal is large, the current generated by the photodetector contains a DC component. It will obviously change the DC operating point of the circuit and weaken the ability of the receiver to amplify the signal. Therefore, in order to obtain a wide DC dynamic range, a DC elimination technique must be designed, and an AC coupling capacitor is added at the output end of the TIA Figure 1The AC coupling capacitor is used to eliminate the DC component, and the AC coupling capacitor and the feedback resistor can be realized by external connection, so that the power consumption and noise are greatly reduced.

[0060] The good cross resistance precision is achieved by using the external feedback resistor (R5) and the external feedback capacitor (C5). Figure 1 The gain precision is ensured without increasing the circuit complexity.

[0061] The external feedback resistor (R5) and the external feedback capacitor (C5) are connected in parallel to form an external feedback resistor circuit, one end of the external feedback resistor circuit is connected to the switch S2 and then connected to the lead-out terminal RF_0, and the other end of the external feedback resistor circuit is connected to the negative input port AIN_N. The parallel capacitor can avoid input oscillation.

[0062] The switch S1 and the switch S2 are not closed at the same time, and are used to select the built-in feedback resistor circuit and the external feedback resistor circuit according to the size of the input current signal. Because the input current range is large, it is impossible to consider all resistance values of the built-in feedback resistor circuit. In order to improve the adaptability of the chip, the lead-out terminal RF_0 is used to control the built-in feedback resistor circuit or the external feedback resistor circuit to be connected to the overall circuit through the switch S1 and the switch S2, so that the adaptability of the chip is improved and the cost is reduced.

[0063] The secondary amplification module PGA includes a programmable gain amplifier, a negative phase first resistor R2, a negative phase second resistor R3, a positive phase third resistor R4´, a positive phase first resistor R2´, a positive phase second resistor R3´, a positive phase third resistor R4´, and an adjustable capacitor C4.

[0064] The positive input end of the programmable gain amplifier is connected to one end of the positive phase first resistor R2´ and one end of the positive phase second resistor R3´, respectively, and the other end of the positive phase first resistor R2´ is connected to the other end of the external AC coupling capacitor C2.

[0065] The first output end of the programmable gain amplifier is connected to the other end of the positive phase second resistor R3´ and one end of the positive phase third resistor R4´, respectively, and the other end of the positive phase third resistor R4´ is connected to one end of the adjustable capacitor C4 and the ADC driving module ADC_Driver, respectively.

[0066] The negative input end of the programmable gain amplifier is connected to one end of the negative phase first resistor R2 and one end of the negative phase second resistor R3, respectively, and the other end of the negative phase first resistor R2 is connected to the other end of the external AC coupling capacitor C2.

[0067] The second output end of the programmable gain amplifier is connected to the other end of the negative phase second resistor R3 and the one end of the negative phase third resistor R4 respectively, and the other end of the negative phase third resistor R4 is connected to the one end of the adjustable capacitor C4 and the ADC driving module ADC_Driver respectively.

[0068] Further comprising: a negative phase first capacitor C3 and a positive phase first capacitor C3';

[0069] The negative phase first capacitor C3 is connected to the negative phase second resistor R3 in parallel, and the positive phase first capacitor C3' is connected to the positive phase second resistor R3' in parallel.

[0070] The secondary amplification module PGA is a full differential operational amplifier, in order to reduce the chip area, the input stage of the operational amplifier only adopts a single set of folded common-gate structure with PMOS tube input, and the PMOS tube input has better noise performance, which can realize rail-to-rail input of negative power supply, and the programmable gain amplifier and the negative phase first resistor R2 and the negative phase second resistor R3 constitute a voltage amplifier with voltage offset and single conversion difference function, and the value of the negative phase second resistor R3 is 10 times the value of the negative phase first resistor R2. On the feedback branch, the negative phase first capacitor C3 is connected to the negative phase second resistor R3 in parallel, and the value can be configured in linkage with the negative phase second resistor R3, providing a first-order low-pass filter function. The negative phase third resistor R4 and the adjustable capacitor C4 constitute a first-order passive RC low-pass filter, and the value of the adjustable capacitor C4 is adjustable, that is, the passband cutoff frequency of the RC filter can be adjusted. The filter realizes the suppression of the wideband noise in the PGA, and it and the first-order low-pass filter in the PGA together constitute a second-order low-pass filter effect, so that the circuit has good noise suppression performance.

[0071] Similarly, the positive phase third resistor R4', the positive phase first resistor R2', the positive phase second resistor R3', the adjustable capacitor C4 and the programmable gain amplifier can realize the suppression of the wideband noise in the PGA, and it and the first-order low-pass filter in the PGA together constitute a second-order low-pass filter effect, so that the positive phase and the negative phase both have good noise suppression performance.

[0072] The ADC driving module ADC_Driver includes a first ADC driving module ADC_Driver and a second ADC driving module ADC_Drive;

[0073] The positive phase input end of the first ADC driving module ADC_Driver is connected to the other end of the positive phase third resistor R4', and the negative phase input end of the first ADC driving module ADC_Driver is connected to the output end of the first ADC driving module ADC_Driver and then connected to the analog-to-digital converter SAR ADC;

[0074] The positive phase input end of the second ADC driving module ADC_Driver is connected to the other end of the negative phase third resistor R4, and the negative phase input end of the second ADC driving module ADC_Driver is connected to the output end of the second ADC driving module ADC_Driver and then connected to the analog-to-digital converter SAR ADC.

[0075] The output voltage of the TIA depends on the feedback resistor R1 and also on the value of the feedback capacitor C1, and the bandwidth of the amplifier circuit mainly depends on the value of the feedback capacitor C1, so the value of the feedback capacitor C1 will change the bandwidth of the entire circuit, so in order to make the circuit work stably in the entire bandwidth, the required capacitor value needs to be calculated according to different current input ranges:

[0076] ;

[0077] Where R1 represents the feedback resistor, and fp is the bandwidth frequency.

[0078] First, calculate the feedback resistor R1 according to the required output voltage and input current, and select the built-in feedback resistor circuit when the built-in feedback resistor meets the requirements, otherwise, select the off-chip feedback resistor circuit, select the off-chip feedback resistor R5 that meets the requirements, and select the off-chip feedback capacitor C5 according to the selected off-chip feedback resistor R5, and the selection of the off-chip feedback capacitor C5 needs to meet .

[0079] In order to drive the sampling capacitor of the SAR ADC to a predetermined precision within a specified time, the ADCDriver needs to achieve a certain bandwidth, and the calculation formula of the bandwidth of the ADCDriver is:

[0080] ;

[0081] Where, BW represents the bandwidth of the ADCDriver, N represents the preset voltage establishment precision, T s is the sampling time.

[0082] Embodiment 2, based on the same inventive concept as embodiment 1, this embodiment introduces an ASIC readout circuit based on a diamond nitrogen vacancy center vector magnetometer, which is used in a diamond nitrogen-vacancy color center readout system, such as Figure 1As shown, the ASIC readout circuit includes: current-to-voltage module TIA, two-stage amplification module PGA, ADC driver module ADC_Driver, digital module DIG_TOP, analog-to-digital converter SAR ADC, and low-temperature drift input reference Reference. In operation, first, the TIA converts the current signal collected and converted by the front-end quantum probe into a proportional voltage signal, followed by a large DC blocking capacitor to filter out the DC component, then enters the two-stage amplification circuit, and after the RC filter, the ADC_Driver is transmitted to the ADC for conversion, and the digital signal is output. The low-temperature drift input reference Reference voltage is provided by a built-in class-AB drive amplifier with an output resistance of 0.5 ohms or less, which is used to drive the digital-to-analog conversion module of the SAR ADC. The digital module DIG_TOP provides the required digital signals (such as ADC enable signal, PGA enable signal, logic timing signal, etc.) for the entire circuit; for example Figure 1 As shown, the interface of the chip also includes analog power supply AVDD, analog ground AGND, digital power supply DVDD, digital ground DGND, shorted analog GND reference REFGND, external reference input REFIO, and reference decoupling capacitor input REFCAP.

[0083] When using external reference input, the switch S3 is disconnected, at which time the REFIO serves as the reference Reference voltage input terminal. Considering the current output capability, an OTA circuit is added as a buffer BUFFER.

[0084] The transimpedance gain of the TIA affects the lower limit of the noise current converted to the input terminal, so a low-value feedback resistor and a transimpedance precision will also reduce the noise performance of the TIA circuit. Generally, the transimpedance of the TIA can be calibrated by fine-tuning with many pads and fuses, but this will greatly increase the silicon area and test budget. The gain error of the TIA can also be compensated by a rear-end digital signal processing algorithm, but this increases the circuit complexity and test budget. Therefore, we designed the RF_0 lead-out terminal in this design, which can use an external feedback resistor (R5) to ensure gain accuracy. Disconnect the switch S1 and connect the RF_0 lead-out terminal and the negative input terminal AIN_N externally, which does not increase the circuit complexity and achieves the purpose well. Figure 1

[0085] When the received optical signal is large, the current generated by the photodetector will contain a DC component. In order to obtain a wide DC range, various DC elimination circuits are usually added in the TIA, but this similar technology greatly increases power consumption and noise due to the introduction of additional circuits. The present application utilizes an AC coupling capacitor added to the output terminal of the TIA Figure 1 ​The AC coupling capacitor is also realized by external connection as the feedback resistor, so that the power consumption and noise are greatly reduced.

[0086] The output voltage of the TIA depends on the feedback resistor R1 and the value of the feedback capacitor C1, and the bandwidth of the amplifier circuit mainly depends on the value of the feedback capacitor C1, so the value of the feedback capacitor C1 changes the bandwidth of the entire circuit, so in order to make the circuit work stably in the entire bandwidth, the required capacitor value needs to be calculated according to different current input ranges:

[0087] ;

[0088] Where R1 represents the feedback resistor, and fp is the bandwidth frequency.

[0089] The PGA is a full differential operational amplifier, in order to reduce the chip area, the input stage of the operational amplifier only adopts a single set of folded common-gate structure with PMOS input, and the PMOS input has better noise performance, which can realize rail-to-rail input of negative power supply, and the PGA and R2-R3 constitute a voltage amplifier with voltage offset and single conversion difference function, and the value of R3 is 10 times that of R2. On the feedback branch, C3 is connected in parallel with R3, and the value of C3 can be configured in conjunction with R3, thereby providing a first-order low-pass filter function. R4 and C4 constitute a first-order passive RC low-pass filter, and the value of C4 is adjustable, that is, the passband cutoff frequency of the RC filter can be adjusted. The filter realizes the suppression of the wideband noise in the PGA, and it and the first-order low-pass filter in the PGA together constitute a second-order low-pass filter effect, so that the circuit has good noise performance.

[0090] In order to drive the sampling capacitor of the SAR ADC to a predetermined precision within a specified time, the ADCDriver needs to achieve a certain bandwidth:

[0091] ;

[0092] Where, BW Bandwidth of the ADC driver module ADC_Driver, N Vset represents the preset voltage establishment precision, T s Tsample represents the sampling time.

[0093] The analog-to-digital converter ADC adopts a 16-bit SAR ADC, and the structural diagram is as follows: Figure 2As shown, the maximum sampling rate is 500 kHz, mainly including a DAC module, a comparator, a SAR logic module and an interface module; in order to reduce the size of the capacitor as much as possible, a resistance-capacitance coupling structure is used in the DAC, the high bit is a capacitor, and the low bit is a resistor; in order to reduce the requirement for VREF, a redundant bit design is used, 2 redundant bits, so there are 18 digital outputs, and then the 18-bit output is converted into a 16-bit output in the digital part. The size of each capacitor in the DAC part is set as Figure 2 As shown; the SAR logic part adopts asynchronous conversion logic; the comparator adopts a three-stage static preamplification + dynamic latch structure.

[0094] The embodiment realizes:

[0095] 1) Low input current noise. The input stage of the two-stage amplification module PGA only uses a single set of folded cascode structure with PMOS input, and the PMOS input has better noise performance. The PGA provides a first-order low-pass filter function on the feedback branch, followed by a first-order passive RC low-pass filter, which together with the first-order low-pass filter in the PGA constitutes a two-order low-pass filter effect, so that the circuit has good noise performance.

[0096] 2) Wide DC dynamic range. When the received optical signal is large, the current generated by the photodetector contains a DC component. It will obviously change the DC operating point of the circuit and weaken the ability of the receiver to amplify the signal. Therefore, in order to obtain a wide DC dynamic range, a DC elimination technique must be designed, and an AC coupling capacitor (C2 in Figure 1 ) is added at the output end of the TIA to remove the DC component. This AC coupling capacitor can also be realized by external connection as the feedback resistor, thereby greatly reducing power consumption and noise.

[0097] 3) Good transimpedance accuracy. The design of the lead-out end RF_0 can use an external feedback resistor (R5 in Figure 1 ) to ensure gain accuracy, without increasing the complexity of the circuit and achieving the purpose well.

[0098] The above only describes the preferred embodiments of the present application, and it should be noted that for ordinary skilled persons in the art, without departing from the technical principles of the present application, a number of improvements and modifications can be made, and these improvements and modifications should be considered as the protection scope of the present application.

Claims

1. An ASIC readout circuit for a vector magnetometer based on diamond nitrogen vacancy centers, characterized in that: include: Integrated in the chip are the current-to-voltage module TIA, the secondary amplifier module PGA, the ADC driver module ADC_Driver, the digital module DIG_TOP, the analog-to-digital converter SAR ADC, and the low-temperature drift input reference Reference; The current-to-voltage module TIA converts the current signal collected and converted by the front-end quantum probe into a proportional voltage signal and filters out the DC component before inputting it into the secondary amplification module PGA; The secondary amplifier module PGA performs a second-order low-pass filter on the input signal and then transmits it to the analog-to-digital converter SAR ADC through the ADC driver module ADC_Driver; The analog-to-digital converter SAR ADC performs analog-to-digital conversion on the input signal and outputs a digital signal; The low temperature drift input reference Reference is used to drive the digital-to-analog conversion module of the analog-to-digital converter SAR ADC; The digital module DIG_TOP provides the required digital signals for the entire ASIC readout circuit; The secondary amplifier module PGA includes: a programmable gain amplifier, a negative phase first resistor R2, a negative phase second resistor R3, a positive phase third resistor R4', a positive phase first resistor R2', a positive phase second resistor R3', a positive phase third resistor R4' and an adjustable capacitor C4; The non-inverting input terminal of the programmable gain amplifier is respectively connected to one end of the first positive-phase resistor R2' and one end of the second positive-phase resistor R3', the other end of the first positive-phase resistor R2' is connected to one end of the off-chip AC coupling capacitor C2, and the other end of the off-chip AC coupling capacitor C2 is connected to the lead terminal RF_0 of the chip, and the lead terminal RF_0 of the chip is connected to the output terminal of the transimpedance amplifier of the current-to-voltage module TIA; The first output terminal of the programmable gain amplifier is respectively connected to the other end of the second positive-phase resistor R3' and one end of the third positive-phase resistor R4', and the other end of the third positive-phase resistor R4' is respectively connected to one end of the adjustable capacitor C4 and an ADC driver module ADC_Driver; The negative phase input terminal of the programmable gain amplifier is connected to one end of the negative phase first resistor R2 and one end of the negative phase second resistor R3 respectively, and the other end of the negative phase first resistor R2 is connected to the lead-out terminal RF_0 of the chip; The second output end of the programmable gain amplifier is respectively connected to the other end of the negative phase second resistor R3 and one end of the negative phase third resistor R4, and the other end of the negative phase third resistor R4 is respectively connected to the other end of the adjustable capacitor C4 and another ADC driver module ADC_Driver; It also includes: a negative phase first capacitor C3 and a positive phase first capacitor C3'; The negative phase first capacitor C3 is connected in parallel with the negative phase second resistor R3 , and the positive phase first capacitor C3 ′ is connected in parallel with the positive phase second resistor R3 ′.

2. The ASIC readout circuit of the diamond nitrogen vacancy center-based vector magnetometer according to claim 1, characterized in that: The current-to-voltage module TIA includes a transimpedance amplifier and a built-in feedback resistor circuit, wherein the built-in feedback resistor circuit includes a first feedback resistor R1, a feedback capacitor C1 and a selection switch S1; The non-inverting input terminal of the transimpedance amplifier is connected to the positive input terminal AIN_P of the chip and the secondary amplifier module PGA respectively, and the positive input terminal AIN_P is used to input a common mode signal; The inverting input terminal of the transimpedance amplifier is respectively connected to the negative input port AIN_N of the chip, one end of the first feedback resistor R1 and one end of the first feedback capacitor C1. The negative input port AIN_N is used to input the current signal converted after the quantum probe collects the optical signal; The other end of the first feedback resistor R1 and the other end of the first feedback capacitor C1 are connected to the switch S1 and then to the output end of the transimpedance amplifier. The output end of the transimpedance amplifier is also connected to the lead-out terminal RF_0 of the chip. The lead-out terminal RF_0 is used to connect an external off-chip feedback resistor R5 or an off-chip AC coupling capacitor C2.

3. The ASIC readout circuit of the diamond nitrogen vacancy center-based vector magnetometer according to claim 2, characterized in that: The off-chip feedback resistor R5 is connected in parallel with an off-chip feedback capacitor C5 to form an off-chip feedback resistor circuit. One end of the off-chip feedback resistor circuit is connected to the switch S2 and then to the lead-out terminal RF_0. The other end of the off-chip feedback resistor circuit is connected to the negative input port AIN_N.

4. The ASIC readout circuit of the diamond nitrogen vacancy center-based vector magnetometer according to claim 3, characterized in that: The switch S1 and the switch S2 are not closed at the same time, and are used to selectively enable the built-in feedback resistor circuit and the off-chip feedback resistor circuit according to the magnitude of the input current signal.

5. The ASIC readout circuit of the diamond nitrogen vacancy center-based vector magnetometer according to claim 4, characterized in that: The conditions for closing switch S1 or switch S2 are: The required resistance value is calculated according to different current input ranges. If the first feedback resistor R1 cannot meet the required resistance value, the switch S1 is opened and the switch S2 is closed to conduct the off-chip feedback resistor circuit; otherwise, the switch S1 is closed and the switch S2 is opened to conduct the built-in feedback resistor circuit.

6. The ASIC readout circuit of the diamond nitrogen vacancy center-based vector magnetometer according to claim 1, characterized in that: The ADC driving module ADC_Driver includes a first ADC driving module ADC_Driver and a second ADC driving module ADC_Drive; A positive phase input terminal of the first ADC driver module ADC_Driver is connected to the other end of the positive phase third resistor R4', and a negative phase input terminal of the first ADC driver module ADC_Driver is connected to the output terminal of the first ADC driver module ADC_Driver and then connected to an analog-to-digital converter SAR ADC; The positive phase input terminal of the second ADC driver module ADC_Driver is connected to the other end of the negative phase third resistor R4, and the negative phase input terminal of the second ADC driver module ADC_Driver is connected to the output terminal of the second ADC driver module ADC_Driver and then connected to the analog-to-digital converter SAR ADC.

7. The ASIC readout circuit of the diamond nitrogen vacancy center based vector magnetometer according to claim 1, characterized in that: The calculation formula of the bandwidth of the ADC driver module ADC_Driver is: ； in, BW Indicates the bandwidth of the ADC driver module ADC_Driver, N Indicates the preset voltage establishment accuracy, T s is the sampling time.

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