A calibration method and system for a digital time converter

Abstract

The present invention relates to a calibration method and system for a digital time converter in the technical field of electronic circuits, comprising the following steps: setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase; keeping the reference clock of the delay circuit at the preset phase, delaying the digital time converter for the first time to a target detection phase one, recording phase information one detected by the time digital converter, and code value information one of the digital time converter corresponding to the phase information one; keeping the reference clock of the delay circuit at the preset phase, delaying the digital time converter again to a target detection phase two, recording phase information two detected by the time digital converter, and code value information two of the digital time converter corresponding to the phase information two; and calculating a calibration result based on phase information one, code value information one, phase information two, and code value information two, thereby solving the problem that the digital time converter is unstable and cannot provide an accurate value.

Description

Technical Field

[0001] The invention relates to the technical field of electronic circuits, and in particular to a calibration method and system for a digital time converter. Background Art

[0002] Fractional division means that the division ratio is not an integer, but contains an integer part and a fractional part. For example, if a divider with a division ratio of 2.5 is required, it will switch the division ratio between different cycles, such as using 2 times division in some cycles and 3 times division in other cycles. Since it is difficult to achieve fractional division (fractionl-n) in traditional analog phase-locked loops, the full digital phase-locked loop (ADPLL) is derived to solve this problem. However, since the full digital phase-locked loop must use a digital time converter (DTC) when implementing fractional division (fractionl-n), and the digital time converter (DTC) is accompanied by process deviations, temperature changes, unstable power supply voltage, etc., it will affect its performance and make it unable to output a fixed accurate value. Therefore, before fractional division, calibration of the digital time converter becomes an important link. Summary of the invention

[0003] In view of the shortcomings of the prior art, the present invention provides a calibration method and system for a D digital time converter, which solves the problem that the digital time converter is unstable and cannot provide accurate values.

[0004] In order to solve the above technical problems, the present invention is solved by the following technical solutions:

[0005] A method for calibrating a digital time converter comprises the following steps:

[0006] Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase based on the preset phase difference;

[0007] Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase;

[0008] Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2;

[0009] Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated.

[0010] Optionally, delaying the reference clock to a preset phase based on the preset phase difference comprises the following steps:

[0011] Adjusting the delay information of the reference clock and detecting the phase adjustment information of the time-to-digital converter;

[0012] When the phase adjustment information reaches a preset phase difference, the reference clock is adjusted according to the delay information when the preset phase difference is reached and reaches a preset phase.

[0013] Optionally, calculating the calibration result of the digital-to-time converter comprises the following steps:

[0014] Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2;

[0015] A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference / phase information difference.

[0016] Optionally, when the digital-to-time converter performs the first delay, phase information one detected by the time-to-digital converter, and when the digital-to-time converter performs the second delay, phase information two detected by the time-to-digital converter are adjacent phases or non-adjacent phases.

[0017] A method for calibrating a digital time converter comprises the following steps:

[0018] Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase one based on the preset phase difference;

[0019] Keep the reference clock of the delay circuit at the preset phase one, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one;

[0020] Delaying the reference clock of the delay circuit to a preset phase two based on the preset phase difference;

[0021] Keep the reference clock of the delay circuit at the preset phase 2, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2, wherein the preset phase difference is also the phase difference between the target detection phase 2 and the preset phase 2;

[0022] Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated.

[0023] A calibration system for a digital-to-time converter, the calibration system for the digital-to-time converter executing the calibration method for the digital-to-time converter as described above, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit;

[0024] The calibration logic circuit is used to provide a preset phase difference;

[0025] The delay circuit is used to delay the input reference clock to a preset phase based on the preset phase difference;

[0026] The digital time conversion circuit is used to perform multiple delay processing on the input reference clock to delay the input reference clock to target detection phase 1 and target detection phase 2 respectively, and obtain code value information 1 and code value information 2, wherein the preset phase difference is the phase difference between the target detection phase 1 and the preset phase;

[0027] The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process;

[0028] The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

[0029] Optionally, the delay circuit delays the reference clock to a preset phase based on the preset phase difference, comprising the following steps:

[0030] The delay circuit adjusts the delay information of the reference clock;

[0031] The time-to-digital conversion circuit detects phase adjustment information, and when the phase adjustment information reaches a preset phase difference, the delay information of the reference clock reaches a preset phase.

[0032] Optionally, the calibration logic circuit outputs the calibration result, comprising the following steps:

[0033] Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2;

[0034] A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference / phase information difference.

[0035] A calibration system for a digital-to-time converter, the calibration system for the digital-to-time converter executing the calibration method for the digital-to-time converter as described above, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit;

[0036] The calibration logic circuit is used to provide a preset phase difference;

[0037] The delay circuit is used to delay the input reference clock to a preset phase one and a preset phase two respectively based on the preset phase difference;

[0038] The digital time conversion circuit is used to perform a first delay process on the input reference clock after the delay circuit delays the input reference clock to the preset phase one, so as to delay the input reference clock to the target detection phase one, and obtain code value information one; after the delay circuit delays the input reference clock to the preset phase two, perform a second delay process on the input reference clock, so as to delay the input reference clock to the target detection phase two, and obtain code value information two, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one, and the preset phase difference is also the phase difference between the target detection phase two and the preset phase two;

[0039] The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process;

[0040] The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

[0041] Compared with the prior art, the technical solution provided by the invention has the following beneficial effects:

[0042] By presetting the phase difference and delaying the reference clock to a preset phase, the problem of inaccurate output value of the time digital converter caused by process deviation, temperature change, unstable power supply voltage, etc. is avoided. Specifically, compared with not performing reference clock delay processing, the present application reduces the error of the time digital converter when performing phase measurement each time by adjusting the reference clock to a preset phase, thereby improving the calibration accuracy and preventing clock jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0044] Figure 1 This is a flow chart of a calibration method for a digital-to-time converter proposed in the first embodiment;

[0045] Figure 2 This is one of the schematic diagrams of the time link proposed in the first embodiment, when the chain length of the time digital converter is 40 chain lengths and the chain lengths of 28 to 29 are calibrated;

[0046] Figure 3 The second schematic diagram of the time link when the chain length of the time digital converter is 40 chain lengths and the chain lengths of 28 to 29 are calibrated according to the second embodiment;

[0047] Figure 4 This is a system structure diagram of a calibration system for a digital-to-time converter proposed in the second embodiment. DETAILED DESCRIPTION

[0048] The present invention is further described in detail below in conjunction with embodiments. The following embodiments are for explanation of the present invention but the present invention is not limited to the following embodiments.

[0049] Example 1

[0050] like Figure 1 As shown, a calibration method for a digital time converter includes the following steps: first, before calibrating the digital time converter, it is necessary to clarify the phase difference value that needs to be measured, and the phase difference value must be preset in the calibration logic circuit. Therefore, first, a preset phase difference is set in the logic circuit, and based on the preset phase difference, the reference clock in the delay circuit is delayed to a preset phase, and the delay circuit state is kept unchanged to ensure that the reference clock is always at the preset phase. It should be noted that in this embodiment, the preset phase difference is 0~3 phases.

[0051] Specifically, in order to ensure that the phase difference to be measured is the preset phase difference, it is necessary to adjust the delay information of the reference clock and detect the phase adjustment information of the time digital converter; when the phase adjustment information reaches the preset phase difference, the reference clock is adjusted according to the delay information when the preset phase difference is reached and reaches the preset phase, thereby ensuring that the delay information when adjusting the reference clock is accurate and can reach the preset phase difference by detecting the phase adjustment information of the time digital converter. After reaching the preset phase, the delay circuit keeps its circuit parameters unchanged.

[0052] like Figure 2 As shown, in this embodiment, taking the link length of the time digital converter as 40 link lengths, the calibration of the link lengths of 28 to 29 is taken as an example. At this time, the reference clock is received. Since the 28th link and the 29th link need to be detected for calibration, the received reference clock needs to be adjusted to the vicinity of the 28th link, and this adjustment range is the preset phase difference. According to the requirement that the preset phase difference is set to 0 to 3, the reference clock can be adjusted to the 27th link. At this time, the phase adjustment information detected by the time digital converter satisfies the range of 0 to 3, and the reference clock reaches the preset phase.

[0053] After the delay circuit is adjusted, the delay circuit is maintained so that the reference clock in the delay circuit is always at the preset phase, and then the digital time converter is delayed for the first time to the target detection phase one (i.e., delayed to the 28th link position), and the phase information one detected by the time digital converter and the code value information one of the digital time converter corresponding to the phase information one are recorded, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase; then, the delay circuit remains unchanged (the reference clock in the delay circuit is always at the preset phase), and the digital time converter is delayed again to the target detection phase two (i.e., delayed to the 29th link position), and the phase information two detected by the time digital converter and the code value information two of the digital time converter corresponding to the phase information two are recorded, thereby adjusting the digital time converter and the detection benchmark of the time digital converter by delaying the reference clock to the vicinity of the phase to be measured, i.e., the preset phase position, to avoid the problem of inaccurate output value of the time digital converter caused by process deviation, temperature change, unstable power supply voltage, etc.

[0054] On the other hand, when the reference clock delay processing is not performed, the benchmark detected by the time digital converter is the 0th link, that is, when the first delay occurs, the time digital converter detects the phase from the 0th link to the 28th link, and when the delay occurs again, the time digital converter detects the phase from the 0th link to the 29th link; while the present embodiment adjusts the benchmark from the 0th link to the 27th link through the reference clock delay processing, so that when the first delay occurs, the time digital converter detects the phase from the 27th link to the 28th link, and when the delay occurs again, the time digital converter detects the phase from the 27th link to the 29th link. Therefore, compared with not performing the reference clock delay processing, the present embodiment reduces the detection error by adjusting the detection benchmark, so that the output result is more accurate and the error range is smaller, avoiding the problem of instability of the digital time converter, and thus ensuring the accuracy of the calibration result.

[0055] Specifically, when the digital time converter delays the input reference clock for the first time, the detected phase information 1 is marked as phe1, and the code value information 1 corresponding to the digital time converter at this time is recorded, marked as code1; when the digital time converter delays the input reference clock again, the detected phase information 2 is marked as pheN, and the code value information 2 corresponding to the digital time converter is recorded, marked as codeN. Figure 2 It can be understood that the phase information one measured during the first delay is the phase information one detected during the 28th link; the phase information two measured during the second delay is the phase information two detected during the 29th link.

[0056] Further, based on phase information one, code value information one, phase information two and code value information two, the calibration result of the digital time converter is calculated, wherein calculating the calibration result of the digital time converter includes the following steps: calculating the phase information difference between phase information one and phase information two, and calculating the code value information difference between code value information one and code value information two; calculating the calibration result based on the phase information difference and the code value information difference, wherein the calibration result = code value information difference / phase information difference.

[0057] Specifically, the phase information difference is pheN-phe1, the code value information difference is codeN-code1, and the final calibration result is .

[0058] It should be noted that the input range of the reference clock can be flexibly set and adjusted at any time according to actual conditions. Both the frequency and the duty cycle can be changed. When the digital-to-time converter is delayed for the first time, the phase information 1 detected by the time-to-digital converter and the phase information 2 detected by the time-to-digital converter when the digital-to-time converter is delayed again are adjacent phases or non-adjacent phases, which are not further limited in this embodiment.

[0059] On the other hand, the time-to-digital converter can also be measured for differential nonlinearity. In this case, each link is measured according to the above method. Specifically, when the phe of the time-to-digital converter is 1, the corresponding delay information is measured by the digital time converter, and the obtained measurement value (code value information difference) is code1-code0; when the phe of the time-to-digital converter is 2 (the phase information at this time represents the delay between phe1 and phe2, that is, the phase information difference), the corresponding delay information is measured by the digital time converter, and the obtained measurement value is code2-code1; and so on, the delay information of each basic unit of the entire time-to-digital converter is measured by the digital time converter, and then each measured phase information difference is accumulated to obtain the actual delay value of the delay chain length. , and obtain the theoretical delay value of the delay chain length , and then the differential nonlinearity of the time-to-digital converter can be obtained based on the differential nonlinearity formula. The calculation formula is: .

[0060] When measuring the integral nonlinearity of the time-to-digital converter, it can be obtained based on the differential nonlinearity, and its calculation formula is: , N represents the chain length.

[0061] Example 2

[0062] The difference between this embodiment and the first embodiment is that this embodiment performs two reference clock delay processes, that is, performs two detection benchmark adjustments, and the steps are as follows: setting a preset phase difference, and delaying the reference clock in the delay circuit to a preset phase one based on the preset phase difference; keeping the reference clock in the delay circuit at the preset phase one, delaying the digital time converter for the first time to the target detection phase one, and recording the phase information one detected by the time-to-digital converter, and the code value information one of the digital time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one; delaying the reference clock in the delay circuit to a preset phase two based on the preset phase difference; keeping the reference clock in the delay circuit at the preset phase two, delaying the digital time converter again to the target detection phase two, and recording the phase information two detected by the time-to-digital converter, and the code value information two of the digital time converter corresponding to the phase information two, wherein the preset phase difference is also the phase difference between the target detection phase two and the preset phase two; calculating the calibration result of the digital time converter based on the phase information one, the code value information one, the phase information two, and the code value information two.

[0063] Specifically, Figure 3As shown, taking the chain length of the time-to-digital converter as 40 chain lengths, and calibrating the chain lengths of 28-29 as an example, the reference clock is received at this time. Since the 28th link and the 29th link need to be detected before calibration, before the first delay processing is performed, the received reference clock is adjusted to the vicinity of the 28th link in this embodiment. According to the requirement that the preset phase difference is set to 0-3, the reference clock can be adjusted to the 27th link. At this time, the phase adjustment information detected by the time-to-digital converter satisfies the range of 0-3, and the reference clock reaches the preset phase one. Then the delay circuit remains unchanged, so that the reference clock in the delay circuit is always at the preset phase one. Then the digital-to-time converter is delayed for the first time to the target detection phase one (that is, delayed to the position of the 28th link), and the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one are recorded. At this time, the phase information one recorded by the time-to-digital converter is the phase from the 27th link to the 28th link, and the code value information one recorded by the digital-to-time converter is the code value information from the 27th link to the 28th link.

[0064] Next, the reference clock is delayed again in the delay circuit. At this time, since the 29th link needs to be detected, based on the range requirement of the preset phase difference, the reference clock can be delayed to the 28th link so that the reference clock reaches the preset phase two, and the delay circuit is kept unchanged so that the reference clock in the delay circuit is always at the preset phase two. Then the digital time converter is delayed for a second time to the target detection phase two (i.e., delayed to the position of the 29th link), and the phase information two detected by the time digital converter and the code value information two of the digital time converter corresponding to the phase information two are recorded. At this time, the phase information recorded by the time digital converter is the phase from the 28th link to the 29th link, and the code value information two recorded by the digital time converter is the code value information from the 28th link to the 29th link.

[0065] Compared with the first embodiment, this embodiment adjusts the reference from the 0th link to the 27th link and the 28th link respectively through two reference clock delay processes of the delay circuit, so that during the first delay, the time digital converter detects the phase from the 27th link to the 28th link, and during the second delay, the time digital converter detects the phase from the 28th link to the 29th link, so that the detection output value is more accurate and the error range is smaller, avoiding the problem of instability of the digital time converter.

[0066] Example 3

[0067] like Figure 4As shown, a calibration system for a digital-to-time converter comprises a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit; the calibration logic circuit is used to provide a preset phase difference; the delay circuit is used to delay an input reference clock to a preset phase based on the preset phase difference, and keep the state unchanged; the digital-to-time conversion circuit is used to perform multiple delay processing on the input reference clock, so as to delay the input reference clock to a target detection phase one and a target detection phase two, respectively, and obtain code value information one and code value information two, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase; the time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs the first delay processing, and to detect phase information two after the digital-to-time conversion circuit performs the second delay processing; the calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

[0068] Furthermore, the delay circuit delays the reference clock to a preset phase based on a preset phase difference, including the following steps: the delay circuit adjusts the delay information of the reference clock; the time-to-digital conversion circuit detects the phase adjustment information, and when the phase adjustment information reaches the preset phase difference, the delay information of the reference clock reaches the preset phase.

[0069] Furthermore, the calibration logic circuit outputs a calibration result, including the following steps: calculating the phase information difference between phase information one and phase information two, and calculating the code value information difference between code value information one and code value information two; calculating the calibration result based on the phase information difference and the code value information difference, wherein the calibration result = code value information difference / phase information difference.

[0070] Furthermore, phase information one detected by the time-to-digital conversion circuit after the digital-to-time conversion circuit performs a first delay process and phase information two detected by the digital-to-time conversion circuit after the digital-to-time conversion circuit performs a second delay process are adjacent phases or non-adjacent phases.

[0071] Specifically, before calibrating the digital time converter DTC, the phase difference value to be measured must be clearly defined. The phase difference value must be preset in the calibration logic circuit to obtain the preset phase difference. The measured value can be two adjacent phases or a phase between non-adjacent phases. The range of the input reference clock 100 is relatively flexible and can be adjusted at any time. Both the frequency and duty cycle can be changed. The reference clock flows into the digital time conversion circuit and the delay circuit respectively, which will cause the reference clock to generate delayed signals 101 and 102.

[0072] In order to ensure that the phase difference to be measured is the preset phase difference, the calibration logic circuit first sends a control signal 104 to the delay circuit to generate an expected delay, so that it delays the reference clock to the preset phase. The time-to-digital conversion circuit detects the phase information 103 to ensure that the delay information generated by the delay circuit is accurate. After that, the calibration logic circuit no longer sends information to the delay circuit, and the state of the delay circuit remains unchanged.

[0073] Secondly, the calibration logic circuit sends information 105 to the digital time conversion circuit to start it working. The control code of the digital time conversion circuit is the thermometer code. The phase information one detected by the time digital conversion circuit for the first time is recorded as phe1. At this time, the calibration logic circuit will record the code value information one code1 corresponding to the digital time conversion circuit at this time; the phase information two detected for the second time is recorded as phe2. At this time, the calibration logic circuit will record the code value information two code2 corresponding to the digital time conversion circuit at this time; the phase information N detected for the Nth time is recorded as pheN. At this time, the calibration logic circuit will record the code value information N corresponding to the digital time conversion circuit at this time as codeN. In this embodiment, the relevant data information of the second detection and the Nth detection can be understood as the data obtained after the detection after the delay processing again.

[0074] Finally, the difference between the code value information of the digital time conversion circuit is calculated as codeN-code1 and recorded as The phase information difference is pheN-phe1, which is recorded as , so the calibration logic circuit calculates and outputs the calibration result of the digital time conversion circuit as 106, and the calibration value calculated by it is: .

[0075] Since the calibration system of the digital-to-time converter of this embodiment executes the calibration method of the digital-to-time converter shown in the first embodiment, it will not be described again in this embodiment.

[0076] Example 4

[0077] like Figure 4As shown, a calibration system for a digital-to-time converter includes a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit, and a time-to-digital conversion circuit; the calibration logic circuit is used to provide a preset phase difference; the delay circuit is used to delay an input reference clock to a preset phase one and a preset phase two based on the preset phase difference; the digital-to-time conversion circuit is used to perform a first delay processing on the input reference clock after the delay circuit delays the input reference clock to the preset phase one, so as to delay the input reference clock to the target detection phase one and obtain code value information one; after the delay circuit delays the input reference clock to the preset phase two, the input reference clock is delayed again Processing is performed to delay the input reference clock to target detection phase two to obtain code value information two, wherein the preset phase difference is the phase difference between target detection phase one and preset phase one, and the preset phase difference is also the phase difference between target detection phase two and preset phase two; the time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs the first delay processing, and to detect phase information two after the digital-to-time conversion circuit performs the second delay processing; the calibration logic circuit is also used to output the calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

[0078] The difference between this embodiment and implementation three is that the delay circuit of this embodiment performs two reference clock delay processes, thereby further improving the accuracy of calibration. Since this embodiment implements the calibration method of the digital-to-time converter of implementation two, it will not be repeated here.

[0079] The above is only a preferred embodiment of the present invention, and is not any formal or substantial limitation of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and supplements without departing from the method of the present invention, and these improvements and supplements should also be regarded as the protection scope of the present invention. Any technician familiar with this profession, without departing from the spirit and scope of the present invention, can make some changes, modifications and evolutions of the technical content disclosed above, which are equivalent embodiments of the present invention; at the same time, any changes, modifications and evolutions of any equivalent changes made to the above embodiments based on the essential technology of the present invention are still within the scope of the technical solution of the present invention.

Claims

1. A method for calibrating a digital-to-time converter, characterized in that: The following steps are involved: Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase based on the preset phase difference; Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase, and the range of the preset phase difference is 0 to 3 phases; Keep the reference clock of the delay circuit at a preset phase, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2; Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated.

2. The calibration method of a digital-to-time converter according to claim 1, characterized in that: Delaying the reference clock to a preset phase based on the preset phase difference comprises the following steps: Adjusting the delay information of the reference clock and detecting the phase adjustment information of the time-to-digital converter; When the phase adjustment information reaches a preset phase difference, the reference clock is adjusted according to the delay information when the preset phase difference is reached and reaches a preset phase.

3. The calibration method of a digital-to-time converter according to claim 1, characterized in that: Calculating the calibration result of the digital-to-time converter includes the following steps: Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2; A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference / phase information difference.

4. A method for calibrating a digital-to-time converter according to any one of claims 1 to 3, characterized in that: When the digital-to-time converter performs the first delay, the phase information one detected by the time-to-digital converter is an adjacent phase or a non-adjacent phase, and when the digital-to-time converter performs the second delay, the phase information two detected by the time-to-digital converter is an adjacent phase or a non-adjacent phase.

5. A method for calibrating a digital-to-time converter, characterized in that: The following steps are involved: Setting a preset phase difference, and delaying a reference clock of a delay circuit to a preset phase one based on the preset phase difference; Keep the reference clock of the delay circuit at the preset phase one, delay the digital-to-time converter for the first time to the target detection phase one, and record the phase information one detected by the time-to-digital converter and the code value information one of the digital-to-time converter corresponding to the phase information one, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one; Delaying the reference clock of the delay circuit to a preset phase two based on the preset phase difference; Keep the reference clock of the delay circuit at the preset phase 2, delay the digital-to-time converter again to the target detection phase 2, and record the phase information 2 detected by the time-to-digital converter and the code value information 2 of the digital-to-time converter corresponding to the phase information 2, wherein the preset phase difference is also the phase difference between the target detection phase 2 and the preset phase 2; Based on the phase information one, the code value information one, the phase information two and the code value information two, a calibration result of the digital-to-time converter is calculated.

6. A calibration system for a digital-to-time converter, characterized in that: The calibration system of the digital-to-time converter performs the calibration method of the digital-to-time converter as claimed in any one of claims 1 to 4, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit; The calibration logic circuit is used to provide a preset phase difference; The delay circuit is used to delay the input reference clock to a preset phase based on the preset phase difference; The digital time conversion circuit is used to perform multiple delay processing on the input reference clock to delay the input reference clock to target detection phase 1 and target detection phase 2 respectively, and obtain code value information 1 and code value information 2, wherein the preset phase difference is the phase difference between the target detection phase 1 and the preset phase; The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process; The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

7. A calibration system for a digital-to-time converter according to claim 6, characterized in that: The delay circuit delays the reference clock to a preset phase based on the preset phase difference, comprising the following steps: The delay circuit adjusts the delay information of the reference clock; The time-to-digital conversion circuit detects phase adjustment information, and when the phase adjustment information reaches a preset phase difference, the delay information of the reference clock reaches a preset phase.

8. The calibration system for a digital-to-time converter according to claim 6, characterized in that: The calibration logic circuit outputs the calibration result, comprising the following steps: Calculating a phase information difference between the phase information 1 and the phase information 2, and calculating a code value information difference between the code value information 1 and the code value information 2; A calibration result is calculated based on the phase information difference and the code value information difference, wherein the calibration result=code value information difference / phase information difference.

9. A calibration system for a digital-to-time converter, characterized in that: The calibration system of the digital-to-time converter performs the calibration method of the digital-to-time converter as claimed in claim 5, comprising a calibration logic circuit, a digital-to-time conversion circuit, a delay circuit and a time-to-digital conversion circuit; The calibration logic circuit is used to provide a preset phase difference; The delay circuit is used to delay the input reference clock to a preset phase one and a preset phase two respectively based on the preset phase difference; The digital time conversion circuit is used to perform a first delay process on the input reference clock after the delay circuit delays the input reference clock to the preset phase one, so as to delay the input reference clock to the target detection phase one, and obtain code value information one; after the delay circuit delays the input reference clock to the preset phase two, perform a second delay process on the input reference clock, so as to delay the input reference clock to the target detection phase two, and obtain code value information two, wherein the preset phase difference is the phase difference between the target detection phase one and the preset phase one, and the preset phase difference is also the phase difference between the target detection phase two and the preset phase two; The time-to-digital conversion circuit is used to detect phase information one after the digital-to-time conversion circuit performs a first delay process, and to detect phase information two after the digital-to-time conversion circuit performs a second delay process; The calibration logic circuit is also used to output a calibration result based on phase information one, phase information two, code value information one corresponding to phase information one, and code value information two corresponding to phase information two.

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