A chip architecture integrating heterogeneous processors shared memory, a chip and a design method thereof

Abstract

The present invention discloses a chip architecture, a chip and a design method thereof for integrating heterogeneous processor shared memory, including a CPU, a GPU, a memory unit, and a processor port, a memory processing unit and a network data processing unit arranged based on a Crossbar structure, so as to realize data exchange through the Crossbar structure; the CPU and the GPU are connected to the corresponding processor ports; the memory unit includes a proximal memory, an intermediate memory and a distal memory, the proximal memory is connected to the CPU and the GPU, the intermediate memory is connected to the corresponding memory processing unit, and the distal memory is arranged on a network device and connected to the corresponding network data processing unit; the CPU and the GPU can access the intermediate memory and the distal memory through the Crossbar structure. In the chip architecture of the present invention, in addition to the exclusive proximal memory, the processor can share access to the intermediate memory or the distal memory to support the memory space required for large model operations.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuits, and in particular to a chip architecture integrating heterogeneous processors with shared memory, a chip and a design method thereof. Background Art

[0002] With the development of science and technology, the application of artificial intelligence is becoming more and more extensive, and the training of large artificial intelligence models requires a large amount of memory space and efficient data processing capabilities. Therefore, the importance of chip design architecture in the field of artificial intelligence is becoming increasingly prominent. That is, designing a chip architecture that can meet the needs of a large amount of memory space while reducing memory access latency has become an important research direction.

[0003] In addition, microelectronic packaging technology and high-speed network communication equipment are also important factors affecting chip performance, that is, the chip design architecture, microelectronic packaging technology and high-speed network communication equipment design and manufacturing level directly affect the performance and cost of the product.

[0004] The existing chip design architecture is mainly based on the central processing unit (CPU) as the core, and various functional modules are connected through a bus structure. This architecture can meet basic computing needs to a certain extent, but with the emergence of large artificial intelligence models, the demand for memory space and data processing capabilities is increasing, and the existing chip design architecture is increasingly unable to meet these needs.

[0005] In addition, the existing chip design architecture has problems of high latency, high energy consumption, and high design and manufacturing costs when faced with large-scale data processing and memory access.

[0006] The disclosure of the above background technology content is only used to assist in understanding the concept and technical solution of the present application. It does not necessarily belong to the prior art of the present application, nor does it necessarily provide technical guidance. In the absence of clear evidence that the above content has been disclosed before the filing date of the present application, the above background technology should not be used to evaluate the novelty and creativity of the present application. Summary of the invention

[0007] The purpose of the present invention is to provide an improved chip architecture, in which, in addition to exclusive proximal memory, the processor can share access to intermediate memory or remote memory to support the memory space required for large model operations.

[0008] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0009] A chip architecture integrating heterogeneous processors with shared memory, including a CPU, a GPU, a memory unit, and multiple processor ports, one or more memory processing units, and a network data processing unit arranged based on a Crossbar structure, wherein the processor ports, the memory processing unit, and the network data processing unit exchange data through the Crossbar structure;

[0010] Wherein, the CPU and GPU are connected to corresponding processor ports;

[0011] The memory unit includes a proximal memory, an intermediate memory and a distal memory, wherein the proximal memory is connected to the CPU and the GPU, the intermediate memory is connected to the corresponding memory processing unit, and the distal memory is arranged on the network device and connected to the corresponding network data processing unit;

[0012] The CPU and the GPU are both configured to access the intermediate level memory and the remote memory through the Crossbar structure.

[0013] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions described above, the number allocation of processor ports, memory processing units and network data processing units is adjusted according to the multi-port structure of the Crossbar structure.

[0014] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the processor port includes at least one PCIe port and multiple communication protocol ports, wherein the PCIe port is connected to the CPU, and the communication protocol port is connected to the GPU in a one-to-one correspondence.

[0015] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the proximal memory includes a proximal DDR memory and a proximal HBM memory, wherein the proximal DDR memory is connected to the CPU, and the proximal HBM memory is connected to the GPU in a one-to-one correspondence.

[0016] Further, based on any one of the technical solutions or a combination of multiple technical solutions described above, the intermediate-level memory includes an intermediate-level DDR memory and an intermediate-level HBM memory, some memory processing units are connected to the intermediate-level DDR memory, and the remaining memory processing units are connected to the intermediate-level HBM memory.

[0017] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the memory processing unit includes one or more DDR controllers and one or more HBM controllers, wherein the DDR controller is connected to the intermediate-level DDR memory, and the HBM controller is connected to the intermediate-level HBM memory.

[0018] Further, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the DDR controller is connected to the intermediate-level DDR memory through a PCIe bus, and the HBM controller is connected to the intermediate-level HBM memory through a communication protocol bus.

[0019] Furthermore, based on any one of the technical solutions or a combination of multiple technical solutions mentioned above, the remote memory is configured on an Ethernet device or an Infiniband device according to the network communication mode of the network data processing unit.

[0020] According to another aspect of the present invention, there is provided a chip integrating heterogeneous processors with shared memory, comprising a plurality of processor ports, one or more memory processing units and a network data processing unit arranged based on a Crossbar structure, wherein the processor ports, the memory processing unit and the network data processing unit exchange data through the Crossbar structure;

[0021] The processor port is configured to be connected to the CPU and the GPU respectively;

[0022] The memory processing unit is configured to be connected to the intermediate level memory;

[0023] The network data processing unit is configured to be connected to a network device;

[0024] The CPU and the GPU are both configured to be able to access the intermediate level memory through the Crossbar structure.

[0025] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the network device connected to the network data processing unit is configured with a remote memory;

[0026] The CPU and the GPU are both configured to access the remote memory through the Crossbar structure.

[0027] According to another aspect of the present invention, a chip architecture design method for integrating processor shared memory is provided, comprising the following steps:

[0028] Build Crossbar as a data exchange center to enable data exchange between the processor port and the memory processing unit through Crossbar;

[0029] Connecting the processor port to the processor, and connecting the memory processing unit to the intermediate level memory;

[0030] The processor is configured to be able to access the intermediate level memory through a Crossbar.

[0031] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the chip architecture design method provided by the present invention also includes:

[0032] Add a network data processing unit so that it can interact with the processor port and memory processing unit through Crossbar;

[0033] Connecting the network data processing unit to a network device, wherein the network device is configured with a remote memory;

[0034] The processor is configured to be able to access the remote memory through Crossbar.

[0035] Further, based on any one of the above-mentioned technical solutions or a combination of multiple technical solutions, the chip architecture design method provided by the present invention also includes:

[0036] Designing the processor to be a heterogeneous processor including a CPU and a GPU;

[0037] Configuring the number of the processor ports to be plural so as to be connected to one or more CPUs and GPUs in a one-to-one correspondence;

[0038] And configure a proximal memory corresponding to the CPU and GPU one by one;

[0039] When the proximal memory is smaller than the current memory space requirement, the corresponding processor sends a request to Crossbar to access the intermediate memory and / or the remote memory.

[0040] The beneficial effects brought by the technical solution provided by the present invention are as follows:

[0041] a. Provide a simple and easy-to-implement chip design architecture centered on data exchange functions. This architecture uses a multi-port Crossbar structure to provide extremely low-latency data exchange, ensure the smoothness of data exchange, and greatly reduce the latency of memory access during operations of heterogeneous processors;

[0042] b. Integrate and expand the shared memory function: In addition to the dedicated near-end memory in the chip architecture, the processor can share access to the intermediate memory or remote memory to support the memory space required for large model operations;

[0043] c. Provide an improved chip architecture suitable for heterogeneous processors, changing the traditional CPU-centric architecture to a GPU processor that focuses on computing power, adapting to large-scale data processing and ensuring the stability of the overall system;

[0044] d. Based on the concept of System on Chip, the chip architecture is miniaturized to a high-density system-level chip, which has important practical value for power-sensitive system equipment: a single package structure can control the delay of data exchange, reduce the operating costs caused by the high power consumption derived from a large number of calculations in the artificial intelligence computing center, and also help improve the performance and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0046] Figure 1 A schematic diagram of the structure of a Crossbar data exchange center provided for an exemplary embodiment of the present invention;

[0047] Figure 2 A schematic diagram of a chip architecture provided for an exemplary embodiment of the present invention;

[0048] Figure 3 A schematic diagram of a multi-level memory architecture provided for an exemplary embodiment of the present invention;

[0049] Figure 4 A flow chart of a chip architecture design method provided for an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, device, product or equipment that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0052] The present invention aims to provide an improved chip design architecture centered on data exchange function, which utilizes a multi-port Crossbar structure to provide extremely low-latency data exchange.

[0053] In one embodiment of the present invention, a chip architecture integrating heterogeneous processors with shared memory is provided, including a CPU, a GPU, a memory unit, and a plurality of processor ports, one or more memory processing units, and a network data processing unit arranged based on a Crossbar structure, wherein the processor ports, the memory processing unit, and the network data processing unit exchange data through a Crossbar structure; the Crossbar structure is as follows: Figure 1 As shown, the Crossbar structure is an efficient switching structure widely used in the computer field, that is, to achieve efficient data routing and switching between multiple ports: data enters from the input port and is routed to the corresponding output port through the switch matrix. Figure 1 The 4×3 switch matrix is ​​for illustration only. The present invention does not limit the number of switches in the switch matrix in the Crossbar, that is, the number of ports / processing units connected thereto is not limited. Figure 1 The ports / processing units in the embodiment refer to the processor ports, memory processing units, and network data processing units in this embodiment.

[0054] In a specific embodiment, Figure 2 The Crossbar structure shown has 16 ports and can use a 4×4 switch matrix. Figure 2 The chip architecture shown is used as an example to illustrate:

[0055] In this architecture, the ports / processing units of the 16 Crossbars are 8 processor ports (1 PCIe port, 7 communication protocol ports), 4 memory processing units (2 DDR controllers, 2 HBM controllers), and 4 network data processing units; obviously, in different embodiments, the number of PCIe ports, communication protocol ports, DDR controllers, HBM controllers, and network data processing units can be adjusted and allocated differently.

[0056] Although Figure 2 The figure shows that only one of the eight processor ports is connected to the CPU processor, and the remaining seven are connected to the GPU processor. This is just a schematic diagram and does not limit the number or proportion. However, this embodiment embodies a newly evolved chip architecture with GPU processors as the core, which is mainly based on computing power, by having more GPUs than CPUs, replacing the traditional chip architecture with CPU as the core. This makes the newly evolved chip architecture of this embodiment more adaptable to the computing power requirements of large artificial intelligence models, and alleviates the high latency problem that occurs in the traditional CPU-based architecture when processing large-scale data. Compared with this, the chip architecture of this embodiment has higher data processing efficiency.

[0057] The connection relationship between the chip's Crossbar structure and the processor and memory unit outside the chip is as follows:

[0058] The CPU and GPU are connected to the corresponding processor ports: the CPU is connected to the PCIe port, and the GPU is connected to the communication protocol port in a one-to-one correspondence; in this embodiment, the communication protocol can adopt a public protocol or a private protocol as the basis for performing memory access operations to ensure the reliability and efficiency of data transmission;

[0059] The memory unit includes proximal memory, intermediate memory and distal memory. Among them, the proximal memory has the shortest latency and is called Level 1 memory. Figure 3 As shown, the proximal memory includes a proximal DDR memory and a proximal HBM memory, wherein the proximal DDR memory is connected to the CPU, and the proximal HBM memory is connected to the GPU in a one-to-one correspondence;

[0060] The intermediate memory has the second highest latency, which is called Level 2 memory, and is connected to the corresponding memory processing unit, such as Figure 3 As shown, according to the memory processing unit, it is divided into a DDR controller and an HBM controller. Correspondingly, the intermediate-level memory includes an intermediate-level DDR memory and an intermediate-level HBM memory. The DDR controller is connected to the intermediate-level DDR memory through a PCIe bus, and the HBM controller is connected to the intermediate-level HBM memory through a communication protocol bus.

[0061] The remote memory is set on the network device, and the network device is connected to the corresponding network data processing unit; the remote memory has the longest latency and is called Level 3 memory. The network data processing unit has the ability of remote direct memory access (RDMA). If the network data processing unit adopts the RDMA onEthernet communication method, the remote memory is configured on the Ethernet device; if the network data processing unit adopts the RDMA onInfiniband communication method, the remote memory is configured on the Infiniband device.

[0062] Based on the connection between the Crossbar structure and the memory unit, the CPU and GPU are configured to access the intermediate memory and the remote memory through the Crossbar structure. The first scenario is as follows Figure 4 As shown: when the memory space requirement is greater than the proximal memory, or when data needs to be exchanged through shared memory, the corresponding processor (CPU / GPU) sends a request for sharing the intermediate-level memory to Crossbar. For example, according to the latency priority, it first requests access to the intermediate-level memory of Level 2. Through a computer table lookup, it can be determined that there is an idle intermediate-level memory Y, which can be successfully accessed by the processor that sent the sharing request to meet the large memory space requirement; in this case, if the processor is a CPU / GPU, the corresponding PCIe port / communication protocol port is the input port of Crossbar, and the DDR controller / HBM controller corresponding to the idle intermediate memory is the output port of Crossbar, and then the switch on the path used to conduct the two in the switch matrix is ​​controlled to be closed, so as to realize the bidirectional conduction of the path from the processor to the intermediate-level memory Y, and finally realize the sharing of the intermediate-level memory Y by the processor.

[0063] Continue to see Figure 4 If it is in a communication scenario, the processor requests to write data to the remote memory so that the data can be further sent to the outside through the network device. In this case, the processor first writes the data to the intermediate memory in an idle state, and then moves the data from the intermediate memory to the remote memory, that is, firstly through a computer table lookup, it can be determined that there is an intermediate memory Z in an idle state, and then the switch on the path between the processor and the intermediate memory Z in the switch matrix of the Crossbar is closed, and then the processor completes the data writing; then the switch on the path between the intermediate memory Z and the remote memory in the switch matrix of the Crossbar is controlled to be closed, so that the written data is moved from the intermediate memory Z to the remote memory.

[0064] The above is a scenario where the processor requests to write data. Another scenario is based on communication requirements and needs to read data in remote memory. The process is as follows: Figure 4 As shown, if the required data is stored in the remote shared memory (i.e., the remote memory of Level 3), the data can be moved to the near shared memory (i.e., the intermediate memory of Level 2) by RDMA: first, the intermediate memory X in an idle state can be determined by looking up a table on a computer, and then the switch on the path between the remote memory and the intermediate memory X in the switch matrix of the Crossbar is controlled to be closed, so that the data is moved from the remote memory to the intermediate memory X, and then the switch on the path between the processor and the intermediate memory X in the switch matrix of the Crossbar is controlled to be closed, so as to finally realize the processor's sharing of the remote memory and reduce the delay of data access.

[0065] The chip architecture of this embodiment can meet the needs of a large amount of memory space when running a large artificial intelligence model, and the memory can be flexibly expanded according to demand; and the priority level of expanded memory can be determined according to the latency to shorten the latency of accessing the expanded memory and improve performance.

[0066] This embodiment can adopt a low-power design concept and further integrate the chip architecture into a high-density SoC (System on Chip), which can appropriately reduce the operating costs caused by the high power consumption derived from a large number of calculations in the artificial intelligence computing center, and is also beneficial to improving the performance and stability of the system. And because it is integrated into a single package structure, the delay of data exchange can be controlled, which is impossible with the existing discrete architecture. In the manufacturing process, advanced microelectronic packaging technology, such as chiplet or 3D packaging, or in a single-chip manner, is used to reduce the manufacturing cost of the chip, which is also beneficial to improving the performance and stability of the chip.

[0067] In one embodiment of the present invention, a chip integrating heterogeneous processors with shared memory is provided, comprising a plurality of processor ports, one or more memory processing units and a network data processing unit arranged based on a Crossbar structure, wherein the processor ports, the memory processing unit and the network data processing unit exchange data through the Crossbar structure;

[0068] Compared with the chip architecture provided in the previous embodiment, the chip of this embodiment does not include a processor (CPU, GPU), a memory unit (near-end memory, intermediate-level memory, and far-end memory), and a network device.

[0069] The chip of this embodiment that integrates heterogeneous processors to share memory has the same concept as the chip architecture provided in the above-mentioned embodiment, that is, the processor accesses other external memories that are not exclusive to itself through the port of the crossbar structure of the chip, that is, memory sharing is realized, which effectively solves the demand for a large amount of memory space for large-scale artificial intelligence model training or other scenarios.

[0070] The processor port of the crossbar structure of the chip of this embodiment is configured to be connected to the CPU and GPU respectively; the memory processing unit is configured to be connected to the intermediate memory; the network data processing unit is configured to be connected to the network device, and the network device is configured with a remote memory;

[0071] The CPU and the GPU are both configured to access the intermediate level memory and / or the remote memory through the Crossbar structure.

[0072] In one embodiment of the present invention, a chip architecture design method for integrating processor shared memory is provided, and the chip architecture design method comprises the following steps:

[0073] Build Crossbar as a data exchange center to enable data exchange between the processor port and the memory processing unit through Crossbar;

[0074] Connecting the processor port to the processor, and connecting the memory processing unit to the intermediate level memory;

[0075] The processor is configured to access the intermediate memory via Crossbar, as follows: Figure 4 As shown, when the memory space requirement is greater than the proximal memory, or when data needs to be exchanged through the shared memory (requesting to read or write data to the remote memory), the corresponding processor sends a request to Crossbar to access the intermediate memory. As in the above chip architecture embodiment, if an idle intermediate memory is traversed, the switch on the path between the processor port corresponding to the processor in the switch matrix of Crossbar and the memory processing unit corresponding to the idle intermediate memory is controlled to be closed, so that the processor can share the intermediate memory.

[0076] The network data processing unit can be further designed so that it can interact with the processor port and the memory processing unit through the Crossbar;

[0077] Connecting the network data processing unit to a network device, wherein the network device is configured with a remote memory;

[0078] The processor is configured to be able to access the remote memory through Crossbar. Specifically, when the exclusive proximal memory of the processor is smaller than the current memory space requirement, the corresponding processor sends a request to Crossbar to access the remote memory. As in the above chip architecture embodiment, if a remote memory in an idle state is traversed, the switch on the path between the processor port corresponding to the processor in the switch matrix of Crossbar and the network data processing unit corresponding to the idle remote memory is controlled to be closed, so that the processor can share the terminal memory.

[0079] When both the intermediate-level memory and the remote memory are idle, the intermediate-level memory with the shorter shared latency can be selected first.

[0080] The chip architecture design method provided above is applicable to heterogeneous processors including CPUs and GPUs; accordingly, the number of the processor ports is configured to be plural, so as to be connected to one or more CPUs and GPUs in a one-to-one correspondence; and the proximal memory is configured to correspond to the CPUs and GPUs in a one-to-one correspondence;

[0081] When the proximal memory is smaller than the current memory space requirement, the corresponding processor sends a request to Crossbar to access the intermediate memory and / or the remote memory.

[0082] The chip architecture, chip and design method for integrating heterogeneous processors with shared memory provided by the present invention are suitable for artificial intelligence applications, big data processing, high-performance computing, network communication equipment and other fields. First, the chip architecture of the present invention can effectively solve the demand for a large amount of memory space when training large artificial intelligence models, and improve the efficiency of artificial intelligence applications; secondly, the chip architecture of the present invention can greatly reduce the latency of memory access, improve the efficiency of big data processing, and meet the needs of high-performance computing; thirdly, the chip architecture of the present invention can improve the data transmission efficiency of network communication equipment through RDMA technology, and meet the needs of high-speed network communication; finally, the chip design architecture of the present invention can reduce the design and manufacturing costs, and is suitable for being set up in a data center or the backbone network layer of cloud computing. Because of the structure of Crossbar to achieve fast data exchange, the computing center can adapt to different computing power requirements and flexibly increase or decrease the number of GPUs in the rack without affecting the computing performance; external DDR / HBM can be used to provide additional required memory space; if there are resources on the network, the network data processing unit can also be used to connect to the regional network to obtain the required data.

[0083] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0084] The above is only a specific implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A chip architecture integrating heterogeneous processors with shared memory, characterized in that: It includes a CPU, a GPU, a memory unit, and multiple processor ports, one or more memory processing units, and a network data processing unit arranged based on a Crossbar structure. The processor ports, the memory processing unit, and the network data processing unit exchange data through the same Crossbar structure. The processor ports, the memory processing unit, the network data processing unit, and a single Crossbar structure constitute a chip integrating heterogeneous processors with shared memory. Wherein, the CPU and GPU are connected to corresponding processor ports; The memory unit includes a proximal memory, an intermediate memory and a remote memory, wherein the proximal memory is connected to the CPU and the GPU, each CPU is directly connected to the proximal memory outside the Crossbar structure, and each GPU is directly connected to the proximal memory outside the Crossbar structure; the intermediate memory is connected to the corresponding memory processing unit, and the remote memory is set on the network device and connected to the corresponding network data processing unit; The CPU and the GPU are both configured to access the intermediate memory and the remote memory through the Crossbar structure, and the GPU does not access the intermediate memory and the remote memory through the CPU; When the memory space requirement is greater than the proximal memory, the CPU / GPU sends a request to Crossbar to share the intermediate memory, and determines that there is an idle intermediate memory Y through a computer table lookup, then the processor port corresponding to the CPU / GPU is used as the Crossbar input port, and the memory processing unit corresponding to the intermediate memory Y is used as the Crossbar output port, and the switch on the path for connecting the input port and the output port in the switch matrix of Crossbar is controlled to be closed; When the CPU / GPU requests to write data to the target remote memory, the CPU / GPU first writes the data to the idle intermediate memory Z through the Crossbar structure, and then controls the switch on the path between the intermediate memory Z and the target remote memory in the switch matrix of the Crossbar to close, so that the data written to the intermediate memory Z is transmitted to the target remote memory; When the CPU / GPU requests to read data in the target remote memory, the data is first transmitted to the idle intermediate memory X through the Crossbar structure by RDMA, and then the switch on the path between the intermediate memory X and the CPU / GPU in the Crossbar switch matrix is ​​controlled to be closed, so that the CPU / GPU can read the data temporarily stored in the intermediate memory X.

2. The chip architecture according to claim 1, characterized in that: The number allocation of processor ports, memory processing units and network data processing units is adjusted according to the multi-port structure of the Crossbar structure.

3. The chip architecture according to claim 1, characterized in that: The processor port includes at least one PCIe port and a plurality of communication protocol ports, wherein the PCIe port is connected to the CPU, and the communication protocol ports are connected to the GPU in a one-to-one correspondence.

4. The chip architecture according to claim 3, characterized in that: The proximal memory includes a proximal DDR memory and a proximal HBM memory, wherein the proximal DDR memory is connected to the CPU, and the proximal HBM memory is connected to the GPU in a one-to-one correspondence.

5. The chip architecture according to claim 1, characterized in that: The intermediate-level memory includes an intermediate-level DDR memory and an intermediate-level HBM memory. Some memory processing units are connected to the intermediate-level DDR memory, and the remaining memory processing units are connected to the intermediate-level HBM memory.

6. The chip architecture according to claim 5, characterized in that: The memory processing unit includes one or more DDR controllers and one or more HBM controllers, wherein the DDR controller is connected to the intermediate-level DDR memory, and the HBM controller is connected to the intermediate-level HBM memory.

7. The chip architecture according to claim 6, characterized in that: The DDR controller is connected to the intermediate-level DDR memory via a PCIe bus, and the HBM controller is connected to the intermediate-level HBM memory via a communication protocol bus.

8. The chip architecture according to claim 1, characterized in that: The remote memory is configured on an Ethernet device or an Infiniband device according to the network communication mode of the network data processing unit.

9. A chip integrating heterogeneous processors with shared memory, used to construct the chip architecture as claimed in any one of claims 1 to 8, characterized in that: It includes multiple processor ports, one or more memory processing units and a network data processing unit arranged based on a Crossbar structure, wherein the processor ports, the memory processing unit and the network data processing unit exchange data through the same Crossbar structure; The processor port is configured to be connected to the CPU and the GPU respectively; The memory processing unit is configured to be connected to the intermediate level memory; The network data processing unit is configured to be connected to a network device; The CPU and the GPU are both configured to access the intermediate-level memory through the Crossbar structure, and the GPU does not access the intermediate-level memory through the CPU.

10. The chip according to claim 9, characterized in that: The network device connected to the network data processing unit is configured with a remote memory; The CPU and the GPU are both configured to access the remote memory through the Crossbar structure, and the GPU does not access the remote memory through the CPU.

11. A method for designing a chip architecture integrating processor shared memory, used for designing a chip architecture as claimed in any one of claims 1 to 8, characterized in that: The following steps are involved: Build Crossbar as a data exchange center to enable data exchange between the processor port and the memory processing unit through Crossbar; Connecting the processor port to the processor, and connecting the memory processing unit to the intermediate level memory; The processor is configured to be able to access the intermediate level memory through a Crossbar.

12. The chip architecture design method according to claim 11, characterized in that: Also includes: Add a network data processing unit so that it can interact with the processor port and memory processing unit through Crossbar; Connecting the network data processing unit to a network device, wherein the network device is configured with a remote memory; The processor is configured to be able to access the remote memory through Crossbar.

13. The chip architecture design method according to claim 11, characterized in that: Also includes: Designing the processor to be a heterogeneous processor including a CPU and a GPU; Configuring the number of the processor ports to be plural so as to be connected to one or more CPUs and GPUs in a one-to-one correspondence; And configure a proximal memory corresponding to the CPU and GPU one by one; When the proximal memory is smaller than the current memory space requirement, the corresponding processor sends a request to Crossbar to access the intermediate memory and / or the remote memory.

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