A probe card partitioning layout method and system for testing circuit die

Abstract

The present invention discloses a method and system for dividing and laying out a probe card for a test circuit die, which is used in the field of circuit testing. The method comprises the following steps: using simulation technology to simulate the correspondence between probes and contact points of the test circuit die for a preset probe card layout covering all test points; constructing a test hierarchy for different test requirements, and dividing the probe card layout according to the test hierarchy; using the test hierarchy to test the test circuit die, and identifying the distribution location and fault type of defective products; designing dense probe test points based on the adjusted probe card layout; using a path optimization algorithm to calculate the optimal test path based on the dense probe test points; and obtaining the final probe card layout. The present invention can deeply understand the behavior and potential problems of the circuit die from multiple dimensions by extracting spatial features from the test data using a convolutional neural network model, combined with the time-varying features captured by a recurrent neural network model.

Description

Technical Field

[0001] The present invention relates to the field of circuit testing, and in particular to a method and system for dividing and laying out a probe card for testing a circuit die. Background Art

[0002] The probe card is a key component in the semiconductor manufacturing test process. It is an interface device used to perform electrical testing at the wafer level before the chip is cut and packaged. Its main function is to provide a precise, physical connection point so that the test equipment can transmit electrical signals to each chip on the wafer for functional verification and performance evaluation. The design and quality of the probe card are critical to ensuring the accuracy and efficiency of the test. Testing circuit dies usually involves a series of complex and precise steps to ensure that the circuit dies meet all design and performance specifications.

[0003] With the development of test circuit technology, test circuit devices for more advanced applications tend to have more pins. Whether it is a traditional test circuit or a test circuit using 3D or 2.5D technology, they usually have a large number of pins. When testing these test circuits with a large number of pins, the number of pins of the test equipment becomes a major bottleneck limiting the test capability of the test circuit.

[0004] Existing testing methods often cannot ensure comprehensive coverage of all key performance indicators of the circuit die, resulting in missing key failure points, affecting product quality and performance. Due to the lack of effective test path optimization and probe card layout design, traditional testing methods will lead to excessively long testing time. There are a large number of unnecessary repeated tests and movements during the testing process, which reduces test efficiency. Existing testing methods and layout designs fail to maximize the use of limited testing resources such as time, equipment and manpower, resulting in unnecessary increase in testing costs. Due to the lack of efficient data analysis and fault identification technology, existing technologies find it difficult to deeply understand the behavior and potential problems of circuit dies from multiple dimensions, and the accuracy of fault identification is limited. Traditional testing methods often lack sufficient flexibility in design, making it difficult to adapt to different testing needs and conditions, as well as to adapt to the development of future technologies, limiting their scope of application and effectiveness.

[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0006] In order to overcome the above problems, the present invention aims to propose a probe card division layout method and system for testing circuit die, with the aim of solving the problems that the prior art is difficult to deeply understand the behavior and potential problems of circuit die from multiple dimensions, the accuracy of fault identification is limited, and traditional testing methods often lack sufficient flexibility in design, making it difficult to adapt to different testing requirements and conditions, and difficult to adapt to the development of future technologies, which limits their scope of application and effectiveness.

[0007] To this end, the specific technical solution adopted by the present invention is as follows:

[0008] According to one aspect of the present invention, a probe card partition layout method for testing circuit dies is provided, the probe card partition layout method comprising the following steps:

[0009] S1, using simulation technology to simulate the correspondence between the probes and the contact points of the test circuit die for the preset probe card layout covering all test points;

[0010] S2. Construct test levels for different test requirements and divide the probe card layout according to the test levels;

[0011] S3, using the test hierarchy to test the test circuit die, mark defective products, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results;

[0012] S4. Based on the adjusted probe card layout, mark the functional areas or high-failure areas and design dense probe test points;

[0013] S5, using a path optimization algorithm to calculate an optimal test path based on dense probe test points;

[0014] S6. Analyze the layout effect of the dense probe test points and the path optimization results of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout.

[0015] Optionally, using simulation technology to simulate the correspondence between probes and contact points of the test circuit die for a preset probe card layout covering all test points includes the following steps:

[0016] S11, marking all test points according to the performance indicators of the test circuit die;

[0017] S12, design the probe card layout to cover all test points on the test circuit die;

[0018] S13. Use electronic simulation tools to simulate the electrical and physical correspondence between the probes and the contact points of the test circuit die, perform simulation analysis on the probe card layout, and verify the probe card layout.

[0019] Optionally, constructing test levels for different test requirements and dividing the probe card layout according to the test levels includes the following steps:

[0020] S21, collecting all test requirements of the test circuit die;

[0021] S22. Classify the test requirements and determine the test level according to different test requirements;

[0022] S23, dividing the probe card layout according to the test level;

[0023] S24. Evaluate whether the divided probe card layout meets the requirements of all test levels.

[0024] Optionally, testing the test circuit die using the test hierarchy, marking defective products found in the test, analyzing the test results, identifying the distribution location and fault type of the defective products, and adjusting the probe card layout according to the identification results include the following steps:

[0025] S31, collecting test data of the test circuit die;

[0026] S32, extracting spatial features from test data of the circuit die using a convolutional neural network model;

[0027] S33, inputting the spatial features into the recursive neural network model, and using the recursive neural network model to capture the time-varying features of the test data that change over time;

[0028] S34, adjusting the convolutional neural network model using a transfer learning strategy according to the time variation characteristics, and identifying the fault type in the circuit die test data;

[0029] S35. Analyze the fault types and distribution of defective products based on the identification results, mark the defective products in the test data, and identify the problem areas with insufficient test coverage or insufficient sensitivity;

[0030] S36. Adjust the probe card layout and design dense probe test points for problem areas.

[0031] Optionally, inputting the spatial features into a recurrent neural network model, and using the recurrent neural network model to capture time-varying features in the test data that vary over time comprises the following steps:

[0032] S331. After the first sampling layer of the convolutional neural network model, a multi-layer recurrent neural network model is introduced;

[0033] S332, using the spatial features obtained after the first sampling layer of the convolutional neural network model as the first layer input of the recursive neural network model;

[0034] S333, in the first layer of the recursive neural network model, using the recursive neural network model to process spatial features and capture features that change over time;

[0035] S334. After the recursive neural network model is processed, the learned variation features are fused with the spatial features to capture the temporal variation features of the test data that change over time.

[0036] Optionally, adjusting the convolutional neural network model using a transfer learning strategy according to the time variation characteristics, and identifying the fault type in the circuit die test data includes the following steps:

[0037] S341. According to the requirements of circuit die testing, add a fully connected layer and a classification layer of the convolutional neural network model;

[0038] S342, dividing the time variation features into a training set, a validation set, and a test set, training the added fully connected layer and the classification layer using the training set, and adjusting the convolutional neural network model;

[0039] S343, training the adjusted convolutional neural network model using the time-varying features in the training set, and evaluating the performance of the convolutional neural network model using the validation set;

[0040] S344. Use the trained convolutional neural network model to predict the test set and identify different fault types.

[0041] Optionally, using a path optimization algorithm, calculating an optimal test path based on dense probe test points includes the following steps:

[0042] S51, based on dense probe test points, and setting the calculation of the optimal test path as a goal;

[0043] S52, a population of initial probe test points, wherein each individual in the population represents a test path, and a fitness function is set to evaluate the quality of the path;

[0044] S53, calculating the fitness value of each individual in the population and evaluating the efficiency of each path;

[0045] S54, selecting the best individual as the father of the next generation according to the fitness value, performing a crossover operation on the selected father individuals, and generating new offspring individuals;

[0046] S55, performing mutation operation on the offspring individuals to randomly change the access order of the test points;

[0047] S56, if the individual after the mutation operation does not meet the preset conditions, correction is performed;

[0048] S57, repeating steps S53 to S56 until a preset termination condition is reached, selecting the individual with the highest fitness as the calculated optimal test path, and outputting the optimal test path.

[0049] Optionally, the formula for calculating the fitness value of each individual in the population is:

[0050] ;

[0051] In the formula, Indicates the fitness value of the path coverage probe test point;

[0052] Indicates the weight coefficient of moving distance in probe test;

[0053] Indicates the total distance of the test path from the starting point to the end point;

[0054] Represents the weight coefficient of different intersection types on the test path;

[0055] Indicates the number of intersections that can be passed through on the path;

[0056] Indicates the number of intersections through which the path turns right;

[0057] Indicates the number of intersections on the route where left turns or U-turns are made.

[0058] Optionally, performing a mutation operation on the offspring individuals to randomly change the access order of the test points includes the following steps:

[0059] S551, randomly selecting individuals from the newly generated offspring individuals for mutation, and determining the mutation mode, which includes single-point mutation, multi-point mutation and reverse mutation;

[0060] Among them, single-point mutation involves randomly selecting a test point in an individual and then replacing the test point with a new position or exchanging the position of the test point with another test point;

[0061] Multi-point mutation involves randomly selecting multiple test points in an individual and performing the operations described in single-point mutation on the multiple test points;

[0062] Reverse mutation involves randomly selecting a subsequence on an individual path and reversing the order of the test points in the subsequence;

[0063] S552, determining the mutation method, performing mutation on the selected individuals;

[0064] S553, recalculate the fitness value of the mutated individual and ensure the validity of the mutated individual;

[0065] S554, if the mutated path fitness value is invalid, correct the path fitness value of the mutated individual;

[0066] If the path fitness value after mutation is higher than the path fitness value of each individual in the population, the successfully mutated individual will replace the individual in the population.

[0067] According to another aspect of the present invention, there is also provided a probe card partitioning layout system for testing circuit dies, the system comprising: a test simulation module, a probe card layout partitioning module, a test execution module, a probe point encryption module, a path optimization module and a layout optimization module;

[0068] The test simulation module is connected to the test execution module through the probe card layout partitioning module, the test execution module is connected to the path optimization module through the probe point encryption module, and the path optimization module is connected to the layout optimization module;

[0069] A test simulation module, used to simulate the correspondence between the probes and the contact points of the test circuit die for a preset probe card layout covering all test points using simulation technology;

[0070] A probe card layout division module is used to build test levels for different test requirements and divide the probe card layout according to the test levels;

[0071] A test execution module is used to test the test circuit die using the test hierarchy, mark defective products found in the test, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results;

[0072] Probe point encryption module, which is used to mark functional areas or high-failure areas and design dense probe test points based on the adjusted probe card layout;

[0073] A path optimization module, for calculating an optimal test path based on dense probe test points using a path optimization algorithm;

[0074] The layout optimization module is used to analyze the layout effect of dense probe test points and the path optimization results of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout.

[0075] Compared with the prior art, this application has the following beneficial effects:

[0076] 1. The present invention ensures that the test can fully cover all key performance indicators of the die by marking all necessary test points and designing a probe card layout covering these points, thereby ensuring the quality and performance of the product. The electronic simulation tool is used to simulate the correspondence between the probe and the contact points of the test circuit die, which not only improves the test efficiency, but also optimizes the probe card layout through simulation analysis, reducing problems encountered in actual production and testing, such as electrical interference and signal weakening.

[0077] 2. The present invention constructs test levels for different test requirements and divides the probe card layout accordingly, making the test process more flexible and able to adapt to different test requirements and conditions, which is conducive to the standardization and automation of testing, and at the same time provides good scalability to adapt to the development of future technologies. Through the carefully designed probe card layout and test level division, it is possible to maximize the use of limited test resources, and through simulation technology, layout and test problems can be discovered and solved in a virtual environment in advance, reducing the rework and debugging time in the actual testing phase, and accelerating the product development cycle.

[0078] 3. The present invention utilizes a convolutional neural network model to extract spatial features from test data, combined with the time-varying features captured by a recursive neural network model, to deeply understand the behavior and potential problems of circuit die from multiple dimensions, greatly improving the accuracy of fault identification. The recursive neural network model is used to capture time-varying features in test data, so that fault analysis is not limited to static features, but can also understand and identify the dynamic change process of faults, providing more information for diagnosing complex faults. By analyzing the identified fault types and defective product distribution, the problem area can be accurately marked, and the probe card layout can be adjusted in a targeted manner, and more precise probe test points can be designed. The convolutional neural network model is adjusted through a transfer learning strategy to make it more suitable for specific test requirements, and can quickly adapt to different types of circuit die tests, thereby improving the efficiency and adaptability of the test process.

[0079] 4. The present invention ensures that the test can cover the key areas of the circuit die more accurately and improves the detection sensitivity of faults, thereby improving the accuracy of the test results by accurately marking the functional areas and high-fault areas and designing dense probe test points. The optimal test path calculated by the path optimization algorithm can significantly improve the efficiency of the test process and reduce the test time. By calculating the shortest or most efficient path to access all test points, unnecessary repeated tests and movements can be avoided, thereby saving time and resources. More efficient probe card layout and test paths not only improve test efficiency, but also reduce test costs. By reducing test time and increasing the utilization rate of test equipment, higher test output can be achieved at a lower cost. It can be adjusted according to different test requirements. Whether it is the precise marking of functional areas or high-fault areas, or the path optimization based on encrypted test points, it can be customized according to actual conditions and needs to adapt to complex test scenarios.

[0080] 5. The present invention can identify bottlenecks and deficiencies in the testing process, such as areas with frequent probe access and redundancy in test paths, by analyzing the existing layout effects of probe test points and the optimization results of test paths, so as to make targeted adjustments to dense probe test points, which helps to achieve higher testing efficiency and accuracy. Through in-depth analysis of test rules and characteristic change trends, potential fault areas and key functional areas on the circuit die can be more accurately identified, so as to design dense probe test points in these areas, ensuring that the test can fully cover key parts and improve the detection capability of subtle faults. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The above characteristics, features and advantages of the present invention and their implementation methods and methods will become more clearly understood in conjunction with the following description of the embodiments, which are described in detail in conjunction with the accompanying drawings. Herein, a schematic diagram is shown:

[0082] Figure 1 is a flow chart of a probe card partitioning and layout method for a test circuit die according to an embodiment of the present invention;

[0083] Figure 2 The present invention is a block diagram of a probe card partitioning and layout system for testing a circuit die according to an embodiment of the present invention.

[0084] In the figure:

[0085] 1. Test simulation module; 2. Probe card layout division module; 3. Test execution module; 4. Probe point encryption module; 5. Path optimization module; 6. Layout optimization module. DETAILED DESCRIPTION

[0086] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0087] According to an embodiment of the present invention, a method and system for dividing and laying out a probe card for testing circuit dies are provided.

[0088] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to one embodiment of the present invention, a probe card division layout method for a test circuit die is provided, and the probe card division layout method comprises the following steps:

[0089] S1. Using simulation technology to simulate the correspondence between the probes and the contact points of the test circuit die for a preset probe card layout covering all test points.

[0090] Preferably, using simulation technology to simulate the correspondence between probes and contact points of the test circuit die for a preset probe card layout covering all test points includes the following steps:

[0091] S11. Mark all test points according to the performance indicators of the test circuit die (import the design file of the test circuit die through the file menu of the software. The design file usually contains the schematic diagram and layout diagram of the die, which is stored in Gerber file, CAD file or other professional format. View the schematic diagram and layout diagram of the circuit die in the selected software, and identify the key points that need to be tested according to the performance indicator requirements);

[0092] S12, design the probe card layout to cover all test points on the test circuit die;

[0093] S13. Use electronic simulation tools to simulate the electrical and physical correspondence between the probes and the contact points of the test circuit die, perform simulation analysis on the probe card layout, and verify the probe card layout.

[0094] It should be explained that first, all the points that must be tested are marked according to the performance indicators of the test circuit die to ensure that the test can fully cover all the key performance indicators of the die, thereby ensuring the quality and performance of the final product. Then, the probe card layout is designed to cover all the marked test points on the test circuit die, taking into account the physical structure of the probe card and the layout of the test circuit to ensure that each test point can be effectively contacted by the corresponding probe, while minimizing the use of space on the probe card to improve the efficiency and reliability of the test. Finally, by using electronic simulation tools to simulate the electrical and physical correspondence between the probe and the contact point of the test circuit die, the probe card layout is simulated and analyzed to verify the effectiveness of the probe card layout and identify problem areas such as electrical interference and signal weakening, so that the probe card layout can be optimized before actual production and testing.

[0095] The corresponding relationship is illustrated as follows: Assume that there is an integrated circuit (IC) die design, which contains multiple performance test points, including: power and location, clock input point and signal input / output (I / O) point;

[0096] Among them, power supply and ground (VDD and GND) are used to test power supply stability and power supply noise.

[0097] The clock input point is used to test the quality and stability of the clock signal.

[0098] Signal input / output (I / O) points are used to test data transfer rates, signal integrity, and latency.

[0099] S2. Construct test levels for different test requirements and divide the probe card layout according to the test levels.

[0100] Preferably, constructing test levels for different test requirements and dividing the probe card layout according to the test levels includes the following steps:

[0101] S21, collecting all test requirements of the test circuit die;

[0102] S22. Classify the test requirements and determine the test level according to different test requirements;

[0103] S23, dividing the probe card layout according to the test level;

[0104] S24. Evaluate whether the divided probe card layout meets the requirements of all test levels.

[0105] It needs to be explained that first of all, it is necessary to collect and understand all the test requirements of the test circuit die, which includes comprehensive test requirements for the die function, performance, durability, etc. According to the nature and importance of the collected test requirements, the comprehensive test requirements are classified and different test levels are determined, which helps to arrange tests in a targeted manner and ensure that each type of test requirement can receive proper attention and processing. The probe card layout is divided according to the determined test levels. According to the requirements of different test levels, the areas and resources on the probe card are allocated and optimized to make the testing process more orderly and focused. Each test level has its corresponding area, thereby improving the efficiency and accuracy of the test. Finally, the divided probe card layout is evaluated to ensure that it can meet the requirements of all test levels and that each test requirement can find the appropriate location and resources in the layout to ensure the reliability and effectiveness of the test results.

[0106] S3. Use the test hierarchy to test the test circuit die, mark the defective products found in the test, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results.

[0107] Preferably, using the test hierarchy to test the test circuit die, marking defective products found in the test, analyzing the test results, identifying the distribution location and fault type of the defective products, and adjusting the probe card layout according to the identification results includes the following steps:

[0108] S31, collecting test data of the test circuit die;

[0109] S32, extracting spatial features from test data of the circuit die using a convolutional neural network model;

[0110] In addition, it should be noted that the process of extracting spatial features from the test data of the circuit die using the convolutional neural network (CNN) model mainly involves utilizing the image processing and feature extraction capabilities of the convolutional neural network model. First, the test data of the circuit die is converted into an image or image-like format. The data image represents the physical layout of the circuit, the fault distribution map, the electrical characteristics map, etc. Then, these image data are input into the convolutional neural network model. The convolutional neural network model automatically learns and extracts key spatial features in the image through its multi-layer structure, including convolutional layers, pooling layers, and fully connected layers. The convolutional layer recognizes local patterns in the image, such as edges, textures, etc., through filters (or called convolution kernels), while the pooling layer is responsible for reducing the spatial dimension of the features and enhancing the generalization ability of the model.

[0111] S33, inputting the spatial features into the recursive neural network model, and using the recursive neural network model to capture the time-varying features of the test data that change over time;

[0112] S34, adjusting the convolutional neural network model using a transfer learning strategy according to the time variation characteristics, and identifying the fault type in the circuit die test data;

[0113] S35. Analyze the distribution of fault types and defective products based on the identification results, mark the defective products in the test data, and identify problem areas with insufficient test coverage or insufficient sensitivity (first, use the features identified by the model, such as specific patterns or abnormal signals, to locate and identify faulty areas and defective products in the circuit die. Faults are manifested as signal discontinuities, abnormal electrical characteristics, or other abnormal indicators. These faults and defective products are marked in the test data. Visual tools are usually used to highlight these areas to make them easy to identify and analyze. By comparing the frequency and type of faults in different areas, areas with insufficient test coverage or insufficient sensitivity can be identified, such as some hot spots with repeated faults or areas that have not been fully tested. Finally, based on these analysis results, the test process and probe card layout can be adjusted to improve the comprehensiveness and sensitivity of the test and ensure that potential problems can be identified and handled more effectively);

[0114] S36. Adjust the probe card layout and design dense probe test points for problem areas.

[0115] In addition, it should be noted that after a comprehensive test of the test circuit die, all test data is collected and recorded, and then the convolutional neural network (CNN) model is used to extract spatial features from the test data. The convolutional neural network model performs well in processing images and spatial data, and can identify local spatial patterns in the test data. Local spatial patterns are related to specific types of faults. The extracted spatial features are input into the recurrent neural network (RNN) model. The recurrent neural network model can capture time-varying features in the data and understand how faults evolve over time during the test process. Then, the convolutional neural network (CNN) model is further adjusted through the transfer learning strategy. It enables it to more accurately identify fault types in circuit die test data. Transfer learning allows the model to use knowledge learned on related tasks to achieve better performance on new tasks. By analyzing the fault types and defective product distribution identified by the model, defective products in the test data are marked, and areas with insufficient test coverage or insufficient sensitivity are identified. The effectiveness of the test process and the defects of the test strategy are understood. Finally, the probe card layout is adjusted for the problem areas identified through analysis, and more precise probe test points are designed. Targeted adjustments make the test more focused on the problem areas, thereby improving the test coverage and sensitivity, and ensuring that the test can more effectively identify and analyze potential problems in the circuit die.

[0116] Preferably, inputting the spatial features into the recursive neural network model and using the recursive neural network model to capture the time-varying features of the test data that vary over time comprises the following steps:

[0117] S331. After the first sampling layer of the convolutional neural network model, a multi-layer recurrent neural network model is introduced;

[0118] S332, using the spatial features obtained after the first sampling layer of the convolutional neural network model as the first layer input of the recursive neural network model;

[0119] S333, in the first layer of the recursive neural network model, using the recursive neural network model to process spatial features and capture features that change over time;

[0120] S334. After the recursive neural network model is processed, the learned variation features are fused with the spatial features to capture the temporal variation features of the test data that change over time.

[0121] Preferably, according to the time variation characteristics, the convolutional neural network model is adjusted using a transfer learning strategy, and the fault type in the circuit die test data is identified, including the following steps:

[0122] S341. According to the requirements of circuit die testing, add a fully connected layer and a classification layer of the convolutional neural network model;

[0123] S342, dividing the time variation features into a training set, a validation set, and a test set, training the added fully connected layer and the classification layer using the training set, and adjusting the convolutional neural network model;

[0124] S343, training the adjusted convolutional neural network model using the time-varying features in the training set, and evaluating the performance of the convolutional neural network model using the validation set;

[0125] S344. Use the trained convolutional neural network model to predict the test set and identify different fault types.

[0126] It needs to be explained that after introducing a multi-layer recursive neural network model into the first sampling layer of the convolutional neural network model, it means that the spatial features processed by the convolutional neural network model are passed to the recursive neural network model for further processing. Then, the spatial features processed by the first sampling layer of the convolutional neural network model are used as the input of the recursive neural network model. The convolutional neural network model effectively extracts spatial features through its convolution and sampling layers, and the recursive neural network model uses these features to capture dynamic features that change over time. The recursive neural network model layer begins to process spatial features to capture changes over time. The recursive neural network model is good at processing sequence data, so it can identify time series patterns and trends in test data, and the results of the recursive neural network model processing are fused with the spatial features of the convolutional neural network model. This fusion helps to capture the dynamic features that change over time in the test data. Changing features can improve the accuracy and sensitivity of fault detection; regarding the application of transfer learning strategies, the convolutional neural network model is adjusted by introducing and training fully connected layers and classification layers. Fully connected layers and classification layers are added to adjust according to test requirements. The segmented training set, validation set and test set are used to train and evaluate the performance of the convolutional neural network model, which can better adapt to specific test requirements and data. The training set is used to further train the convolutional neural network model, and the validation set is used to evaluate the performance of the model. The trained convolutional neural network model is used to predict the test set to identify different types of faults. Overall, this process combines the powerful spatial feature extraction capabilities of convolutional neural networks and the time series analysis capabilities of recursive neural networks, and further optimizes the model through transfer learning strategies to more accurately identify fault types and time-varying characteristics in circuit die test data.

[0127] Transfer learning strategy is a machine learning method that allows the model to apply the knowledge learned from one task (source task) to another related task (target task). It can reduce the amount of training data required for the target task while accelerating the learning process and improving the performance of the model. Transfer learning has been widely used in many fields such as image recognition, natural language processing, and sound recognition.

[0128] S4. Based on the adjusted probe card layout, mark the functional areas or high-failure areas, and design dense probe test points (in the process of marking the functional areas and high-failure areas based on the adjusted probe card layout, first load the probe card layout file through the circuit design software, and then use the software's graphics and annotation tools to mark the key areas in detail on the probe card layout diagram according to the functional planning of the circuit die and historical failure data, and distinguish between functional areas and high-failure areas).

[0129] It needs to be explained that by further refining the test strategy based on the preliminary analysis and adjusted probe card layout, especially for those functional areas or high-failure areas, it is necessary to accurately mark the various functional areas on the circuit die and their performance indicators, as well as the high-failure areas identified through previous test data analysis. Next, based on these marked areas, intensive probe test points are designed, and more probe points are added to improve the accuracy and sensitivity of the test. The design of intensive probe test points must not only consider the comprehensiveness and depth of the test, but also the efficiency and feasibility of the test. In addition, the design of intensive probe test points also involves fine-tuning the probe card layout to ensure that the newly added probe points can effectively contact the target test points on the circuit die without introducing additional interference or affecting other functions of the probe card.

[0130] S5. Calculate the optimal test path based on dense probe test points using a path optimization algorithm.

[0131] Preferably, using a path optimization algorithm, calculating an optimal test path based on dense probe test points includes the following steps:

[0132] S51, based on dense probe test points, and setting the calculation of the optimal test path as a goal;

[0133] S52, a population of initial probe test points, wherein each individual in the population represents a test path, and a fitness function is set to evaluate the quality of the path;

[0134] S53, calculating the fitness value of each individual in the population and evaluating the efficiency of each path;

[0135] S54, selecting the best individual as the father of the next generation according to the fitness value, performing a crossover operation on the selected father individuals, and generating new offspring individuals;

[0136] S55, performing mutation operation on the offspring individuals to randomly change the access order of the test points;

[0137] S56, if the individual after the mutation operation does not meet the preset conditions, correction is performed;

[0138] S57, repeating steps S53 to S56 until a preset termination condition is reached, selecting the individual with the highest fitness as the calculated optimal test path, and outputting the optimal test path.

[0139] Preferably, the formula for calculating the fitness value of each individual in the population is:

[0140] ;

[0141] In the formula, Indicates the fitness value of the path coverage probe test point;

[0142] Indicates the weight coefficient of moving distance in probe test;

[0143] Indicates the total distance of the test path from the starting point to the end point;

[0144] Represents the weight coefficient of different intersection types on the test path;

[0145] Indicates the number of intersections that can be passed through on the path;

[0146] Indicates the number of intersections through which the path turns right;

[0147] Indicates the number of intersections on the route where left turns or U-turns are made.

[0148] Preferably, performing mutation operation on the offspring individuals to randomly change the access order of the test points comprises the following steps:

[0149] S551, randomly selecting individuals from the newly generated offspring individuals for mutation, and determining the mutation mode, which includes single-point mutation, multi-point mutation and reverse mutation;

[0150] Among them, single-point mutation involves randomly selecting a test point in an individual and then replacing the test point with a new position or exchanging the position of the test point with another test point;

[0151] Multi-point mutation involves randomly selecting multiple test points in an individual and performing the operations described in single-point mutation on the multiple test points;

[0152] Reverse mutation involves randomly selecting a subsequence on an individual path and reversing the order of the test points in the subsequence;

[0153] S552, determining the mutation method, performing mutation on the selected individuals;

[0154] S553, recalculate the fitness value of the mutated individual and ensure the validity of the mutated individual;

[0155] S554, if the mutated path fitness value is invalid, correct the path fitness value of the mutated individual;

[0156] If the path fitness value after mutation is higher than the path fitness value of each individual in the population, the successfully mutated individual will replace the individual in the population.

[0157] It should be explained that, first, the optimization goal is to find the optimal test path based on the encrypted probe test points, then initialize a population of test paths, each path is regarded as an individual, and define a fitness function to evaluate the quality of each path. The fitness function is usually defined based on the path length, test efficiency or path complexity to ensure that the optimal path is both short and efficient. The fitness value of each individual in the population is calculated to evaluate the efficiency of different test paths. Then, the best path is selected according to the fitness value, and new path individuals are generated through genetic operations such as crossover and mutation. The mutation process is added, in which the access order of test points in the path is randomly changed to increase path diversity and explore more solutions. If the mutation result is not ideal, appropriate corrections will be made, and the above process will be repeated until the end condition is met, such as reaching the preset number of iterations or the fitness value is no longer significantly improved, and the path with the highest fitness is selected as the final optimal test path to ensure that the test path covers all important test points and is as short and efficient as possible, thereby optimizing the time and resource consumption of the entire test process.

[0158] The path optimization algorithm is an improved genetic algorithm that enhances the performance of the standard genetic algorithm by introducing new strategies and mechanisms. The improvements include more efficient selection mechanisms, diversified crossover and mutation operations, introduction of local search strategies, optimized fitness functions, techniques for maintaining population diversity, and dynamic adjustment of algorithm parameters. The strategies work together to improve the efficiency, speed, and quality of solutions of the algorithm in solving complex optimization problems. Through these improvements, the genetic algorithm can better balance global search and local search, effectively avoid premature convergence, and thus find better or near-optimal solutions in a wider range of problem domains.

[0159] S6. Analyze the layout effect of the dense probe test points and the path optimization results of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout.

[0160] In addition, additional supplementary explanations are as follows: The process of analyzing the layout effect of dense probe test points and the path optimization results of the optimal test path is as follows:

[0161] The simulation model is used to simulate the process of reaching the circuit die through the probe card test point. The simulation model takes into account factors such as time delay, signal attenuation, and noise interference of signal transmission. Through the simulation software of the simulation model, the current probe card layout is simulated and tested, especially the dense probe test point area, and the test results are recorded, including test coverage, signal integrity, test time and other indicators. Based on the simulation test results of the simulation model, the effect of the current probe card layout is evaluated, especially the impact of dense probe test points on test coverage and signal integrity;

[0162] The process of identifying test patterns and feature change trends is as follows:

[0163] Analyze the data generated by the simulation test to identify areas with poor test results and the reasons for low test efficiency or inaccurate test results. Use statistical machine learning algorithms to identify the regularities and characteristic change trends in the dense probe test point layout. For example, certain layout patterns lead to higher signal interference, while certain specific probe spacing improves test coverage.

[0164] The process of adjusting the dense probe test points according to the identification results is as follows:

[0165] Use algorithms of existing technologies (such as genetic algorithms and simulated annealing algorithms) to optimize test paths, reduce test time and improve test efficiency, including rearranging test sequences and optimizing probe movement paths. Based on the identified patterns and trends, adjust the layout of dense probe test points, including changing the probe spacing, increasing or decreasing the number of probes in a specific area, or adjusting the specific positions of the probes. Perform simulation tests on the adjusted probe card layout again to verify the effect of the adjustments, ensure that the improvement measures effectively improve test coverage and test efficiency, while reducing signal interference, and confirm that the adjusted probe card layout is the final version.

[0166] It needs to be explained that first, the execution results of the optimal test path are analyzed, the efficiency and coverage of the path are evaluated, and it is determined whether all encrypted probe test points are effectively tested, and whether there are unnecessary duplications or missed areas in the test path. Through the above analysis, the regularities and characteristic change trends in the test process can be identified, such as whether certain areas frequently have test bottlenecks or high-incidence areas of failure. Next, the layout of the encrypted probe test points is adjusted according to the analysis results, including adding probe test points to increase the test coverage of certain areas, or reducing those redundant test points to improve test efficiency. The test path can also be adjusted to avoid unnecessary test delays or optimize the test sequence, and the adjustments will be integrated into the final probe card layout to ensure that the test layout is both efficient and comprehensive.

[0167] According to another embodiment of the present invention, Figure 2 As shown, a probe card partitioning and layout system for testing circuit dies is also provided, the system comprising: a test simulation module 1, a probe card layout partitioning module 2, a test execution module 3, a probe point encryption module 4, a path optimization module 5 and a layout optimization module 6;

[0168] The test simulation module 1 is connected to the test execution module 3 through the probe card layout division module 2, the test execution module 3 is connected to the path optimization module 5 through the probe point encryption module 4, and the path optimization module 5 is connected to the layout optimization module 6;

[0169] A test simulation module 1 is used to simulate the correspondence between the probes and the contact points of the test circuit die for a preset probe card layout covering all test points using simulation technology;

[0170] The probe card layout division module 2 is used to construct test levels for different test requirements and divide the probe card layout according to the test levels;

[0171] The test execution module 3 is used to test the test circuit die using the test hierarchy, mark defective products found in the test, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results;

[0172] A probe point encryption module 4 is used to mark functional areas or high-failure areas based on the adjusted probe card layout, and design dense probe test points;

[0173] A path optimization module 5, used to calculate an optimal test path based on dense probe test points using a path optimization algorithm;

[0174] The layout optimization module 6 is used to analyze the layout effect of the dense probe test points and the path optimization result of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout.

[0175] In summary, with the aid of the above-mentioned technical scheme of the present invention, the present invention ensures that the test can comprehensively cover all key performance indicators of the die by marking all necessary test points and designing a probe card layout covering these points, thereby ensuring the quality and performance of the product, and utilizing electronic simulation tools to simulate the correspondence between the probe and the contact points of the test circuit die, which not only improves the efficiency of the test, but also optimizes the probe card layout through simulation analysis, thereby reducing problems encountered in actual production and testing, such as electrical interference and signal weakening; the present invention constructs test levels for different test requirements and divides the probe card layout accordingly, making the test process more flexible, able to adapt to different test requirements and conditions, and conducive to the standardization and automation of the test, while The invention provides good scalability to adapt to the development of future technologies. Through the carefully designed probe card layout and test level division, it can make the best use of limited test resources. Through the simulation technology, layout and test problems can be discovered and solved in the virtual environment in advance, which reduces the rework and debugging time in the actual test phase and accelerates the product development cycle. The invention uses the convolutional neural network model to extract spatial features from the test data, combined with the time-varying features captured by the recursive neural network model, to deeply understand the behavior and potential problems of the circuit die from multiple dimensions, greatly improve the accuracy of fault identification, and use the recursive neural network model to capture the time-varying features in the test data, so that fault analysis is not limited to static features. , and can also understand and identify the dynamic change process of faults, providing more information for diagnosing complex faults. By analyzing the identified fault types and defective product distribution, the problem area can be accurately marked, and the probe card layout can be adjusted in a targeted manner, and more precise probe test points can be designed. The convolutional neural network model is adjusted through the transfer learning strategy to make it more suitable for specific test needs, and can quickly adapt to different types of circuit die tests, thereby improving the efficiency and adaptability of the test process; the present invention ensures that the test can cover the key areas of the circuit die more accurately by accurately marking the functional areas and high-incidence areas of faults and designing dense probe test points, thereby improving the detection sensitivity of faults and thus improving the accuracy of the test results. The optimal test path calculated by the path optimization algorithm can significantly improve the efficiency of the test process and reduce the test time. By calculating the shortest or most effective path to access all test points, unnecessary repeated tests and movements can be avoided, thus saving time and resources. More effective probe card layout and test paths not only improve test efficiency, but also reduce test costs. By reducing test time and increasing the utilization rate of test equipment, higher test output can be achieved at a lower cost. It can be adjusted according to different test requirements, whether it is the precise marking of functional areas or high-failure areas, or the path optimization based on encrypted test points, it can be customized according to actual conditions and needs to adapt to complex test scenarios.The present invention can identify bottlenecks and deficiencies in the test process, such as areas with frequent probe access and redundancy of test paths, by analyzing the existing probe test point layout effects and test path optimization results, so as to make targeted adjustments to the dense probe test points, which is helpful to achieve higher test efficiency and accuracy. Through in-depth analysis of test rules and characteristic change trends, potential fault areas and key functional areas on the circuit die can be more accurately identified, so as to design dense probe test points in these areas, ensure that the test can fully cover the key parts, and improve the detection capability of subtle faults. ;

[0176] Although the present invention has been disclosed as above with preferred embodiments, the embodiments are merely examples for the convenience of description and are not intended to limit the present invention. Those skilled in the art may make several changes and modifications without departing from the spirit and scope of the present invention. The scope of protection claimed by the present invention shall be based on the claims.

Claims

1. A method for dividing and laying out a probe card for a test circuit die, characterized in that: The probe card partition layout method comprises the following steps: S1, using simulation technology to simulate the correspondence between the probes and the contact points of the test circuit die for the preset probe card layout covering all test points; S2. Construct test levels for different test requirements and divide the probe card layout according to the test levels; S3, using the test hierarchy to test the test circuit die, mark defective products, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results; S4. Based on the adjusted probe card layout, mark the functional areas or high-failure areas and design dense probe test points; S5, using a path optimization algorithm to calculate an optimal test path based on dense probe test points; S6. Analyze the layout effect of the dense probe test points and the path optimization result of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout; The method of calculating the optimal test path based on dense probe test points by using a path optimization algorithm comprises the following steps: S51, based on dense probe test points, and setting the calculation of the optimal test path as a goal; S52, a population of initial probe test points, wherein each individual in the population represents a test path, and a fitness function is set to evaluate the quality of the path; S53, calculating the fitness value of each individual in the population and evaluating the efficiency of each path; S54, selecting the best individual as the father of the next generation according to the fitness value, performing a crossover operation on the selected father individuals, and generating new offspring individuals; S55, performing mutation operation on the offspring individuals, and randomly changing the access order of the test points; S56, if the individual after the mutation operation does not meet the preset conditions, correction is performed; S57, repeating steps S53 to S56 until a preset termination condition is reached, selecting the individual with the highest fitness as the calculated optimal test path, and outputting the optimal test path; The formula for calculating the fitness value of each individual in the population is: ； In the formula, Indicates the fitness value of the path coverage probe test point; Indicates the weight coefficient of moving distance in probe test; Indicates the total distance of the test path from the starting point to the end point; Represents the weight coefficient of different intersection types on the test path; Indicates the number of intersections that can be passed through on the path; Indicates the number of intersections through which the path turns right; Indicates the number of intersections on the path where left turns or U-turns are made; The step of performing mutation operation on the offspring individuals and randomly changing the access order of the test points comprises the following steps: S551, randomly selecting individuals from the newly generated offspring individuals for mutation, and determining the mutation mode, which includes single-point mutation, multi-point mutation and reverse mutation; Wherein, the single-point mutation includes randomly selecting a test point in an individual and then replacing the test point with a new position or exchanging the position of the test point with another test point; The multi-point mutation includes randomly selecting multiple test points in an individual and performing the operation described in the single-point mutation on the multiple test points; The reverse mutation includes randomly selecting a subsequence on the individual path and reversing the order of the test points in the subsequence; S552, determining the mutation method, performing mutation on the selected individuals; S553, recalculate the fitness value of the mutated individual and ensure the validity of the mutated individual; S554, if the mutated path fitness value is invalid, correct the path fitness value of the mutated individual; If the path fitness value after mutation is higher than the path fitness value of each individual in the population, the successfully mutated individual will replace the individual in the population.

2. A method for dividing and laying out a probe card for a test circuit die according to claim 1, characterized in that: The method of using simulation technology to simulate the correspondence between the probes of the preset probe card layout covering all test points and the contact points of the test circuit die comprises the following steps: S11, marking all test points according to the performance indicators of the test circuit die; S12, design the probe card layout to cover all test points on the test circuit die; S13. Use electronic simulation tools to simulate the electrical and physical correspondence between the probes and the contact points of the test circuit die, perform simulation analysis on the probe card layout, and verify the probe card layout.

3. The method for dividing and laying out a probe card for a test circuit die according to claim 1, characterized in that: The construction of test levels for different test requirements and the division of probe card layouts according to the test levels include the following steps: S21, collecting all test requirements of the test circuit die; S22. Classify the test requirements and determine the test level according to different test requirements; S23, dividing the probe card layout according to the test level; S24. Evaluate whether the divided probe card layout meets the requirements of all test levels.

4. A method for dividing and laying out a probe card for a test circuit die according to claim 3, characterized in that: The method of testing the test circuit die using the test hierarchy, marking defective products found in the test, analyzing the test results, identifying the distribution location and fault type of the defective products, and adjusting the probe card layout according to the identification results includes the following steps: S31, collecting test data of the test circuit die; S32, extracting spatial features from test data of the circuit die using a convolutional neural network model; S33, inputting the spatial features into the recursive neural network model, and using the recursive neural network model to capture the time-varying features of the test data that change over time; S34, adjusting the convolutional neural network model using a transfer learning strategy according to the time variation characteristics, and identifying the fault type in the circuit die test data; S35. Analyze the fault types and distribution of defective products based on the identification results, mark the defective products in the test data, and identify the problem areas with insufficient test coverage or insufficient sensitivity; S36. Adjust the probe card layout and design dense probe test points for problem areas.

5. A method for dividing and laying out a probe card for a test circuit die according to claim 4, characterized in that: The step of inputting the spatial features into the recurrent neural network model and using the recurrent neural network model to capture the time-varying features of the test data that vary over time includes the following steps: S331. After the first sampling layer of the convolutional neural network model, a multi-layer recurrent neural network model is introduced; S332, using the spatial features obtained after the first sampling layer of the convolutional neural network model as the first layer input of the recursive neural network model; S333, in the first layer of the recursive neural network model, using the recursive neural network model to process spatial features and capture features that change over time; S334. After the recursive neural network model is processed, the learned variation features are fused with the spatial features to capture the temporal variation features of the test data that change over time.

6. A method for dividing and laying out a probe card for a test circuit die according to claim 5, characterized in that: The method of adjusting the convolutional neural network model according to the time variation characteristics and identifying the fault type in the circuit die test data by using the transfer learning strategy includes the following steps: S341. According to the requirements of circuit die testing, add a fully connected layer and a classification layer of the convolutional neural network model; S342, dividing the time variation features into a training set, a validation set, and a test set, training the added fully connected layer and the classification layer using the training set, and adjusting the convolutional neural network model; S343, training the adjusted convolutional neural network model using the time-varying features in the training set, and evaluating the performance of the convolutional neural network model using the validation set; S344. Use the trained convolutional neural network model to predict the test set and identify different fault types.

7. A probe card partitioning and layout system for testing circuit dies, used to implement the probe card partitioning and layout method for testing circuit dies according to any one of claims 1 to 6, characterized in that: The system includes: a test simulation module, a probe card layout partitioning module, a test execution module, a probe point encryption module, a path optimization module and a layout optimization module; The test simulation module is connected to the test execution module through the probe card layout partitioning module, the test execution module is connected to the path optimization module through the probe point encryption module, and the path optimization module is connected to the layout optimization module; The test simulation module is used to simulate the correspondence between the probes and the contact points of the test circuit die for a preset probe card layout covering all test points using simulation technology; The probe card layout division module is used to construct test levels for different test requirements and divide the probe card layout according to the test levels; The test execution module is used to test the test circuit die using the test hierarchy, mark defective products found in the test, analyze the test results, identify the distribution location and fault type of the defective products, and adjust the probe card layout according to the identification results; The probe point encryption module is used to mark functional areas or high-failure areas based on the adjusted probe card layout and design dense probe test points; The path optimization module is used to calculate the optimal test path based on the dense probe test points using a path optimization algorithm; The layout optimization module is used to analyze the layout effect of dense probe test points and the path optimization result of the optimal test path, identify the test rules and feature change trends, and adjust the dense probe test points according to the identification results to obtain the final probe card layout.

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