An enhanced gallium nitride HEMT device with dual channels and a method for preparing the same

Abstract

The present application discloses an enhanced gallium nitride HEMT device with dual channels and a preparation method thereof, belonging to the technical field of semiconductor devices. The device mainly comprises: a substrate layer; a buffer layer; a P-type gallium nitride back barrier layer, which is formed by etching a first groove in the buffer layer, depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride, so that the first groove is flush with the surface of the substrate layer, thereby forming a P-type gallium nitride back barrier, or by depositing gallium nitride of a predetermined thickness on a predetermined area above the buffer layer to form a P-type gallium nitride back barrier; a first channel layer; a first barrier layer; a second channel layer; a second barrier layer; a passivation layer; a source electrode; a gate electrode; and a drain electrode. The present application makes it easier to obtain an enhanced HEMT device with a high withstand voltage.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an enhanced gallium nitride HEMT device with a dual channel and a preparation method thereof. Background Art

[0002] In the prior art, gallium nitride materials are the preferred materials for manufacturing third-generation semiconductor devices. They are widely used because of their advantages such as wider bandgap, higher critical breakdown electric field, higher electron saturation velocity and higher thermal conductivity. Devices made of this material have the advantages of high breakdown voltage, fast switching speed, low conduction loss, small off-state leakage current and good high-temperature characteristics. Therefore, this material is widely used in the fields of high-frequency, high-voltage and high-power devices.

[0003] However, although gallium nitride (GaN)-based HEMT (high electron mobility transistor) devices have excellent properties such as high breakdown voltage, fast switching speed, low conduction loss, small off-state leakage current and good high-temperature characteristics, there are two problems: First, since electric field spikes are prone to exist near the gate edge of the device made of this material, its surface leakage current and buffer layer leakage current are large, which will cause the device to easily break down prematurely, and the voltage resistance of the device is far from the theoretical limit of GaN material; second, it is difficult to realize an enhancement-mode device with a high threshold voltage using the device made of this material. Summary of the invention

[0004] In view of the problems in the prior art that enhancement-mode devices are prone to premature breakdown and difficult to achieve high threshold voltage, the present application mainly provides an enhancement-mode gallium nitride HEMT device with a dual channel and a preparation method thereof.

[0005] In order to achieve the above-mentioned purpose, the first technical solution adopted by the present application is: an enhancement-mode gallium nitride HEMT device with a double channel, which includes: a substrate layer; a buffer layer, which is formed by deposition on the substrate layer; a P-type gallium nitride back barrier layer, which is formed by etching a first groove in the buffer layer, depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride, so that the first groove is flush with the surface of the buffer layer, thereby forming a P-type gallium nitride back barrier, or by depositing gallium nitride of a predetermined thickness on a predetermined area on the buffer layer to form a P-type gallium nitride back barrier; a first channel layer, which is formed by deposition on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; a first barrier layer, which is formed by depositing on the first channel layer a second channel layer, which is formed by deposition on the first barrier layer; a second barrier layer, which is formed by deposition on the second channel layer; a passivation layer, which is formed by deposition on the second barrier layer; a source, which is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer at the edge of the field plate to form a second trench, and depositing source material in the second trench to form the source; a gate, which is formed by etching the second channel layer and the second barrier layer to form a third trench, and depositing gate material in the third trench to form the gate; a drain, which is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and part of the buffer layer at the other edge of the field plate to form a fourth trench, and depositing drain material in the fourth trench to form the drain.

[0006] Optionally, the buffer layer is composed of a multi-layer structure or a single-layer structure, and its material is aluminum nitride, aluminum gallium nitride and / or a super lattice structure composed of aluminum nitride and gallium nitride.

[0007] Optionally, the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, and the width of the P-type gallium nitride back barrier is greater than the width of the gate.

[0008] Optionally, the P-type gallium nitride back barrier layer includes one or more P-type gallium nitride back barriers.

[0009] Optionally, when the P-type GaN back barrier layer includes a plurality of P-type GaN back barriers, the length of the next-level P-type GaN back barrier is not greater than the distance from the edge of the field plate to the first P-type GaN back barrier.

[0010] Optionally, the first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride.

[0011] Optionally, the P-type gallium nitride back barrier is located in a region of the buffer layer corresponding to the position of the gate.

[0012] Optionally, heterojunction interfaces are formed between the first channel layer and the first barrier layer, and between the second channel layer and the second barrier layer, respectively, and two-dimensional electron gases are generated respectively.

[0013] Optionally, the P-type gallium nitride back barrier layer assists in depleting the two-dimensional electron gas generated in the first channel, and the second barrier layer depletes the two-dimensional electron gas under the gate.

[0014] The second technical solution adopted in the present application is: a method for preparing an enhancement-mode gallium nitride HEMT device with a double channel, which comprises: depositing a substrate layer, and depositing a buffer layer on the substrate layer; etching a first groove in the buffer layer, and depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride, so that the first groove is flush with the surface of the buffer layer, thereby forming a P-type gallium nitride back barrier, or forming a P-type gallium nitride back barrier by depositing gallium nitride of a predetermined thickness on a predetermined area on the buffer layer, thereby forming a P-type gallium nitride back barrier layer; forming a first channel layer by depositing on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; and forming a P-type gallium nitride back barrier layer by depositing a first channel layer between the first channel layer and the buffer layer. A first barrier layer is formed by deposition on the field plate; a second channel layer is formed by deposition on the first barrier layer; a second barrier layer is formed by deposition on the second channel layer; a passivation layer is formed by deposition on the second barrier layer; a second trench is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer at the edge of the field plate, and a source material is deposited in the second trench to form a source; a third trench is formed by etching the second channel layer and the second barrier layer, and a gate material is deposited in the third trench to form a gate; a fourth trench is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and part of the buffer layer at the other edge of the field plate, and a drain material is deposited in the fourth trench to form a drain.

[0015] Optionally, the buffer layer is composed of a multi-layer structure or a single-layer structure, and its material is aluminum nitride, aluminum gallium nitride and / or a super lattice structure composed of aluminum nitride and gallium nitride.

[0016] Optionally, the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, and the width of the P-type gallium nitride back barrier is greater than the width of the gate.

[0017] Optionally, the P-type gallium nitride back barrier layer includes one or more P-type gallium nitride back barriers.

[0018] Optionally, when the P-type GaN back barrier layer includes a plurality of P-type GaN back barriers, the length of the next-level P-type GaN back barrier is not greater than the distance from the edge of the field plate to the first P-type GaN back barrier.

[0019] Optionally, the first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride.

[0020] Optionally, the P-type gallium nitride back barrier is located in a region of the buffer layer corresponding to the position of the gate.

[0021] Optionally, heterojunction interfaces are formed between the first channel layer and the first barrier layer, and between the second channel layer and the second barrier layer, respectively, and two-dimensional electron gases are generated respectively.

[0022] Optionally, the P-type gallium nitride back barrier layer assists in depleting the two-dimensional electron gas generated in the first channel, and the second barrier layer depletes the two-dimensional electron gas under the gate.

[0023] The HEMT device and the preparation method thereof provided by the present invention can more easily obtain an enhanced device with high withstand voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 It is a schematic diagram of a specific implementation of an enhancement-mode gallium nitride HEMT device with dual channels of the present application;

[0026] Figure 2 is a schematic diagram of the structure of a double-channel AlGaN / GaN HEMT with a field plate structure and a back barrier structure of the present application;

[0027] Figure 3 is a schematic diagram of another double-channel AlGaN / GaN HEMT structure with a field plate structure and a back barrier structure of the present application;

[0028] Figure 4 It is a schematic diagram of a specific implementation method of a method for preparing an enhancement-mode gallium nitride HEMT device with dual channels of the present application;

[0029] Attached Figure 1-3 Structural description: 1-substrate layer, 2-buffer layer, 3-P-type gallium nitride back barrier layer, 4-first channel layer, 5-first barrier layer, 6-second channel layer, 7-second barrier layer, 8-passivation layer.

[0030] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present application are described in detail below in conjunction with the accompanying drawings so that the advantages and features of the present application can be more easily understood by those skilled in the art, thereby making a clearer and more definite definition of the protection scope of the present application.

[0032] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0033] In the prior art, in order to solve the problem that devices made of gallium nitride materials are prone to premature breakdown and difficult to achieve enhanced devices with high threshold voltage, the following solutions are usually adopted:

[0034] In order to solve the problem of premature breakdown of devices made of gallium nitride materials, researchers have proposed a variety of technologies to increase the breakdown voltage, which mainly include field plate technology, fluorine ion implantation technology and back barrier technology.

[0035] Among them, the field plate technology introduces an electric field perpendicular to the device surface to reduce the electric field peak on the gate edge close to the drain side, assisting the depletion region to expand toward the drain, thereby increasing the average field strength in the drift region to increase the device breakdown voltage;

[0036] Ion implantation technology is to implant fluorine ions with strong electronegativity into the barrier layer of the drift region of the HEMT made of GaN material, so as to alleviate the electric field concentration effect at the gate edge and modulate the electric field distribution on the surface of the drift region.

[0037] The back barrier layer technology is to insert a back barrier layer between the buffer layer and the channel layer to raise the conduction band of the buffer layer to improve the confinement of the two-dimensional electron gas.

[0038] In order to realize enhancement-mode devices, researchers have proposed solutions including P-type gate technology, thin barrier technology, recessed gate technology and fluorine ion implantation.

[0039] P-type gate technology is to insert a layer of P-type GaN or AlGaN (aluminum gallium nitride) between the gate metal and the AlGaN (aluminum gallium nitride) barrier layer, thereby raising the conduction band in the channel below the gate to above the Fermi level, depleting the 2DEG (two-dimensional electron gas), and thus achieving the purpose of using the device as an enhancement-mode device;

[0040] Thin barrier is a technology that reduces the intensity of polarization effect by reducing the proportion and thickness of Al (aluminum) components, thereby reducing the concentration of two-dimensional electron gas and achieving enhanced technology;

[0041] The recessed gate technology is a technology that achieves enhanced performance by partially or completely etching the AlGaN barrier layer under the gate to weaken the polarization effect and deplete the 2DEG concentration in the channel under the gate.

[0042] However, although the various breakdown voltage technologies mentioned above all have the effect of improving the breakdown voltage of the device, they will also introduce other problems. For example, the field plate technology will introduce additional parasitic capacitance, and the fluorine ions injected into the barrier layer in the fluorine ion implantation technology will cause the electron mobility in the channel layer to decrease, thereby affecting the saturated output current of the device; for example, the back barrier technology increases the possibility of the inverse piezoelectric effect, and it has a scattering effect on the two-dimensional electron gas at the interface, and also affects the charge distribution of the material.

[0043] Based on the above problems, the present application further designs and optimizes the device structure to obtain an enhanced device with high withstand voltage and high threshold voltage.

[0044] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The specific embodiments described below can be combined with each other to form new embodiments. The same or similar ideas or processes described in one embodiment may not be repeated in other embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0045] Figure 1 An embodiment of an enhancement-mode gallium nitride HEMT device with double channels of the present application is shown.

[0046] Figure 1The enhanced-mode gallium nitride HEMT device with double channels shown in the figure comprises: a substrate layer; a buffer layer formed by deposition on the substrate layer; a P-type gallium nitride back barrier layer formed by etching a first groove in the buffer layer, depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride so that the first groove is flush with the surface of the buffer layer, thereby forming a P-type gallium nitride back barrier, or forming a P-type gallium nitride back barrier by depositing gallium nitride of a predetermined thickness on a predetermined area on the buffer layer; a first channel layer formed by deposition on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; a first barrier layer formed by deposition on the first channel layer; and a second channel layer formed by deposition on the first barrier layer. a second barrier layer, which is formed by deposition on the second channel layer; a passivation layer, which is formed by deposition on the second barrier layer; a source, which is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, and the second barrier layer at the edge of the field plate to form a second trench, and depositing a source material in the second trench to form the source; a gate, which is formed by etching the second channel layer and the second barrier layer to form a third trench, and depositing a gate material in the third trench to form the gate; a drain, which is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and part of the buffer layer at the other edge of the field plate to form a fourth trench, and depositing a drain material in the fourth trench to form the drain.

[0047] The HEMT device provided in this specific embodiment is easier to obtain an enhancement-mode device with high withstand voltage, and the dual-channel structure can make the currents of the two channels converge at the drain, thereby obtaining a larger saturation current. The P-type GaN (gallium nitride) back barrier layer of the device has an auxiliary depletion effect on the 2DEG (two-dimensional electron gas) in the first channel. The back barrier layer is combined with the MIS gate or the p-GaN gate inserted above the barrier layer to achieve the depletion effect on the 2DEG under the gate. The two together realize the device enhancement mode, and the P-type GaN back barrier layer (P-type gallium nitride back barrier layer) is conducive to the expansion of the depletion region of the two-dimensional electron gas, reducing the electric field peak at the gate edge. At the same time, the P-type gallium nitride back barrier layer as a blocking layer reduces the leakage current transmitted between the source and the drain through the buffer layer, effectively improving the breakdown voltage of the device; the present application combines the field plate and the gate field plate to modulate the electric field between the gate and the drain, fully optimizes the electric field distribution between the gate and the drain, and further improves the withstand voltage of the device.

[0048] Specifically, the structures of the present application from bottom to top along the vertical direction of the device are substrate layer 1, buffer layer 2, single-layer or multi-layer p-GaN 3, first channel layer 4, first barrier layer 5, second channel layer 6, second barrier layer 7 and passivation layer 8, and the structures of the present application from left to right along the lateral direction of the device are source, gate structure and drain structure. The present application forms heterojunction interfaces through the first channel layer 4 and the first barrier layer 5, the second channel layer 6 and the second barrier layer 7, respectively, and generates corresponding two-dimensional electron gas through the heterojunction interface, and uses the two-dimensional electron gas to suppress the peak voltage near the gate of the device, thereby reducing the probability of premature breakdown of the device.

[0049] In a specific embodiment of the present application, the buffer layer is composed of a multi-layer structure or a single-layer structure, and its material is aluminum nitride, aluminum gallium nitride and / or a super lattice structure composed of aluminum nitride and gallium nitride.

[0050] In a specific embodiment of the present application, the first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride.

[0051] Specifically, Figure 1 The device of the present application is shown in that a single or multiple P-GaN (P-type gallium nitride) layer is inserted as a back barrier layer under the first channel layer, and the field plate technology and the double channel technology are combined to form a double channel AlGaN (aluminum gallium nitride) or GaN (gallium nitride) HEMT device with a unique field plate structure and a back barrier structure. Among them, the substrate layer is located under the buffer layer, and its material includes sapphire, silicon, silicon carbide or intrinsic gallium nitride material; the buffer layer is located above the substrate layer and below the first channel layer, and it electrically isolates the substrate layer from the first channel layer, the source of the HEMT device, the drain of the HEMT device and the P-type gallium nitride back barrier layer; the passivation layer is located above the second barrier layer, and it isolates the HEMT device from the external environment, and its material is silicon nitride, silicon oxide or aluminum oxide. The first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride conductor material. That is, the substrate can be made of sapphire, silicon, SiC (silicon carbide) or GaN intrinsic materials; the buffer layer is composed of a multi-layer structure or a single-layer structure, and the material of each layer or the material of the multiple layers can be AlN (aluminum nitride) or AlGaN (aluminum gallium nitride) or a superlattice structure of AlN and GaN; the first channel layer and the second channel layer can be made of GaN or other channel materials; the first barrier layer and the second barrier layer can be made of AlN, AlGaN or InGaN (indium gallium nitride) and other materials; the passivation layer can be made of SiNx (silicon nitride), SiO2 (silicon oxide) or Al2O3 (aluminum oxide) and other materials.

[0052] In a specific embodiment of the present application, the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, and the width of the P-type gallium nitride back barrier is greater than the width of the gate.

[0053] In a specific embodiment of the present application, the number of the P-type gallium nitride back barriers included in the P-type gallium nitride back barrier layer is one or more.

[0054] In a specific embodiment of the present application, the P-type gallium nitride back barrier is located in a region of the buffer layer corresponding to the gate position.

[0055] Specifically, the P-GaN back barrier layer is placed between the buffer layer and the first channel layer, and it can be located in the buffer layer or on the surface close to one side of the channel layer structure, so as to achieve the purpose of directly or indirectly contacting the channel layer, and the number of P-GaN back barrier layers can be one or more, and their shapes can be arranged in various shapes. The specific shape is not limited in this application, and it is located in the buffer layer. The area obtained by projecting the gate position is divided into.

[0056] It is worth noting that the position of the P-type gallium nitride back barrier and the gate corresponding to each other as limited here is only a specific embodiment of the present application. In actual application, the P-type gallium nitride back barrier is only limited to be located in the buffer layer or on the surface of the buffer layer, and the relative position between the P-type gallium nitride back barrier and the gate is not specifically limited.

[0057] Figure 2 Schematic diagram of the double-channel AlGaN / GaN HEMT structure with field plate structure and back barrier structure of the present application. Figure 2 The double-channel AlGaN (aluminum gallium nitride) or GaN (gallium nitride) HEMT structure with a field plate structure and a back barrier structure shown includes a substrate layer 1, a buffer layer 2, a single-layer P-GaN (P-type gallium nitride) 3, a first channel layer 4, a first barrier layer 5, a second channel layer 6, a second barrier layer 7 and a passivation layer 8, a recessed gate dielectric, a T-type gate, a source and a drain plate electrode, wherein the thickness of the single-layer P-GaN is not greater than the thickness of the buffer layer, and the gate and the drain both adopt a drain field plate and a gate field plate structure. The use of these two gate and drain forms can realize electric field modulation between the gate and the drain, can fully optimize the electric field distribution between the gate and the drain, and further improve the withstand voltage of the device.

[0058] Preferably, the substrate layer of the device adopts a silicon substrate; the buffer layer is composed of one or two materials of GaN or AlGaN with a thickness of 0.5~5um; the thickness of the single layer of P-GaN is 60-150nm, its length is not greater than the distance between the source and the drain, and its width is greater than the width of the T-type gate; the thickness of the first channel layer and is 8-20nm, and the thickness of the second channel layer is 10-25nm; the first barrier layer is made of AlGaN or AlN, preferably AlN with a thickness of 1-5nm; the second barrier layer is made of AlGaN with a thickness of 15-28nm; the groove dielectric layer is made of Al2O3 (aluminum oxide) with a thickness of 4-6nm; the gate and the drain both adopt a drain field plate and a gate field plate structure.

[0059] In a specific embodiment of the present application, in a specific embodiment of the present application, when the number of P-type gallium nitride back barriers included in the P-type gallium nitride back barrier layer is multiple, the length of the next-level P-type gallium nitride back barrier arranged is not greater than the distance from the edge of the field plate to the first P-type gallium nitride back barrier.

[0060] Specifically, Figure 3 FIG. 1 is a schematic diagram of another double-channel AlGaN / GaN HEMT structure with a field plate structure and a back barrier structure of the present application. Figure 3 The double-channel AlGaN / GaN HEMT structure with a field plate structure and a back barrier structure shown in the figure includes a substrate layer 1, a buffer layer 2, a plurality of P-GaN (P-type gallium nitride) 3, a first channel layer 4, a first barrier layer 5, a second channel layer 6, a second barrier layer 7 and a passivation layer 8, a recessed gate dielectric, a Γ-type gate, a source electrode and a drain plate electrode, wherein the present application is relatively Figure 3 The length of the extra P-GaN back barrier layer is not greater than the length from the edge of the field plate to the Figure 3 The distance between the P-GaN back barrier and the field plate edge electric field spike is balanced to obtain a higher breakdown voltage. The structural constraints of the rest of the device are similar to Figure 3 The structural limitations of the devices shown are the same and will not be repeated here.

[0061] In a specific embodiment of the present application, the gate adopts a recessed gate structure to be inserted into the second barrier layer from above the barrier layer, and the gate adopts a T-type gate structure or a Γ-type gate structure.

[0062] In a specific embodiment of the present application, the drain structure is a standard drain structure or a drain field plate structure.

[0063] Specifically, the gate structure can be a MIS groove gate and the gate can be directly inserted into the second barrier layer from above the barrier layer, and the gate plate can be a T-type gate structure or a Γ-type gate structure, and the drain structure of the device can be a standard structure and a drain field plate structure.

[0064] In a specific embodiment of the present application, heterojunction interfaces are formed between the first channel layer and the first barrier layer, and between the second channel layer and the second barrier layer, respectively, and two-dimensional electron gases are generated respectively.

[0065] In a specific embodiment of the present application, the P-type gallium nitride back barrier layer assists in depleting the two-dimensional electron gas generated in the first channel, and the second barrier layer depletes the two-dimensional electron gas under the gate.

[0066] Specifically, the first channel layer and the first barrier layer form a heterojunction interface and generate a first two-dimensional electron gas, and the second channel layer and the second barrier layer form a heterojunction interface and generate a second two-dimensional electron gas. By forming a double-layer two-dimensional electron gas, the device can obtain a higher electron gas concentration, thereby greatly improving the saturation current of the device and reducing the on-resistance of the device. The P-type GaN back barrier layer is beneficial to the expansion of the depletion region and reduces the electric field peak near the gate edge. At the same time, as a blocking layer, it reduces the leakage current between the source and drain electrodes through the buffer layer.

[0067] Figure 4 It is a schematic diagram of another specific implementation of a method for preparing an enhancement-mode gallium nitride HEMT device with dual channels of the present application.

[0068] In this specific embodiment, the method for preparing an enhancement-mode gallium nitride HEMT device with a dual channel mainly includes:

[0069] S401, depositing a substrate layer, and depositing a buffer layer on the substrate layer;

[0070] S402, etching a first groove in the buffer layer, depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride, so that the first groove is flush with the surface of the buffer layer, thereby forming a P-type gallium nitride back barrier, or forming a P-type gallium nitride back barrier by depositing gallium nitride of a predetermined thickness on a predetermined area above the buffer layer, thereby forming a P-type gallium nitride back barrier layer;

[0071] S403, forming a first channel layer by depositing on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; forming a first barrier layer by depositing on the first channel layer;

[0072] S404, forming a second channel layer by deposition on the first barrier layer;

[0073] S405, forming a second barrier layer by deposition on the second channel layer;

[0074] S406, forming a passivation layer by deposition on the second barrier layer;

[0075] S407, forming a second trench by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer and the second barrier layer at the edge of the field plate, and depositing a source material in the second trench to form a source electrode;

[0076] S408, forming a third trench by etching the second channel layer and the second barrier layer, and depositing a gate material in the third trench to form a gate;

[0077] S409 , forming a fourth trench by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and part of the buffer layer at the other edge of the field plate, and depositing a drain material in the fourth trench to form a drain.

[0078] In a specific embodiment of the present application, the buffer layer is composed of a multi-layer structure or a single-layer structure, and its material is aluminum nitride, aluminum gallium nitride and / or a super lattice structure composed of aluminum nitride and gallium nitride.

[0079] In a specific embodiment of the present application, the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, and the width of the P-type gallium nitride back barrier is greater than the width of the gate.

[0080] In a specific embodiment of the present application, the number of the P-type gallium nitride back barriers included in the P-type gallium nitride back barrier layer is one or more.

[0081] In a specific embodiment of the present application, when the P-type GaN back barrier layer includes multiple P-type GaN back barriers, the length of the next-level P-type GaN back barrier is not greater than the distance from the edge of the field plate to the first P-type GaN back barrier.

[0082] In a specific embodiment of the present application, the first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride.

[0083] In a specific embodiment of the present application, the P-type gallium nitride back barrier is located in a region of the buffer layer corresponding to the gate position.

[0084] In a specific embodiment of the present application, heterojunction interfaces are formed between the first channel layer and the first barrier layer, and between the second channel layer and the second barrier layer, respectively, and two-dimensional electron gases are generated respectively.

[0085] In a specific embodiment of the present application, the P-type gallium nitride back barrier layer assists in depleting the two-dimensional electron gas generated in the first channel, and the second barrier layer depletes the two-dimensional electron gas under the gate.

[0086] The method for preparing the enhancement-mode gallium nitride HEMT device with dual channels provided in the present application can be used to implement the enhancement-mode gallium nitride HEMT device with dual channels described in any of the above embodiments. The implementation principle and technical effects are similar and will not be described in detail herein.

[0087] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0088] The above description is only an embodiment of the present application and does not limit the patent scope of the present application. Any equivalent structural transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. An enhancement-mode gallium nitride HEMT device with dual channels, characterized in that: include: substrate layer; a buffer layer formed by deposition on the substrate layer; A P-type gallium nitride back barrier layer is formed by etching a first groove in the buffer layer, depositing gallium nitride in the first groove, and depositing the material of the buffer layer again after the deposition of gallium nitride, so that the first groove is flush with the surface of the buffer layer, thereby forming the P-type gallium nitride back barrier, or by depositing gallium nitride of a predetermined thickness on a predetermined area above the buffer layer to form the P-type gallium nitride back barrier, wherein the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, the width of the P-type gallium nitride back barrier is greater than the width of the gate, and the P-type gallium nitride back barrier is located in a region corresponding to the position of the gate; A first channel layer is formed by deposition on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; a first barrier layer formed by deposition on the first channel layer; a second channel layer formed by deposition on the first barrier layer; a second barrier layer formed by deposition on the second channel layer; a passivation layer formed by deposition on the second barrier layer; A source electrode, which is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer and the second barrier layer at the edge of the field plate to form a second trench, and depositing a source electrode material in the second trench; A gate, which is formed by etching the second channel layer and the second barrier layer to form a third trench, and depositing a gate material in the third trench; The drain is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and part of the buffer layer at the other edge of the field plate to form a fourth trench, and depositing a drain material in the fourth trench.

2. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 1, characterized in that: The buffer layer is composed of a multi-layer structure or a single-layer structure, and its material is aluminum nitride, aluminum gallium nitride and / or a super lattice structure composed of aluminum nitride and gallium nitride.

3. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 1, characterized in that: The P-type gallium nitride back barrier layer includes one or more P-type gallium nitride back barriers.

4. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 3, characterized in that: When the P-type GaN back barrier layer includes a plurality of P-type GaN back barriers, the length of the next-level P-type GaN back barrier is not greater than the distance from the edge of the field plate to the first P-type GaN back barrier.

5. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 1, characterized in that: The first channel layer and the second channel layer are made of gallium nitride material; the first barrier layer and the second barrier layer are made of aluminum nitride, aluminum gallium nitride or indium gallium nitride.

6. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 1, characterized in that: Heterojunction interfaces are formed between the first channel layer and the first barrier layer, and between the second channel layer and the second barrier layer, respectively, and two-dimensional electron gases are generated respectively.

7. The enhancement-mode gallium nitride HEMT device with dual channels according to claim 1, characterized in that: The P-type gallium nitride back barrier layer assists in depleting the two-dimensional electron gas generated in the first channel, and the second barrier layer depletes the two-dimensional electron gas under the gate.

8. A method for preparing an enhancement-mode gallium nitride HEMT device having a dual channel, characterized in that: include: Depositing a substrate layer, and depositing a buffer layer on the substrate layer; A first groove is formed by etching in the buffer layer, and gallium nitride is deposited in the first groove, and the material of the buffer layer is deposited again after the deposition of gallium nitride, so that the first groove is flush with the surface of the buffer layer, thereby forming a P-type gallium nitride back barrier, or a P-type gallium nitride back barrier is formed by depositing gallium nitride of a predetermined thickness on a predetermined area above the buffer layer, thereby forming a P-type gallium nitride back barrier layer, wherein the length of the P-type gallium nitride back barrier is not greater than the distance between the source and the drain, the width of the P-type gallium nitride back barrier is greater than the width of the gate, and the P-type gallium nitride back barrier is located in a region corresponding to the position of the gate; Forming a first channel layer by depositing on the buffer layer or on the buffer layer and the P-type gallium nitride back barrier layer; forming a first barrier layer by deposition on the first channel layer; forming a second channel layer by depositing on the first barrier layer; forming a second barrier layer by deposition on the second channel layer; forming a passivation layer by deposition on the second barrier layer; Forming a second trench by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer and the second barrier layer at the edge of the field plate, and depositing a source material in the second trench to form the source electrode; forming a third trench by etching the second channel layer and the second barrier layer, and depositing a gate material in the third trench to form the gate; A fourth trench is formed by etching the buffer layer, the first channel layer, the first barrier layer, the second channel layer, the second barrier layer and a portion of the buffer layer at the other edge of the field plate, and a drain material is deposited in the fourth trench to form the drain.

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