Fully differential DFF trigger, odd frequency division circuit, chip and electronic device

Abstract

The present disclosure relates to a fully differential DFF trigger, an odd frequency division circuit, a chip and an electronic device, and relates to the field of integrated circuits. The fully differential DFF trigger includes: a first driving stage circuit, which is used to generate an intermediate differential output signal at an intermediate differential output end according to a differential clock signal received at a differential clock end and a differential input signal received at a differential input end; a second driving stage circuit, which is used to generate a final differential output signal at a final differential output end according to the differential clock signal and the intermediate differential output signal. The present disclosure is applicable to high operating frequencies and wide frequency ranges, and has excellent differential output performance. The circuit structure adopts a fully differential symmetrical structure to ensure the output performance of differential signals. Using the fully differential DFF trigger and odd frequency division circuit of the present disclosure, various odd frequency division clock output signals with a duty cycle of 50% such as three-way frequency division, five-way frequency division, seven-way frequency division and nine-way frequency division can be realized.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuits, and in particular to a fully differential DFF trigger, an odd-number frequency division circuit, a chip, and an electronic device. Background Art

[0002] Frequency division circuits are widely used in integrated circuits to reduce the frequency of input signals (such as clock signals) to the frequency required by chip modules. Frequency division circuits can be applied to clock management, communication, data conversion, oscillators, radio frequency systems, microcontrollers and processors, power management and other aspects of integrated circuits.

[0003] With the development of communication technology and the continuous reduction of semiconductor process nodes, high-speed PHY (physical) interface circuits have put forward higher and higher requirements for high-speed clock circuits. The frequency synthesis circuits and clock path circuits in high-speed PHY interface circuits require higher-performance frequency division circuits, and often require clock signals to have high-speed, differential, 50% duty cycle and other characteristics. Among them, for a 50% duty cycle, an even-numbered frequency divider naturally has a 50% duty cycle output, while an odd-numbered frequency divider is more difficult to achieve a 50% duty cycle output. Summary of the invention

[0004] In view of this, the present disclosure provides a fully differential DFF trigger, an odd-number frequency division circuit, a chip and an electronic device to achieve various odd-number frequency divisions of clock signals at ultra-high operating frequencies and in an ultra-wide output frequency range.

[0005] The technical solution of the present disclosure is achieved as follows:

[0006] According to one aspect of an embodiment of the present disclosure, a fully differential DFF trigger is provided, wherein the fully differential DFF trigger has a differential input terminal, an intermediate differential output terminal, a final differential output terminal, and a differential clock terminal;

[0007] The fully differential DFF trigger comprises:

[0008] a first driver stage circuit, the first driver stage circuit being coupled to the differential clock terminal, the differential input terminal and the intermediate stage differential output terminal, and being configured to generate an intermediate stage differential output signal at the intermediate stage differential output terminal according to a differential clock signal received at the differential clock terminal and a differential input signal received at the differential input terminal; and

[0009] The second driving stage circuit is coupled to the differential clock terminal, the intermediate stage differential output terminal and the final stage differential output terminal, and is used to generate a final stage differential output signal at the final stage differential output terminal according to the differential clock signal and the intermediate stage differential output signal.

[0010] In one possible implementation, the first driving stage circuit includes:

[0011] a first positive driving circuit, the first positive driving circuit being coupled to the differential clock terminal, the positive input terminal among the differential input terminals, and the intermediate positive output terminal among the intermediate differential output terminals, and being configured to generate an intermediate positive output signal among the intermediate differential output signals at the intermediate positive output terminal according to the differential clock signal and the positive input signal among the differential input signals received by the positive input terminal;

[0012] A first negative driving circuit, the first negative driving circuit is coupled to the differential clock terminal, the negative input terminal of the differential input terminals and the intermediate negative output terminal of the intermediate differential output terminals, and is used for generating an intermediate negative output signal of the intermediate differential output signal at the intermediate negative output terminal according to the differential clock signal and the negative input signal of the differential input signal received by the negative input terminal.

[0013] In one possible implementation manner, the first positive driving circuit includes:

[0014] A first driving PMOS, wherein a gate of the first driving PMOS is coupled to a positive clock terminal of the differential clock terminal, and a source of the first driving PMOS is coupled to a power supply;

[0015] a second driving PMOS, wherein a gate of the second driving PMOS is coupled to the positive input terminal, and a source of the second driving PMOS is coupled to a drain of the first driving PMOS;

[0016] A first driving NMOS, wherein a gate of the first driving NMOS is coupled to a negative clock terminal of the differential clock terminal, and a source of the first driving NMOS is grounded;

[0017] A second driving NMOS, wherein the gate of the second driving NMOS is coupled to the positive input terminal, the source of the second driving NMOS is coupled to the drain of the first driving NMOS, and the drain of the second driving NMOS is coupled to the drain of the second driving PMOS and coupled to the intermediate stage positive output terminal.

[0018] In one possible implementation manner, the first negative driving circuit includes:

[0019] a third driving PMOS, wherein a gate of the third driving PMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the third driving PMOS is coupled to a power supply;

[0020] a fourth driving PMOS, wherein a gate of the fourth driving PMOS is coupled to the negative input terminal, and a source of the fourth driving PMOS is coupled to a drain of the third driving PMOS;

[0021] A third driving NMOS, wherein a gate of the third driving NMOS is coupled to a negative clock terminal of the differential clock terminal, and a source of the third driving NMOS is grounded;

[0022] a fourth driving NMOS, wherein the gate of the fourth driving NMOS is coupled to the negative input terminal, the source of the fourth driving NMOS is coupled to the drain of the third driving NMOS, and the drain of the fourth driving NMOS is coupled to the drain of the fourth driving PMOS and coupled to the intermediate stage negative output terminal.

[0023] In one possible implementation manner, the second driving stage circuit includes:

[0024] a second positive driving circuit, the second positive driving circuit being coupled to the differential clock terminal, the intermediate stage positive output terminal of the intermediate stage differential output terminals, and the final stage positive output terminal of the final stage differential output terminals, and being configured to generate a final stage positive output signal of the final stage differential output signal at the final stage positive output terminal according to the differential clock signal and the intermediate stage positive output signal of the intermediate stage differential output signal received from the intermediate stage positive output terminal;

[0025] a second negative driving circuit, the second negative driving circuit is coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal and the final stage negative output terminal of the final stage differential output terminal, and is used for generating a final stage negative output signal of the final stage differential output signal at the final stage negative output terminal according to the differential clock signal and the intermediate stage negative output signal of the intermediate stage differential output signal received from the intermediate stage negative output terminal.

[0026] In one possible implementation manner, the second positive driving circuit includes:

[0027] a fifth driving PMOS, wherein a gate of the fifth driving PMOS is coupled to the negative clock terminal of the differential clock terminal, and a source of the fifth driving PMOS is coupled to a power supply;

[0028] a sixth driving PMOS, wherein a gate of the sixth driving PMOS is coupled to the intermediate stage positive output terminal, and a source of the sixth driving PMOS is coupled to a drain of the fifth driving PMOS;

[0029] a fifth driving NMOS, wherein a gate of the fifth driving NMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the fifth driving NMOS is grounded;

[0030] a sixth driving NMOS, wherein the gate of the sixth driving NMOS is coupled to the intermediate stage positive output terminal, the source of the sixth driving NMOS is coupled to the drain of the fifth driving NMOS, and the drain of the sixth driving NMOS is coupled to the drain of the sixth driving PMOS and coupled to the final stage positive output terminal.

[0031] In one possible implementation manner, the second negative driving circuit includes:

[0032] a seventh driving PMOS, wherein a gate of the seventh driving PMOS is coupled to the negative clock terminal of the differential clock terminal, and a source of the seventh driving PMOS is coupled to a power supply;

[0033] an eighth driving PMOS, wherein a gate of the eighth driving PMOS is coupled to the intermediate stage negative output terminal, and a source of the eighth driving PMOS is coupled to a drain of the seventh driving PMOS;

[0034] a seventh driving NMOS, wherein a gate of the seventh driving NMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the seventh driving NMOS is grounded;

[0035] an eighth driving NMOS, wherein the gate of the eighth driving NMOS is coupled to the intermediate stage negative output terminal, the source of the eighth driving NMOS is coupled to the drain of the seventh driving NMOS, and the drain of the eighth driving NMOS is coupled to the drain of the eighth driving PMOS and coupled to the final stage negative output terminal.

[0036] In a possible implementation manner, the fully differential DFF trigger further includes:

[0037] a first latch circuit, the first latch circuit being coupled to the differential clock terminal and the intermediate stage differential output terminal and being used for latching the intermediate stage differential output signal, wherein the signal driving capability of the first latch circuit is lower than the signal driving capability of the first driving stage circuit;

[0038] A second latch circuit, the second latch circuit is coupled to the differential clock terminal and the final differential output terminal, and is used to latch the final differential output signal, wherein the signal driving capability of the second latch circuit is lower than the signal driving capability of the second driving stage circuit.

[0039] In one possible implementation manner, the first latch circuit includes:

[0040] a first positive latch circuit, the first positive latch circuit being coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal, and the intermediate stage positive output terminal of the intermediate stage differential output terminal, and being configured to latch the intermediate stage positive output signal of the intermediate stage differential output signal generated by the intermediate stage positive output terminal according to the differential clock signal and the intermediate stage negative output signal of the intermediate stage differential output signal received from the intermediate stage negative output terminal;

[0041] A first negative latch circuit, the first negative latch circuit is coupled to the differential clock terminal, the intermediate stage negative output terminal and the intermediate stage positive output terminal, and is used for latching the intermediate stage negative output signal in the intermediate stage differential output signal generated by the intermediate stage negative output terminal according to the differential clock signal and the intermediate stage positive output signal received from the intermediate stage positive output terminal.

[0042] In one possible implementation manner, the first positive latch circuit includes:

[0043] A first latch PMOS, wherein a gate of the first latch PMOS is coupled to a negative clock terminal of the differential clock terminal, and a source of the first latch PMOS is coupled to a power supply;

[0044] a second latch PMOS, wherein a gate of the second latch PMOS is coupled to the intermediate stage negative output terminal, and a source of the second latch PMOS is coupled to a drain of the first latch PMOS;

[0045] A first latch NMOS, wherein a gate of the first latch NMOS is coupled to a positive clock terminal of the differential clock terminal, and a source of the first latch NMOS is grounded;

[0046] A second latch NMOS, wherein the gate of the second latch NMOS is coupled to the intermediate stage negative output terminal, the source of the second latch NMOS is coupled to the drain of the first latch NMOS, and the drain of the second latch NMOS is coupled to the drain of the second latch PMOS and coupled to the intermediate stage positive output terminal.

[0047] In one possible implementation, the first negative latch circuit includes:

[0048] a third latch PMOS, wherein a gate of the third latch PMOS is coupled to the negative clock terminal of the differential clock terminal, and a source of the third latch PMOS is coupled to a power supply;

[0049] a fourth latch PMOS, wherein a gate of the fourth latch PMOS is coupled to the intermediate stage positive output terminal, and a source of the fourth latch PMOS is coupled to a drain of the third latch PMOS;

[0050] A third latch NMOS, wherein a gate of the third latch NMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the third latch NMOS is grounded;

[0051] A fourth latch NMOS, wherein the gate of the fourth latch NMOS is coupled to the intermediate stage positive output terminal, the source of the fourth latch NMOS is coupled to the drain of the third latch NMOS, and the drain of the fourth latch NMOS is coupled to the drain of the fourth latch PMOS and coupled to the intermediate stage negative output terminal.

[0052] In one possible implementation manner, the second latch circuit includes:

[0053] a second positive latch circuit, the second positive latch circuit being coupled to the differential clock terminal, the final negative output terminal of the final differential output terminal, and the final positive output terminal of the final differential output terminal, and being configured to latch the final positive output signal of the final differential output signal generated by the final positive output terminal according to the differential clock signal and the final negative output signal of the final differential output signal received from the final negative output terminal;

[0054] A second negative latch circuit, the second negative latch circuit is coupled to the differential clock terminal, the final stage negative output terminal and the final stage positive output terminal, and is used to latch the final stage negative output signal in the final stage differential output signal generated by the final stage negative output terminal according to the differential clock signal and the final stage positive output signal received from the final stage positive output terminal.

[0055] In one possible implementation manner, the second positive latch circuit includes:

[0056] a fifth latch PMOS, wherein a gate of the fifth latch PMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the fifth latch PMOS is coupled to a power supply;

[0057] a sixth latch PMOS, wherein a gate of the sixth latch PMOS is coupled to the final negative output terminal, and a source of the sixth latch PMOS is coupled to a drain of the fifth latch PMOS;

[0058] a fifth latch NMOS, wherein a gate of the fifth latch NMOS is coupled to the negative clock terminal of the differential clock terminal, and a source of the fifth latch NMOS is grounded;

[0059] A sixth latch NMOS, wherein the gate of the sixth latch NMOS is coupled to the final stage negative output terminal, the source of the sixth latch NMOS is coupled to the drain of the fifth latch NMOS, and the drain of the sixth latch NMOS is coupled to the drain of the sixth latch PMOS and coupled to the final stage positive output terminal.

[0060] In one possible implementation manner, the second negative latch circuit includes:

[0061] a seventh latch PMOS, wherein a gate of the seventh latch PMOS is coupled to the positive clock terminal of the differential clock terminal, and a source of the seventh latch PMOS is coupled to a power supply;

[0062] an eighth latch PMOS, wherein a gate of the eighth latch PMOS is coupled to the final-stage positive output terminal, and a source of the eighth latch PMOS is coupled to a drain of the seventh latch PMOS;

[0063] a seventh latch NMOS, wherein a gate of the seventh latch NMOS is coupled to the negative clock terminal of the differential clock terminal, and a source of the seventh latch NMOS is grounded;

[0064] An eighth latch NMOS, wherein the gate of the eighth latch NMOS is coupled to the final stage positive output terminal, the source of the eighth latch NMOS is coupled to the drain of the seventh latch NMOS, and the drain of the eighth latch NMOS is coupled to the drain of the eighth latch PMOS and coupled to the final stage negative output terminal.

[0065] According to another aspect of an embodiment of the present disclosure, there is provided an odd-number frequency division circuit, comprising:

[0066] A clock signal transmission circuit, comprising a signal transmission chain consisting of at least two coupled fully differential DFF triggers as described in any one of the above items, wherein in the signal transmission chain, the differential input terminal of the latter fully differential DFF trigger between two adjacent fully differential DFF triggers is coupled to the final differential output terminal of the previous fully differential DFF trigger, and the differential clock terminal of each of the fully differential DFF triggers in the clock signal transmission circuit receives a system differential clock signal;

[0067] a first NOR gate, wherein one input terminal of the first NOR gate is coupled to a positive input terminal among differential input terminals of a last fully differential DFF flip-flop in the signal transmission chain, another input terminal of the first NOR gate is coupled to a final positive output terminal among final differential output terminals of the last fully differential DFF flip-flop, and an output terminal of the first NOR gate is coupled to a positive input terminal among differential input terminals of a first fully differential DFF flip-flop in the signal transmission chain;

[0068] a first NAND gate, wherein one input terminal of the first NAND gate is coupled to a negative input terminal of the differential input terminals of the last fully differential DFF trigger, another input terminal of the first NAND gate is coupled to a final negative output terminal of a final differential output terminal of the last fully differential DFF trigger, and an output terminal of the first NAND gate is coupled to a negative input terminal of the differential input terminals of the first fully differential DFF trigger;

[0069] A fully differential output stage circuit, wherein the fully differential output stage circuit is coupled to the final differential output terminal and the intermediate differential output terminal of the last fully differential DFF trigger, and outputs an odd-numbered frequency-divided differential clock signal associated with the system differential clock signal according to the final differential output signal and the intermediate differential output signal output by the last fully differential DFF trigger.

[0070] In one possible implementation, the fully differential output stage circuit includes:

[0071] a second NOR gate, wherein one input terminal of the second NOR gate is coupled to a final positive output terminal of a final differential output terminal of the last fully differential DFF flip-flop, another input terminal of the second NOR gate is coupled to an intermediate negative output terminal of an intermediate differential output terminal of the last fully differential DFF flip-flop, and an output terminal of the second NOR gate outputs a positive clock signal of the odd-numbered frequency-divided differential clock signal;

[0072] A second NAND gate, one input end of the second NAND gate is coupled to the final negative output end of the final differential output end of the last fully differential DFF trigger, the other input end of the second NAND gate is coupled to the intermediate positive output end of the intermediate differential output end of the last fully differential DFF trigger, and the output end of the second NAND gate outputs the negative clock signal of the odd-numbered frequency-divided differential clock signal.

[0073] In one possible implementation manner, the fully differential output stage circuit further includes:

[0074] A cross-coupling pair is coupled between an output terminal of the second NOR gate and an output terminal of the second NAND gate.

[0075] In one possible implementation manner, the cross-coupling pair includes:

[0076] A first inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the second NOR gate, and an output terminal of the first inverter is coupled to an output terminal of the second NAND gate;

[0077] A second inverter, wherein an input terminal of the second inverter is coupled to an output terminal of the second NAND gate, and an output terminal of the second inverter is coupled to an output terminal of the second NOR gate.

[0078] According to another aspect of an embodiment of the present disclosure, a chip is provided, comprising the odd-number frequency division circuit as described in any one of the above items.

[0079] According to another aspect of an embodiment of the present disclosure, an electronic device is provided, comprising the chip as described above.

[0080] It can be seen from the above scheme that the fully differential DFF trigger, odd frequency division circuit, chip and electronic device of the embodiment of the present disclosure can be applied to high operating frequency and wide frequency range, and have excellent differential output performance. The circuit structure of the fully differential DFF trigger and the odd frequency division circuit adopts a fully differential symmetrical structure to ensure the output performance of the differential signal. In addition, the differential output performance can be further improved by adding a cross-coupling pair at the output stage. Using the fully differential DFF trigger and odd frequency division circuit disclosed in the present disclosure, various odd frequency division clock output signals with a duty cycle of 50% such as three-way division, five-way division, seven-way division and nine-way division can be realized. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 A schematic diagram of a three-frequency division circuit structure of a single-ended clock output in the related art;

[0082] Figure 2 for Figure 1 The timing diagram of the three-way frequency division circuit of the single-ended clock output is shown;

[0083] Figure 3 A schematic diagram of a five-frequency division circuit structure for a single-ended clock output in the related art;

[0084] Figure 4 for Figure 3 The timing diagram of the five-frequency divider circuit with single-ended clock output is shown;

[0085] Figure 5 is a schematic diagram of a circuit structure of a fully differential DFF trigger according to an exemplary embodiment;

[0086] Figure 6 is a schematic diagram of a circuit structure of another fully differential DFF trigger according to an exemplary embodiment;

[0087] Figure 7 is a schematic diagram of an odd-number frequency division circuit structure according to an exemplary embodiment;

[0088] Figure 8 is a schematic diagram of a three-frequency division circuit structure according to an exemplary embodiment;

[0089] Fig. 9 yes Figure 8 The timing diagram of the three-frequency dividing circuit shown;

[0090] Fig.10 1 is a schematic diagram of a five-frequency division circuit structure according to an exemplary embodiment. DETAILED DESCRIPTION

[0091] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below with reference to the accompanying drawings and examples.

[0092] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0093] The trigger is a commonly used component in the digital frequency division circuit, which can be used for clock, data and other signal processing. Among them, in the signal processing of the clock signal, the trigger is a commonly used semiconductor device. The trigger of the relevant technology is used to realize odd frequency division. If you want to achieve a 50% duty cycle output, the usual odd frequency divider needs to be composed of an odd frequency division circuit and a 50% duty cycle generation circuit. Among them, the 50% duty cycle generation circuit is specifically used to adjust the clock signal after the odd frequency division circuit is divided into a 50% duty cycle, so that the clock signal after the odd frequency division can be used.

[0094] Figure 1 The schematic diagram of the three-frequency circuit structure of the single-ended clock output in the related art is as follows. Figure 2 for Figure 1 The timing diagram of the three-way frequency division circuit with single-ended clock output is shown in FIG. Figure 1 As shown, the three-way frequency division circuit of the single-ended clock output mainly includes a three-way frequency division circuit 101 and a 50% duty cycle generation circuit 102. The three-way frequency division circuit 101 includes a first D flip-flop dff0, a second D flip-flop dff1 and a first NOR gate nor0, wherein the clock input port Clk of the first D flip-flop dff0 and the clock input port Clk of the second D flip-flop dff1 are connected to the clock input signal clkin, the output terminal Q0 of the first D flip-flop dff0 is coupled to the input terminal D of the second D flip-flop dff1 and one input terminal of the first NOR gate nor0, the output terminal Q1 of the second D flip-flop dff1 is used as the output terminal of the three-way frequency division circuit 101 to output the three-way frequency division signal div3, and the output terminal Q1 of the second D flip-flop dff1 is coupled to the other input terminal of the first NOR gate nor0, and the output terminal of the first NOR gate nor0 is coupled to the input terminal D of the first D flip-flop dff0. The 50% duty cycle generation circuit 102 includes a third D flip-flop dff2 and a second NOR gate nor1, wherein the clock input port Clk of the third D flip-flop dff2 is connected to the clock input signal clkin, the output terminal Q0 of the first D flip-flop dff0 is coupled to the input terminal D of the second D flip-flop dff1 and one input terminal of the first NOR gate nor0, the output terminal Q1 of the second D flip-flop dff1 is coupled to the input terminal D of the first D flip-flop dff0. The clock input signal clkin is connected, the input terminal D of the third D flip-flop dff2 and one input terminal of the second NOR gate nor1 are coupled to the output terminal of the three-way frequency division circuit 101 to receive the three-way frequency division signal div3. Specifically, the input terminal D of the third D flip-flop dff2 and one input terminal of the second NOR gate nor1 are coupled to the output terminal Q1 of the second D flip-flop dff1, and the output terminal Q_h of the third D flip-flop dff2 is coupled to the other input terminal of the second NOR gate nor1 to output the three-way frequency division delay signal div3_h to the second NOR gate nor1. The second NOR gate nor1 obtains a 50% duty cycle three-way frequency division clock signal div3_g according to the three-way frequency division signal div3 received at one input terminal and the three-way frequency division delay signal div3_h received at the other input terminal.

[0095] The first D flip-flop dff0 and the second D flip-flop dff1 are triggered by the rising edge of the clock input signal clkin, and the third D flip-flop dff2 is triggered by the falling edge of the clock input signal clkin. The working principle of the three-way frequency division circuit 101 is shown in Table 1: Q1Q0 (indicating the value of the output terminal Q1 of the second D flip-flop dff1 and the output terminal Q0 of the first D flip-flop dff0) is the current state, Assuming that the initial states Q1Q0 of the second D flip-flop dff1 and the first D flip-flop dff0 are 00, after the next rising edge of the clock input signal clkin arrives, the next state of the second D flip-flop dff1 and the first D flip-flop dff0 is becomes 01, Figure 1 According to the logic of the circuit diagram shown, Q1Q0 will change cyclically between 00, 01, and 10. The clock sequence of the three-way frequency division circuit 101 outputting the three-way frequency division signal div3 is expressed as 001001001001001001…, the frequency of the clock input signal clkin is divided by 3, and the duty cycle of the three-way frequency division signal div3 is 33.33%. The output waveform is as follows: Figure 2 The timing waveform of the three-frequency division signal div3 is shown.

[0096] Table 1 Three-way frequency circuit 101 working principle truth table

[0097]

[0098] See also Figure 2 As shown, Figure 1The principle of generating a 50% duty cycle by the 50% duty cycle generating circuit 102 in the three-frequency dividing circuit of the single-ended clock output shown is as follows: delaying the three-frequency dividing signal div3 by half a cycle through the third D flip-flop dff2 (falling edge flip-flop) to generate a three-frequency dividing delay signal div3_h, and performing a NOR logic operation on the three-frequency dividing signal div3 and the three-frequency dividing delay signal div3_h through the second NOR gate nor1 to generate a 50% duty cycle three-frequency dividing clock signal div3_g.

[0099] Using the above principle, the frequency division circuit can be expanded to a five-frequency division circuit. Figure 3 Schematic diagram of the five-frequency division circuit structure of the single-ended clock output in the related art. Figure 4 for Figure 3 The timing diagram of the five-frequency divider circuit with single-ended clock output is shown in FIG. The five-frequency divider circuit mainly includes a five-frequency divider circuit and a 50% duty cycle generating circuit. Figure 3 As shown, the five-frequency division circuit includes a first D flip-flop dff0, a second D flip-flop dff1, a third D flip-flop dff2 and a first NOR gate nor0, wherein a clock input port Clk of the first D flip-flop dff0, a clock input port Clk of the second D flip-flop dff1 and a clock input port Clk of the third D flip-flop dff2 are connected to a clock input signal clkin, an output terminal Q0 of the first D flip-flop dff0 is coupled to an input terminal D of the second D flip-flop dff1, an output terminal Q1 of the second D flip-flop dff1 is coupled to an input terminal D of the third D flip-flop dff2 and an input terminal of the first NOR gate nor0, an output terminal Q2 of the third D flip-flop dff2 serves as an output terminal of the five-frequency division circuit to output a five-frequency division signal div5, and an output terminal Q2 of the third D flip-flop dff2 is coupled to another input terminal of the first NOR gate nor0, and an output terminal of the first NOR gate nor0 is coupled to an input terminal D of the first D flip-flop dff0. The 50% duty cycle generating circuit comprises a fourth D flip-flop dff3 and a second NOR gate nor1, wherein the clock input port of the fourth D flip-flop dff3 is Connected to the clock input signal clkin, the input terminal D of the fourth D flip-flop dff3 and one input terminal of the second NOR gate nor1 are coupled to the output terminal of the five-division circuit to receive the five-division signal div5. Specifically, the input terminal D of the fourth D flip-flop dff3 and one input terminal of the second NOR gate nor1 are coupled to the output terminal Q2 of the third D flip-flop dff2. The output terminal Q_h of the fourth D flip-flop dff3 is coupled to the other input terminal of the second NOR gate nor1 to output the five-division delay signal div5_h to the second NOR gate nor1. The second NOR gate nor1 obtains a 50% duty cycle five-division clock signal div5_g according to the five-division signal div5 received at one input terminal and the five-division delay signal div5_h received at the other input terminal.

[0100] Among them, the first D flip-flop dff0, the second D flip-flop dff1 and the third D flip-flop dff2 are triggered by the rising edge of the clock input signal clkin, and the fourth D flip-flop dff3 is triggered by the falling edge of the clock input signal clkin. The working principle of the five-frequency dividing circuit is shown in Table 2: Q2Q1Q0 (indicates the value of the output terminal Q2 of the third D flip-flop dff2, the output terminal Q1 of the second D flip-flop dff1 and the output terminal Q0 of the first D flip-flop dff0) is the current state, Assuming that the initial states Q2Q1Q0 of the third D flip-flop dff2, the second D flip-flop dff1 and the first D flip-flop dff0 are 000, after the next rising edge of the clock input signal clkin arrives, the next state of the third D flip-flop dff2, the second D flip-flop dff1 and the first D flip-flop dff0 is becomes 001, Figure 3 According to the logic of the circuit diagram shown, Q2Q1Q0 will change cyclically between 000, 001, 011, 110, and 100. The clock sequence of the five-frequency division circuit outputting the five-frequency division signal div5 is expressed as 00011000110001100011…, and the duty cycle of the five-frequency division signal div5 is 40%. The output waveform is as follows: Figure 4 The timing waveform of the five-frequency division signal div5 is shown.

[0101] Table 2 Truth table of the working principle of the five-frequency divider circuit

[0102]

[0103] Figure 3 The principle of the 50% duty cycle generating circuit in the five-frequency division circuit of the single-ended clock output shown in the figure is as follows: the five-frequency division signal div5 is delayed by half a cycle through the fourth D flip-flop dff3 (falling edge flip-flop) to generate a five-frequency division delay signal div5_h, and the five-frequency division signal div5 and the five-frequency division delay signal div5_h are subjected to a NOR logic operation through the second NOR gate nor1 to generate a 50% duty cycle five-frequency division clock signal div5_g.

[0104] According to the above principle, the circuit with 50% duty cycle clock output can be further expanded into odd-number divider circuits such as seven-division and nine-division.

[0105] As mentioned above, the odd-number frequency-dividing circuits have only one frequency-dividing clock signal with a single-ended output and cannot provide differential output. In addition, the single-ended clock inside the trigger must be converted into a differential clock to drive the trigger. This causes the Tcq time (the delay time from the clock input port Clk of the trigger to the output port Q) to become longer, which makes it difficult for the frequency-dividing circuit to reach the maximum operating frequency. In addition, since the Tcq of the rising edge trigger and the Tcq of the falling edge trigger are not the same, the 50% output duty cycle performance will also deteriorate.

[0106] In view of this, the embodiments of the present disclosure provide a fully differential DFF trigger, an odd-number division circuit, a chip and an electronic device to achieve odd-number division of a clock signal suitable for high speed, wide frequency range, and fully differential 50% duty cycle.

[0107] Figure 5 1 is a circuit diagram of a fully differential DFF (Data Flip-Flop) trigger according to an exemplary embodiment. The fully differential DFF trigger of the disclosed embodiment, i.e., a fully differential D-type trigger, has a differential input terminal (D, )、Intermediate differential output terminal (A、 )、final differential output terminal(Q、 ) and differential clock terminals (ck, ).like Figure 5 As shown, in the exemplary embodiment, the fully differential DFF trigger includes a first driver stage circuit 51 and a second driver stage circuit 52. The first driver stage circuit 51 is coupled to the differential clock terminal, the differential input terminal and the intermediate differential output terminal, and the first driver stage circuit 51 is used to generate an intermediate differential output signal at the intermediate differential output terminal according to the differential clock signal received at the differential clock terminal and the differential input signal received at the differential input terminal. The second driver stage circuit 52 is coupled to the differential clock terminal, the intermediate differential output terminal and the final differential output terminal, and the second driver stage circuit 52 is used to generate a final differential output signal at the final differential output terminal according to the differential clock signal and the intermediate differential output signal.

[0108] The fully differential DFF trigger of the disclosed embodiment is a fully differential, semi-dynamic DFF trigger, whose differential clock terminal can be connected to a differential clock signal, and whose differential input terminal can be connected to a differential input signal, and the required two pairs of differential output signals are generated at the intermediate-stage differential output terminal and the final-stage differential output terminal, respectively. Thus, in conjunction with other logic devices, odd-number division suitable for high-speed, wide-frequency range, and odd-number division of fully differential 50% duty cycle clock signals can be achieved.

[0109] like Figure 5As shown, in the exemplary embodiment, the first driving stage circuit 51 includes a first positive driving circuit 511 and a first negative driving circuit 512. The first positive driving circuit 511 is coupled to the differential clock terminal, the positive input terminal D among the differential input terminals, and the intermediate stage positive output terminal A among the intermediate stage differential output terminals. The first positive driving circuit 511 is used to generate an intermediate stage positive output signal among the intermediate stage differential output signals at the intermediate stage positive output terminal A according to the differential clock signal and the positive input signal among the differential input signals received by the positive input terminal D. The first negative driving circuit 512 is coupled to the differential clock terminal, the negative input terminal among the differential input terminals, and the intermediate stage positive output terminal A among the intermediate stage differential output signals. and the intermediate stage negative output terminal of the intermediate stage differential output terminal , used according to the differential clock signal, and the negative input terminal The negative input signal in the received differential input signal is at the negative output terminal of the intermediate stage. An intermediate stage negative output signal is generated among the intermediate stage differential output signals.

[0110] like Figure 5 As shown, in the exemplary embodiment, the first positive driving circuit 511 includes a first driving PMOS P11, a second driving PMOS P12, a first driving NMOS N11 and a second driving NMOS N12. The gate of the first driving PMOS P11 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the first driving PMOS P11 is coupled to the power supply. The gate of the second driving PMOS P12 is coupled to the positive input terminal D, and the source of the second driving PMOS P12 is coupled to the drain of the first driving PMOS P11. The gate of the first driving NMOS N11 is coupled to the negative clock terminal of the differential clock terminal. , the source of the first driving NMOS N11 is grounded. The gate of the second driving NMOS N12 is coupled to the positive input terminal D, the source of the second driving NMOS N12 is coupled to the drain of the first driving NMOS N11, and the drain of the second driving NMOS N12 is coupled to the drain of the second driving PMOS P12 and coupled to the intermediate stage positive output terminal A. It can be seen that the first positive driving circuit 511 composed of the first driving PMOS P11, the second driving PMOS P12, the first driving NMOS N11 and the second driving NMOS N12 is equivalent to a three-state gate circuit, wherein the differential clock terminal is equivalent to the enable terminal of the three-state gate, the positive input terminal D is equivalent to the input terminal of the three-state gate, and the intermediate stage positive output terminal A is equivalent to the output terminal of the three-state gate. According to the working principle of the tri-state gate circuit, in the first positive driving circuit 511: when the positive clock signal received at the positive clock end of the differential clock end is at a low level (i.e., the negative clock signal received at the negative clock end of the differential clock end is at a high level), the first driving PMOS P11 and the first driving NMOS N11 are turned on, and then the second driving PMOS P12 and the second driving NMOS N12 form an inverter, and at this time, the intermediate stage positive output signal of the intermediate stage positive output terminal A is opposite to the positive input signal of the positive input terminal D; when the positive clock signal received at the positive clock end of the differential clock end is at a high level (i.e., the negative clock signal received at the negative clock end of the differential clock end is at a low level), the first driving PMOS P11 and the first driving NMOS N11 are turned off, and the intermediate stage positive output terminal A is in a high impedance state because it is disconnected from both the power supply and the ground. It can be seen that starting from the rising edge of the positive clock signal received at the positive clock end of the differential clock end, the first positive drive circuit 511 can sample the positive input signal of the differential input signal to obtain a state opposite to the positive input signal and maintain it. Because there is a parasitic capacitance between the CMOS (Complementary Metal Oxide Semiconductor) device and the integrated circuit substrate, the intermediate stage positive output terminal A can maintain the rising edge of the positive clock signal in a state opposite to the positive input signal for a period of time in a high impedance state.

[0111] like Figure 5 As shown, in the exemplary embodiment, the first negative driving circuit 512 includes a third driving PMOS P13, a fourth driving PMOS P14, a third driving NMOS N13 and a fourth driving NMOS N14. The gate of the third driving PMOS P13 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the third driving PMOS P13 is coupled to the power supply. The gate of the fourth driving PMOS P14 is coupled to the negative input terminal The source of the fourth driving PMOS P14 is coupled to the drain of the third driving PMOS P13. The gate of the third driving NMOS N13 is coupled to the negative clock terminal of the differential clock terminal. The source of the third driving NMOS N13 is grounded. The gate of the fourth driving NMOS N14 is coupled to the negative input terminal The source of the fourth driving NMOS N14 is coupled to the drain of the third driving NMOS N13, the drain of the fourth driving NMOS N14 is coupled to the drain of the fourth driving PMOS P14 and coupled to the intermediate stage negative output terminal It can be seen that the first negative driving circuit 512 composed of the third driving PMOS P13, the fourth driving PMOS P14, the third driving NMOS N13 and the fourth driving NMOS N14 is equivalent to a three-state gate circuit, in which the differential clock terminal is equivalent to the enable terminal of the three-state gate, and the negative input terminal Equivalent to the input of the three-state gate, the negative output of the intermediate stage According to the working principle of the tri-state gate circuit, in the first negative driving circuit 512: when the positive clock signal received at the positive clock end of the differential clock end is at a low level (that is, the negative clock signal received at the negative clock end of the differential clock end is at a high level), the third driving PMOS P13 and the third driving NMOS N13 are turned on, and then the fourth driving PMOS P14 and the fourth driving NMOS N14 form an inverter. At this time, the intermediate stage negative output terminal The signal is connected to the negative input terminal of the differential input terminal. When the positive clock signal received at the positive clock end of the differential clock end is high level (that is, the negative clock signal received at the negative clock end of the differential clock end is low level), the third driver PMOS P13 and the third driver NMOS N13 are turned off, and the intermediate stage negative output terminal Because it is disconnected from the power supply and the ground, it is in a high impedance state. It can be seen that starting from the rising edge of the positive clock signal received by the positive clock end of the differential clock end, the first negative drive circuit 512 can sample the negative input signal of the differential input signal to obtain a state opposite to the negative input signal and maintain it. Because there is a parasitic capacitance between the CMOS device and the integrated circuit substrate, the intermediate stage negative output terminal In the high-impedance state, the rising edge of the positive clock signal can be kept opposite to the negative input signal for a period of time.

[0112] It can be seen from the above description that the first driving stage circuit 51 starts sampling and holding the differential input signal at the rising edge of the positive clock signal received at the positive clock end of the differential clock end (represented by the positive clock signal in the differential clock signal, the rising edge of the positive clock signal in the differential clock signal can also be called the rising edge of the differential clock signal), and utilizes the parasitic capacitance between the CMOS device and the integrated circuit substrate so that the intermediate stage differential output end can save the state of the differential input signal at the rising edge of the differential clock signal for a period of time in the high impedance state after the rising edge of the differential clock signal, wherein the intermediate stage positive output end A saves the state of the differential clock signal at the rising edge of the differential clock signal opposite to the state of the positive input signal in the differential input signal, and the intermediate stage negative output end What is saved is the state where the rising edge time of the differential clock signal is opposite to the negative input signal in the differential input signal.

[0113] like Figure 5 As shown, in the exemplary embodiment, the second driving stage circuit 52 includes a second positive driving circuit 521 and a second negative driving circuit 522. The second positive driving circuit 521 is coupled to the differential clock terminal, the intermediate stage positive output terminal A of the intermediate stage differential output terminal, and the final stage positive output terminal Q of the final stage differential output terminal, and is used to generate a final stage positive output signal Q of the final stage differential output signal at the final stage positive output terminal Q according to the differential clock signal and the intermediate stage positive output signal of the intermediate stage differential output signal received from the intermediate stage positive output terminal A. The second negative driving circuit 522 is coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal, and the final stage positive output signal Q of the final stage differential output signal. and the final stage negative output terminal in the final stage differential output terminal , used according to the differential clock signal, and from the negative output terminal of the intermediate stage The intermediate stage negative output signal in the received intermediate stage differential output signal is output at the negative output terminal of the final stage. A final stage negative output signal is generated in the final stage differential output signal.

[0114] like Figure 5 As shown, in the exemplary embodiment, the second positive driving circuit 521 includes a fifth driving PMOS P15, a sixth driving PMOS P16, a fifth driving NMOS N15 and a sixth driving NMOS N16. The gate of the fifth driving PMOS P15 is coupled to the negative clock terminal of the differential clock terminal. , the source of the fifth driving PMOS P15 is coupled to the power supply. The gate of the sixth driving PMOS P16 is coupled to the intermediate stage positive output terminal A, and the source of the sixth driving PMOS P16 is coupled to the drain of the fifth driving PMOS P15. The gate of the fifth driving NMOS N15 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the fifth driving NMOS N15 is grounded. The gate of the sixth driving NMOS N16 is coupled to the intermediate stage positive output terminal A, the source of the sixth driving NMOS N16 is coupled to the drain of the fifth driving NMOS N15, and the drain of the sixth driving NMOS N16 is coupled to the drain of the sixth driving PMOS P16 and coupled to the final stage positive output terminal Q. It can be seen that the second positive driving circuit 521 composed of the fifth driving PMOS P15, the sixth driving PMOS P16, the fifth driving NMOS N15 and the sixth driving NMOS N16 is equivalent to a three-state gate circuit, wherein the differential clock terminal is equivalent to the enable terminal of the three-state gate, the intermediate stage positive output terminal A is equivalent to the input terminal of the three-state gate, and the final stage positive output terminal Q is equivalent to the output terminal of the three-state gate. According to the working principle of the three-state gate circuit, in the second positive driving circuit 521: when the positive clock signal received at the positive clock end of the differential clock end is at a low level (that is, the negative clock signal received at the negative clock end of the differential clock end is at a high level), the fifth driving PMOS P15 and the fifth driving NMOS N15 are turned off, and the final positive output terminal Q is in a high impedance state because it is disconnected from both the power supply and the ground; when the positive clock signal received at the positive clock end of the differential clock end is at a high level (that is, the negative clock signal received at the negative clock end of the differential clock end is at a low level), the fifth driving PMOS P15 and the fifth driving NMOS N15 are turned on, and then the sixth driving PMOS P16 and the sixth driving NMOS N16 form an inverter, and at this time, the signal at the intermediate positive output terminal A is inverted through the second positive driving circuit 521 and output from the final positive output terminal Q. It can be seen that at the rising edge of the positive clock signal received at the positive clock end of the differential clock end, the state of the final stage positive output terminal Q will be flipped due to the activation of the second positive drive circuit 521 which is a three-state gate circuit, and then the signal state of the intermediate stage positive output terminal A will be output from the final stage positive output terminal Q (the signal of the final stage positive output terminal Q is opposite to the signal of the intermediate stage positive output terminal A).

[0115] like Figure 5 As shown, in the exemplary embodiment, the second negative driving circuit 522 includes a seventh driving PMOS P17, an eighth driving PMOS P18, a seventh driving NMOS N17 and an eighth driving NMOS N18. The gate of the seventh driving PMOS P17 is coupled to the negative clock terminal of the differential clock terminal. The source of the seventh driving PMOS P17 is coupled to the power supply. The gate of the eighth driving PMOS P18 is coupled to the intermediate stage negative output terminal The source of the eighth driving PMOS P18 is coupled to the drain of the seventh driving PMOS P17. The gate of the seventh driving NMOS N17 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the seventh driving NMOS N17 is grounded. The gate of the eighth driving NMOS N18 is coupled to the intermediate stage negative output terminal The source of the eighth driving NMOS N18 is coupled to the drain of the seventh driving NMOS N17, the drain of the eighth driving NMOS N18 is coupled to the drain of the eighth driving PMOS P18 and coupled to the final stage negative output terminal It can be seen that the second negative drive circuit 522 composed of the seventh drive PMOS P17, the eighth drive PMOS P18, the seventh drive NMOS N17 and the eighth drive NMOS N18 is equivalent to a three-state gate circuit, in which the differential clock terminal is equivalent to the enable terminal of the three-state gate, and the intermediate stage negative output terminal is equivalent to the enable terminal of the three-state gate. Equivalent to the input end of the three-state gate, the negative output end of the final stage According to the working principle of the tri-state gate circuit, in the second negative driving circuit 522: when the positive clock signal received at the positive clock end of the differential clock end is at a low level (that is, the negative clock signal received at the negative clock end of the differential clock end is at a high level), the seventh driving PMOS P17 and the seventh driving NMOS N17 are turned off, and the final negative output end Because it is disconnected from the power supply and the ground, it is in a high impedance state; when the positive clock signal received at the positive clock end of the differential clock end is at a high level (that is, the negative clock signal received at the negative clock end of the differential clock end is at a low level), the seventh drive PMOS P17 and the seventh drive NMOS N17 are turned on, and then the eighth drive PMOS P18 and the eighth drive NMOS N18 form an inverter. At this time, the intermediate stage negative output terminal The signal is inverted by the second negative drive circuit 522 and output from the negative output terminal of the final stage Output. It can be seen that at the rising edge of the positive clock signal received at the positive clock end of the differential clock end, the final negative output end The state of the negative output terminal of the intermediate stage will be reversed due to the opening of the second negative drive circuit 522 as a three-state gate circuit, thereby The signal state is from the negative output terminal of the final stage Output (final negative output terminal The signal is connected to the negative output terminal of the intermediate stage opposite signal).

[0116] It can be seen from the above description that at the rising edge of the differential clock signal, the final differential output terminal will flip due to the opening of the second driving stage circuit 52, and then the signal state at the intermediate differential output terminal will be output from the final differential output terminal, wherein the final positive output terminal Q outputs the state opposite to the intermediate positive output signal in the intermediate differential output signal at the rising edge of the differential clock signal, and the final negative output terminal The output is a state in which the rising edge timing of the differential clock signal is opposite to the intermediate stage negative output signal in the intermediate stage differential output signal.

[0117] It can be seen that in the embodiment of the present disclosure, the first driving stage circuit 51 and the second driving stage circuit 52, under the control of the differential clock signal, implement delay and two-time inversion of the differential input signal.

[0118] Figure 5 The fully differential DFF trigger of the illustrated embodiment uses eight driving PMOS and eight driving NMOS to form a structurally symmetrical driving circuit structure, thereby achieving the combination of differential input signals and differential clock signals to obtain intermediate differential output signals and final differential output signals.

[0119] The fully differential DFF trigger of the embodiment of the present disclosure processes differential input signals, and therefore provides a circuit that can be implemented for the frequency division of differential clock signals. In addition, in subsequent embodiments of the present disclosure, the fully differential DFF trigger is used in conjunction with other logic devices to achieve various odd-number frequency divisions for differential clock signals at ultra-high operating frequencies and ultra-wide output frequency ranges.

[0120] In the exemplary embodiment, the device parameters of the first drive PMOS P11, the second drive PMOS P12, the third drive PMOS P13, the fourth drive PMOS P14, the fifth drive PMOS P15, the sixth drive PMOS P16, the seventh drive PMOS P17 and the eighth drive PMOS P18 are the same, and the device parameters of the first drive NMOS N11, the second drive NMOS N12, the third drive NMOS N13, the fourth drive NMOS N14, the fifth drive NMOS N15, the sixth drive NMOS N16, the seventh drive NMOS N17 and the eighth drive NMOS N18 are the same.

[0121] like Figure 5As shown, in the exemplary embodiment, the first positive driving circuit 511 and the second positive driving circuit 521 constitute a positive signal processing circuit for processing the positive input signal of the differential input signal, and the first negative driving circuit 512 and the second negative driving circuit 522 constitute a negative signal processing circuit for processing the negative input signal of the differential input signal, and the structures of the positive signal processing circuit and the negative signal processing circuit are the same. Furthermore, when the positive input signal and the negative input signal of the differential input signal simultaneously enter the fully differential DFF trigger of the disclosed embodiment, the states of each PMOS and NMOS in the positive signal processing circuit and the negative signal processing circuit change synchronously, thereby synchronously generating a pair of intermediate-stage differential output signals, namely, an intermediate-stage positive output signal and an intermediate-stage negative output signal, and synchronously generating a pair of final-stage differential output signals, namely, a final-stage positive output signal and a final-stage negative output signal, which helps to ensure the synchronization of the differential signals.

[0122] like Figure 5 As shown, taking the first positive driving circuit 511 and the second positive driving circuit 521 as an example, in the first positive driving circuit 511, the second driving PMOS P12 and the second driving NMOS N12 form an inverter, and in the second positive driving circuit 521, the sixth driving PMOS P16 and the sixth driving NMOS N16 form an inverter. It can be seen that the inverter composed of the second driving PMOS P12 and the second driving NMOS N12, and the inverter composed of the sixth driving PMOS P16 and the sixth driving NMOS N16 form a two-stage inverter. Similarly, the first negative driving circuit 512 and the second negative driving circuit 522 also have two-stage inverters with the same structure. This DFF trigger composed of two-stage inverters is a fully dynamic inverter, which has a fast response speed to signals. In this structure, the output end of the inverter composed of the second driving PMOS P12 and the second driving NMOS N12 in the first positive driving circuit 511 is the intermediate positive output terminal A, and the output end of the inverter composed of the fourth driving PMOS P14 and the fourth driving NMOS N14 in the first negative driving circuit 512 is the intermediate negative output terminal In this fully dynamic inverter, the intermediate stage positive output terminal A and the intermediate stage negative output terminal , because the load of the fully differential DFF trigger circuit composed of CMOS devices is relatively small, and the response to the differential input signal is very fast, but at the same time, the parasitic capacitance of the intermediate node is relatively small, and the CMOS device is difficult to maintain the signal for a long time due to the existence of leakage. The same problem exists, especially when using advanced fin-gate transistors (FinFET), because the leakage current of the fin gate is larger than that of traditional transistors, it is even less suitable for lower speed (frequency) signal response.

[0123] Based on the above situation, the embodiments of the present disclosure are Figure 5 Based on the fully differential DFF trigger shown, a second fully differential DFF trigger is provided to meet the requirements of lower speed (frequency) signals. Although the performance of the fully differential DFF trigger under certain high-frequency signals may be sacrificed, the fully differential DFF trigger can be exchanged for adaptability to a wider frequency range.

[0124] Figure 6 is a schematic diagram of a circuit structure of another fully differential DFF trigger according to an exemplary embodiment, such as Figure 6 As shown, the fully differential DFF flip-flop is Figure 5 The fully differential DFF trigger of the embodiment shown in the figure adds a latch circuit based on the DFF trigger. Figure 5 In addition to the same circuit structure, Figure 6 The fully differential DFF trigger shown further includes a first latch circuit 61 and a second latch circuit 62. The first latch circuit 61 is coupled to the differential clock terminal and the intermediate differential output terminal, and is used to latch the intermediate differential output signal, wherein the signal driving capability of the first latch circuit 61 is lower than the signal driving capability of the first driver circuit 51. The second latch circuit 62 is coupled to the differential clock terminal and the final differential output terminal, and is used to latch the final differential output signal, wherein the signal driving capability of the second latch circuit 62 is lower than the signal driving capability of the second driver circuit 52.

[0125] Figure 6 The fully differential DFF trigger of the embodiment shown uses the first latch circuit 61 added after the first driving stage circuit 51 and the second latch circuit 62 added after the second driving stage circuit 52 to increase the parasitic capacitance at the intermediate node and the final node. During the operation of the fully differential DFF trigger, the first latch circuit 61 and the second latch circuit 62 will continuously replenish the charge of the intermediate node and the final node to offset the influence of the leakage current. Although the addition of the latch circuit will weaken the processing capability of high-frequency signals, it will enhance the processing capability of low-frequency signals. Compared with Figure 5 For the fully differential DFF trigger of the embodiment shown, Figure 6 The fully differential DFF trigger has a wider operating frequency range.

[0126] like Figure 6As shown, in the exemplary embodiment, the first latch circuit 61 includes a first positive latch circuit 611 and a first negative latch circuit 612. The first positive latch circuit 611 is coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal, and the intermediate stage negative output terminal. and the intermediate stage positive output terminal A in the intermediate stage differential output terminal, for outputting the differential clock signal from the intermediate stage negative output terminal The first negative latch circuit 612 is coupled to the differential clock terminal, the intermediate stage negative output terminal, and the intermediate stage positive output signal in the intermediate stage differential output signal generated by the intermediate stage positive output terminal A. and the intermediate stage positive output terminal A, for providing a differential clock signal to the intermediate stage negative output terminal according to the differential clock signal and the intermediate stage positive output signal received from the intermediate stage positive output terminal A. The intermediate stage negative output signal among the generated intermediate stage differential output signals is latched.

[0127] like Figure 6 As shown, in the exemplary embodiment, the first positive latch circuit 611 includes a first latch PMOS P21, a second latch PMOS P22, a first latch NMOS N21 and a second latch NMOS N22. The gate of the first latch PMOS P21 is coupled to the negative clock terminal of the differential clock terminal. The source of the first latch PMOS P21 is coupled to the power supply. The gate of the second latch PMOS P22 is coupled to the intermediate stage negative output terminal. The source of the second latch PMOS P22 is coupled to the drain of the first latch PMOS P21. The gate of the first latch NMOS N21 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the first latch NMOS N21 is grounded. The gate of the second latch NMOS N22 is coupled to the intermediate stage negative output terminal , the source of the second latch NMOS N22 is coupled to the drain of the first latch NMOS N21, and the drain of the second latch NMOS N22 is coupled to the drain of the second latch PMOS P22 and coupled to the intermediate stage positive output terminal A. The working principle of the first positive latch circuit 611 can refer to the working principle of the second positive driving circuit 521.

[0128] like Figure 6 As shown, in the exemplary embodiment, the first negative latch circuit 612 includes a third latch PMOS P23, a fourth latch PMOS P24, a third latch NMOS N23 and a fourth latch NMOS N24. The gate of the third latch PMOS P23 is coupled to the negative clock terminal of the differential clock terminal. , the source of the third latch PMOS P23 is coupled to the power supply. The gate of the fourth latch PMOS P24 is coupled to the intermediate stage positive output terminal A, and the source of the fourth latch PMOS P24 is coupled to the drain of the third latch PMOS P23. The gate of the third latch NMOS N23 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the third latch NMOS N23 is grounded. The gate of the fourth latch NMOS N24 is coupled to the intermediate stage positive output terminal A, the source of the fourth latch NMOS N24 is coupled to the drain of the third latch NMOS N23, and the drain of the fourth latch NMOS N24 is coupled to the drain of the fourth latch PMOS P24 and coupled to the intermediate stage negative output terminal. The working principle of the first negative latch circuit 612 may refer to the working principle of the second negative drive circuit 522 .

[0129] like Figure 6 As shown, in the exemplary embodiment, the second latch circuit 62 includes a second positive latch circuit 621 and a second negative latch circuit 622. The second positive latch circuit 621 is coupled to the differential clock terminal, the final negative output terminal of the final differential output terminal, and the final positive output terminal of the final differential output terminal. and the final stage positive output terminal Q in the final stage differential output terminal, used to generate a differential clock signal according to the differential clock signal, and from the final stage negative output terminal The second negative latch circuit 622 is coupled to the differential clock terminal, the final stage negative output terminal, and the final stage positive output signal in the final stage differential output signal generated by the final stage positive output terminal Q. and the final stage positive output terminal Q, for the final stage negative output terminal according to the differential clock signal and the final stage positive output signal received from the final stage positive output terminal Q The final stage negative output signal of the generated final stage differential output signal is latched.

[0130] like Figure 6 As shown, in the exemplary embodiment, the second positive latch circuit 621 includes a fifth latch PMOS P25, a sixth latch PMOS P26, a fifth latch NMOS N25 and a sixth latch NMOS N26. The gate of the fifth latch PMOS P25 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the fifth latch PMOS P25 is coupled to the power supply. The gate of the sixth latch PMOS P26 is coupled to the final negative output terminal The source of the sixth latch PMOS P26 is coupled to the drain of the fifth latch PMOS P25. The gate of the fifth latch NMOS N25 is coupled to the negative clock terminal of the differential clock terminal. The source of the fifth latch NMOS N25 is grounded. The gate of the sixth latch NMOS N26 is coupled to the negative output terminal of the final stage. The source of the sixth latch NMOS N26 is coupled to the drain of the fifth latch NMOS N25, and the drain of the sixth latch NMOS N26 is coupled to the drain of the sixth latch PMOS P26 and coupled to the final positive output terminal Q. The working principle of the second positive latch circuit 621 can refer to the working principle of the first positive driving circuit 511.

[0131] like Figure 6 As shown, in the exemplary embodiment, the second negative latch circuit 622 includes a seventh latch PMOS P27, an eighth latch PMOS P28, a seventh latch NMOS N27 and an eighth latch NMOS N28. Among them, the gate of the seventh latch PMOS P27 is coupled to the positive clock terminal ck of the differential clock terminal, and the source of the seventh latch PMOS P27 is coupled to the power supply. The gate of the eighth latch PMOS P28 is coupled to the final stage positive output terminal Q, and the source of the eighth latch PMOS P28 is coupled to the drain of the seventh latch PMOS P27. The gate of the seventh latch NMOS N27 is coupled to the negative clock terminal of the differential clock terminal. The source of the seventh latch NMOS N27 is grounded. The gate of the eighth latch NMOS N28 is coupled to the final positive output terminal Q, the source of the eighth latch NMOS N28 is coupled to the drain of the seventh latch NMOS N27, and the drain of the eighth latch NMOS N28 is coupled to the drain of the eighth latch PMOS P28 and coupled to the final negative output terminal. The working principle of the second negative latch circuit 622 may refer to the working principle of the second positive drive circuit 512 .

[0132] In the illustrative embodiment, the signal driving capability of each latch PMOS and each latch NMOS in the first latch circuit 61 and the second latch circuit 62 is lower than the signal driving capability of each drive PMOS and each drive NMOS in the first drive stage circuit 51 and the second drive stage circuit 52, thereby helping the intermediate node and the final node to maintain the signal state for a longer time and will not hinder the signal flipping of the intermediate node and the final node.

[0133] In an illustrative embodiment, the signal driving capabilities of each driving PMOS, each driving NMOS, each latching PMOS and each latching NMOS can be determined by relevant manufacturing parameters of the semiconductor device, such as realizing MOS devices with different signal driving capabilities by controlling the length and width of the channel.

[0134] Based on the fully differential DFF trigger of the embodiment of the present disclosure, an odd-number frequency division circuit capable of realizing an odd-number frequency division clock with a duty cycle of 50% can be designed, which can be applicable to the frequency division of high-speed, wide-frequency-range clock signals.

[0135] Figure 7is a schematic diagram of an odd-number frequency division circuit structure according to an exemplary embodiment, such as Figure 7 As shown, the odd-number frequency division circuit includes a clock signal transmission circuit 71, a first NOR gate nor0, a first NAND gate nand0 and a fully differential output stage circuit 72. The clock signal transmission circuit 71 includes a signal transmission chain composed of at least two fully differential DFF triggers DFF100 coupled in any one of the above embodiments, wherein in the signal transmission chain, the latter fully differential DFF trigger DFF100 (for example, Figure 7 The differential input terminal of the right fully differential DFF flip-flop DFF100 between two adjacent fully differential DFF flip-flops DFF100 is coupled to the previous fully differential DFF flip-flop DFF100 (eg Figure 7 The final differential output terminal of the left fully differential DFF trigger DFF100 between two adjacent fully differential DFF triggers DFF100 shown in the figure, the differential clock terminal of each fully differential DFF trigger DFF100 in the clock signal transmission circuit 71 receives the system differential clock signal. One input terminal of the first NOR gate nor0 is coupled to the last fully differential DFF trigger DFF100 (for example) in the clock signal transmission circuit 71 (signal transmission chain). Figure 7 The positive input terminal D of the differential input terminal of the rightmost fully differential DFF flip-flop DFF100 shown in the figure, the other input terminal of the first NOR gate nor0 is coupled to the final positive output terminal Q of the final differential output terminal of the last fully differential DFF flip-flop DFF100, and the output terminal of the first NOR gate nor0 is coupled to the first fully differential DFF flip-flop DFF100 (for example) in the signal transmission chain (clock signal transmission circuit 71). Figure 7 One input terminal of the first NAND gate nand0 is coupled to the negative input terminal of the differential input terminal of the last fully differential DFF flip-flop DFF100 in the signal transmission chain. The other input terminal of the first NAND gate nand0 is coupled to the final negative output terminal of the final differential output terminal of the last fully differential DFF trigger DFF100 in the signal transmission chain. The output terminal of the first NAND gate nand0 is coupled to the negative input terminal of the differential input terminal of the first fully differential DFF trigger DFF100 in the signal transmission chain. The fully differential output stage circuit 72 is coupled to the final differential output terminal and the intermediate differential output terminal of the last fully differential DFF flip-flop DFF100 in the signal transmission chain, and outputs an odd-numbered frequency-divided differential clock signal associated with the system differential clock signal according to the final differential output signal and the intermediate differential output signal output by the last fully differential DFF flip-flop DFF100 in the signal transmission chain.

[0136] like Figure 7 As shown, in the exemplary embodiment, the fully differential output stage circuit 72 includes a second NOR gate nor1 and a second NAND gate nand1. One input terminal of the second NOR gate nor1 is coupled to the final positive output terminal Q of the final differential output terminal of the last fully differential DFF flip-flop DFF100 in the signal transmission chain, and the other input terminal of the second NOR gate nor1 is coupled to the intermediate negative output terminal Q of the intermediate differential output terminal of the last fully differential DFF flip-flop DFF100 in the signal transmission chain. The output terminal of the second NOR gate nor1 outputs the positive clock signal ckop of the odd-numbered frequency-divided differential clock signal. One input terminal of the second NAND gate nand1 is coupled to the final negative output terminal of the final differential output terminal of the last fully differential DFF flip-flop DFF100 in the signal transmission chain. The other input end of the second NAND gate nand1 is coupled to the intermediate stage positive output end A of the intermediate stage differential output end of the last fully differential DFF trigger DFF100 in the signal transmission chain, and the output end of the second NAND gate nand1 outputs the negative clock signal ckon of the odd-numbered frequency-divided differential clock signal.

[0137] like Figure 7 As shown, in the exemplary embodiment, the fully differential output stage circuit 72 further includes a cross couple 721 , and the cross couple 721 is coupled between the output terminal of the second NOR gate nor1 and the output terminal of the second NAND gate nand1 .

[0138] like Figure 7 As shown, in the exemplary embodiment, the cross-coupling pair 721 includes a first inverter inv0 and a second inverter inv1. The input end of the first inverter inv0 is coupled to the output end of the second NOR gate nor1, and the output end of the first inverter inv0 is coupled to the output end of the second NAND gate nand1. The input end of the second inverter inv1 is coupled to the output end of the second NAND gate nand1, and the output end of the second inverter inv1 is coupled to the output end of the second NOR gate nor1.

[0139] The function of the cross-coupling pair 721 is to calibrate the differential signal outputted by the output end of the second NOR gate nor1 and the output end of the second NAND gate nand1. Ideally, the signal outputted by the second NOR gate nor1 and the signal outputted by the second NAND gate nand1 should be inverted and synchronously flipped. However, the second NOR gate nor1 and the second NAND gate nand1 have different logics and circuit structures, which will cause the flipping time of the pair of signals to be different and thus the differential property will be weakened. After adding the cross-coupling pair 721, the differential performance of the differential signal can be improved.

[0140] The odd-number frequency division circuit disclosed in the present invention is further described below in conjunction with two specific circuits.

[0141] Figure 8 is a schematic diagram of a three-frequency division circuit structure according to an exemplary embodiment. Figure 8 As shown, the clock signal transmission circuit 71 of the three-frequency division circuit includes a signal transmission chain composed of a first fully differential DFF trigger DFF101 and a second fully differential DFF trigger DFF102 coupled together, wherein the differential input terminal of the second fully differential DFF trigger DFF102 is coupled to the final differential output terminal of the first fully differential DFF trigger DFF101, specifically, the positive input terminal D of the second fully differential DFF trigger DFF102 is coupled to the final positive output terminal Q of the first fully differential DFF trigger DFF101, and the negative input terminal Q of the second fully differential DFF trigger DFF102 is coupled to the final positive output terminal Q of the first fully differential DFF trigger DFF101. coupled to the final negative output terminal of the first fully differential DFF flip-flop DFF101 . The differential clock end of the first fully differential DFF trigger DFF101 and the differential clock end of the second fully differential DFF trigger DFF102 both receive the system differential clock signal. One input end of the first NOR gate nor0 is coupled to the positive input end D of the differential input end of the second fully differential DFF trigger DFF102, the other input end of the first NOR gate nor0 is coupled to the final positive output end Q of the final differential output end of the second fully differential DFF trigger DFF102, and the output end of the first NOR gate nor0 is coupled to the positive input end D of the differential input end of the first fully differential DFF trigger DFF101. One input end of the first NAND gate nand0 is coupled to the negative input end of the differential input end of the second fully differential DFF trigger DFF102. The other input terminal of the first NAND gate nand0 is coupled to the final negative output terminal of the final differential output terminal of the second fully differential DFF flip-flop DFF102. The output terminal of the first NAND gate nand0 is coupled to the negative input terminal of the differential input terminal of the first fully differential DFF trigger DFF101. The fully differential output stage circuit 72 is coupled to the final differential output terminal and the intermediate differential output terminal of the second fully differential DFF flip-flop DFF102, and outputs a three-frequency differential clock signal (ckop, ckon) associated with the system differential clock signal according to the final differential output signal and the intermediate differential output signal output by the second fully differential DFF flip-flop DFF102.

[0142] One input terminal of the second NOR gate nor1 in the fully differential output stage circuit 72 is coupled to the final positive output terminal Q of the final differential output terminal of the second fully differential DFF flip-flop DFF102, and the other input terminal of the second NOR gate nor1 is coupled to the intermediate negative output terminal Q of the intermediate differential output terminal of the second fully differential DFF flip-flop DFF102. The output terminal of the second NOR gate nor1 outputs the positive clock signal ckop of the three-frequency differential clock signal. One input terminal of the second NAND gate nand1 in the fully differential output stage circuit 72 is coupled to the final negative output terminal of the final differential output terminal of the second fully differential DFF flip-flop DFF102. The other input end of the second NAND gate nand1 is coupled to the intermediate positive output end A of the intermediate differential output end of the second fully differential DFF flip-flop DFF102, and the output end of the second NAND gate nand1 outputs the negative clock signal ckon of the three-frequency differential clock signal.

[0143] Fig. 9 yes Figure 8 The timing diagram of the three-way frequency division circuit is shown in FIG. Fig. 9 As shown, a4 is the signal of the final positive output terminal Q of the second fully differential DFF trigger DFF102, and b4 is the signal of the final negative output terminal Q of the second fully differential DFF trigger DFF102. a4 and b4 can also be called the three-frequency differential clock signal output by the clock signal transmission circuit 71, a3 is the signal of the intermediate positive output terminal A of the second fully differential DFF trigger DFF102, and b3 is the signal of the intermediate negative output terminal signals, where a3 leads a4 by half a clock cycle and a3 and a4 are reversed, and b3 leads b4 by half a clock cycle and b3 and b4 are reversed. Therefore, a4 and b3 can be directly subjected to NOR logic through the second NOR gate nor1, and b4 and a3 can be subjected to NAND logic through the second NAND gate nand1 to generate a differential clock output with a 50% duty cycle (including the positive clock signal ckop and the negative clock signal ckon).

[0144] Fig.10 is a schematic diagram of a five-frequency division circuit structure according to an exemplary embodiment, such as Fig.10As shown, the clock signal transmission circuit 71 of the five-frequency division circuit includes a signal transmission chain composed of a first fully differential DFF trigger DFF101, a second fully differential DFF trigger DFF102 and a third fully differential DFF trigger DFF103, wherein the differential input terminal of the second fully differential DFF trigger DFF102 is coupled to the final differential output terminal of the first fully differential DFF trigger DFF101, and the differential input terminal of the third fully differential DFF trigger DFF103 is coupled to the final differential output terminal of the second fully differential DFF trigger DFF102. Specifically, the positive input terminal D of the second fully differential DFF trigger DFF102 is coupled to the final positive output terminal Q of the first fully differential DFF trigger DFF101, and the negative input terminal Q of the second fully differential DFF trigger DFF102 is coupled to the final positive output terminal Q of the first fully differential DFF trigger DFF101. coupled to the final negative output terminal of the first fully differential DFF flip-flop DFF101 The positive input terminal D of the third fully differential DFF trigger DFF103 is coupled to the final positive output terminal Q of the second fully differential DFF trigger DFF102, and the negative input terminal coupled to the negative output terminal of the final stage of the second fully differential DFF flip-flop DFF102 . The differential clock terminals of the first fully differential DFF trigger DFF101, the differential clock terminals of the second fully differential DFF trigger DFF102, and the differential clock terminals of the third fully differential DFF trigger DFF103 all receive the system differential clock signal. One input terminal of the first NOR gate nor0 is coupled to the positive input terminal D among the differential input terminals of the third fully differential DFF trigger DFF103, the other input terminal of the first NOR gate nor0 is coupled to the final positive output terminal Q among the final differential output terminals of the third fully differential DFF trigger DFF103, and the output terminal of the first NOR gate nor0 is coupled to the positive input terminal D among the differential input terminals of the first fully differential DFF trigger DFF101. One input terminal of the first NAND gate nand0 is coupled to the negative input terminal The other input terminal of the first NAND gate nand0 is coupled to the final negative output terminal of the final differential output terminal of the third fully differential DFF flip-flop DFF103. The output terminal of the first NAND gate nand0 is coupled to the negative input terminal of the differential input terminal of the first fully differential DFF trigger DFF101. The fully differential output stage circuit 72 is coupled to the final differential output terminal and the intermediate differential output terminal of the third fully differential DFF flip-flop DFF103, and outputs a five-frequency differential clock signal associated with the system differential clock signal according to the final differential output signal and the intermediate differential output signal output by the third fully differential DFF flip-flop DFF103.

[0145] One input terminal of the second NOR gate nor1 in the fully differential output stage circuit 72 is coupled to the final positive output terminal Q of the final differential output terminal of the third fully differential DFF flip-flop DFF103, and the other input terminal of the second NOR gate nor1 is coupled to the intermediate negative output terminal Q of the intermediate differential output terminal of the third fully differential DFF flip-flop DFF103. The output terminal of the second NOR gate nor1 outputs the positive clock signal ckop of the five-frequency differential clock signal. One input terminal of the second NAND gate nand1 in the fully differential output stage circuit 72 is coupled to the final negative output terminal of the final differential output terminal of the third fully differential DFF flip-flop DFF103. The other input end of the second NAND gate nand1 is coupled to the intermediate positive output end A of the intermediate differential output end of the third fully differential DFF flip-flop DFF103, and the output end of the second NAND gate nand1 outputs the negative clock signal ckon of the five-frequency differential clock signal.

[0146] According to the above Figure 7 , Figure 8 , Fig.10 By continuing to add different numbers of the fully differential DFF triggers DFF100 of the embodiments of the present disclosure, a higher odd frequency division circuit, a three-way frequency division circuit, and a five-way frequency division circuit can be achieved. Fig.10 Adding a fully differential DFF trigger DFF100 of the embodiment of the present disclosure on the basis of the present invention can achieve seven-frequency division. Fig.10 By adding two fully differential DFF triggers DFF100 of the disclosed embodiment, nine-frequency division can be achieved, etc. Moreover, the obtained odd-numbered frequency-divided clock signals are all clock signals with a duty cycle of 50%.

[0147] The fully differential DFF trigger and odd-number frequency division circuit of the disclosed embodiment can be applied to high operating frequency and wide frequency range, and have excellent differential output performance. The circuit structure of the fully differential DFF trigger and odd-number frequency division circuit adopts a fully differential symmetrical structure to ensure the output performance of the differential signal. In addition, the differential output performance can be further improved by adding a cross-coupling pair at the output stage. Using the fully differential DFF trigger and odd-number frequency division circuit of the disclosed embodiment, various odd-number frequency division clock output signals with a duty cycle of 50% such as three-way frequency division, five-way frequency division, seven-way frequency division, and nine-way frequency division can be realized.

[0148] An embodiment of the present disclosure further provides a chip, comprising the odd-number frequency division circuit of any one of the above embodiments.

[0149] An embodiment of the present disclosure also provides an electronic device, comprising the chip of the above embodiment.

[0150] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present disclosure, and will not be described in detail here.

[0151] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A fully differential DFF trigger for odd frequency division, characterized in that: The fully differential DFF trigger has a differential input terminal, an intermediate differential output terminal, a final differential output terminal and a differential clock terminal, wherein the differential clock terminal includes a positive clock terminal and a negative clock terminal, the positive clock terminal is used to receive a positive clock signal in a differential clock signal, and the negative clock terminal is used to receive a negative clock signal in a differential clock signal; The fully differential DFF trigger comprises: a first driver stage circuit, the first driver stage circuit being coupled to the differential clock terminal, the differential input terminal and the intermediate stage differential output terminal, and being configured to generate an intermediate stage differential output signal at the intermediate stage differential output terminal according to the positive clock signal and the negative clock signal in the differential clock signal received at the differential clock terminal and the differential input signal received at the differential input terminal; and a second driver stage circuit, the second driver stage circuit being coupled to the differential clock terminal, the intermediate stage differential output terminal and the final stage differential output terminal, and being configured to generate a final stage differential output signal at the final stage differential output terminal according to the positive clock signal and the negative clock signal in the differential clock signal and the intermediate stage differential output signal; The fully differential DFF trigger generates two pairs of required differential output signals at the intermediate differential output end and the final differential output end respectively.

2. The fully differential DFF trigger according to claim 1, characterized in that: The first driving stage circuit comprises: a first positive driving circuit, the first positive driving circuit being coupled to the differential clock terminal, the positive input terminal among the differential input terminals, and the intermediate positive output terminal among the intermediate differential output terminals, and being configured to generate an intermediate positive output signal among the intermediate differential output signals at the intermediate positive output terminal according to the differential clock signal and the positive input signal among the differential input signals received by the positive input terminal; A first negative driving circuit, the first negative driving circuit is coupled to the differential clock terminal, the negative input terminal of the differential input terminals and the intermediate negative output terminal of the intermediate differential output terminals, and is used for generating an intermediate negative output signal of the intermediate differential output signal at the intermediate negative output terminal according to the differential clock signal and the negative input signal of the differential input signal received by the negative input terminal.

3. The fully differential DFF trigger according to claim 2, characterized in that: The first positive driving circuit comprises: A first driving PMOS, wherein a gate of the first driving PMOS is coupled to the positive clock terminal, and a source of the first driving PMOS is coupled to a power supply; a second driving PMOS, wherein a gate of the second driving PMOS is coupled to the positive input terminal, and a source of the second driving PMOS is coupled to a drain of the first driving PMOS; A first driving NMOS, wherein a gate of the first driving NMOS is coupled to the negative clock terminal, and a source of the first driving NMOS is grounded; A second driving NMOS, wherein the gate of the second driving NMOS is coupled to the positive input terminal, the source of the second driving NMOS is coupled to the drain of the first driving NMOS, and the drain of the second driving NMOS is coupled to the drain of the second driving PMOS and coupled to the intermediate stage positive output terminal.

4. The fully differential DFF trigger according to claim 2, characterized in that: The first negative driving circuit comprises: a third driving PMOS, wherein a gate of the third driving PMOS is coupled to the positive clock terminal, and a source of the third driving PMOS is coupled to a power supply; a fourth driving PMOS, wherein a gate of the fourth driving PMOS is coupled to the negative input terminal, and a source of the fourth driving PMOS is coupled to a drain of the third driving PMOS; A third driving NMOS, wherein a gate of the third driving NMOS is coupled to the negative clock terminal, and a source of the third driving NMOS is grounded; a fourth driving NMOS, wherein the gate of the fourth driving NMOS is coupled to the negative input terminal, the source of the fourth driving NMOS is coupled to the drain of the third driving NMOS, and the drain of the fourth driving NMOS is coupled to the drain of the fourth driving PMOS and coupled to the intermediate stage negative output terminal.

5. The fully differential DFF trigger according to claim 1, characterized in that: The second driving stage circuit comprises: a second positive driving circuit, the second positive driving circuit being coupled to the differential clock terminal, the intermediate stage positive output terminal of the intermediate stage differential output terminals, and the final stage positive output terminal of the final stage differential output terminals, and being configured to generate a final stage positive output signal of the final stage differential output signal at the final stage positive output terminal according to the differential clock signal and the intermediate stage positive output signal of the intermediate stage differential output signal received from the intermediate stage positive output terminal; a second negative driving circuit, the second negative driving circuit is coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal and the final stage negative output terminal of the final stage differential output terminal, and is used for generating a final stage negative output signal of the final stage differential output signal at the final stage negative output terminal according to the differential clock signal and the intermediate stage negative output signal of the intermediate stage differential output signal received from the intermediate stage negative output terminal.

6. The fully differential DFF trigger according to claim 5, characterized in that: The second positive driving circuit comprises: a fifth driving PMOS, wherein a gate of the fifth driving PMOS is coupled to the negative clock terminal, and a source of the fifth driving PMOS is coupled to a power supply; a sixth driving PMOS, wherein a gate of the sixth driving PMOS is coupled to the intermediate stage positive output terminal, and a source of the sixth driving PMOS is coupled to a drain of the fifth driving PMOS; a fifth driving NMOS, wherein a gate of the fifth driving NMOS is coupled to the positive clock terminal, and a source of the fifth driving NMOS is grounded; a sixth driving NMOS, wherein the gate of the sixth driving NMOS is coupled to the intermediate stage positive output terminal, the source of the sixth driving NMOS is coupled to the drain of the fifth driving NMOS, and the drain of the sixth driving NMOS is coupled to the drain of the sixth driving PMOS and coupled to the final stage positive output terminal.

7. The fully differential DFF trigger according to claim 5, characterized in that: The second negative driving circuit comprises: a seventh driving PMOS, wherein a gate of the seventh driving PMOS is coupled to the negative clock terminal, and a source of the seventh driving PMOS is coupled to a power supply; an eighth driving PMOS, wherein a gate of the eighth driving PMOS is coupled to the intermediate stage negative output terminal, and a source of the eighth driving PMOS is coupled to a drain of the seventh driving PMOS; a seventh driving NMOS, wherein a gate of the seventh driving NMOS is coupled to the positive clock terminal, and a source of the seventh driving NMOS is grounded; an eighth driving NMOS, wherein the gate of the eighth driving NMOS is coupled to the intermediate stage negative output terminal, the source of the eighth driving NMOS is coupled to the drain of the seventh driving NMOS, and the drain of the eighth driving NMOS is coupled to the drain of the eighth driving PMOS and coupled to the final stage negative output terminal.

8. The fully differential DFF trigger according to claim 1, characterized in that: The fully differential DFF trigger further includes: a first latch circuit, the first latch circuit being coupled to the differential clock terminal and the intermediate stage differential output terminal and being used for latching the intermediate stage differential output signal, wherein the signal driving capability of the first latch circuit is lower than the signal driving capability of the first driving stage circuit; A second latch circuit, the second latch circuit is coupled to the differential clock terminal and the final differential output terminal, and is used to latch the final differential output signal, wherein the signal driving capability of the second latch circuit is lower than the signal driving capability of the second driving stage circuit.

9. The fully differential DFF trigger according to claim 8, characterized in that: The first latch circuit comprises: a first positive latch circuit, the first positive latch circuit being coupled to the differential clock terminal, the intermediate stage negative output terminal of the intermediate stage differential output terminal, and the intermediate stage positive output terminal of the intermediate stage differential output terminal, and being configured to latch the intermediate stage positive output signal of the intermediate stage differential output signal generated by the intermediate stage positive output terminal according to the differential clock signal and the intermediate stage negative output signal of the intermediate stage differential output signal received from the intermediate stage negative output terminal; A first negative latch circuit, the first negative latch circuit is coupled to the differential clock terminal, the intermediate stage negative output terminal and the intermediate stage positive output terminal, and is used for latching the intermediate stage negative output signal in the intermediate stage differential output signal generated by the intermediate stage negative output terminal according to the differential clock signal and the intermediate stage positive output signal received from the intermediate stage positive output terminal.

10. The fully differential DFF trigger according to claim 9, characterized in that: The first positive latch circuit comprises: A first latch PMOS, wherein a gate of the first latch PMOS is coupled to the negative clock terminal, and a source of the first latch PMOS is coupled to a power supply; a second latch PMOS, wherein a gate of the second latch PMOS is coupled to the intermediate stage negative output terminal, and a source of the second latch PMOS is coupled to a drain of the first latch PMOS; A first latch NMOS, wherein a gate of the first latch NMOS is coupled to the positive clock terminal, and a source of the first latch NMOS is grounded; A second latch NMOS, wherein the gate of the second latch NMOS is coupled to the intermediate stage negative output terminal, the source of the second latch NMOS is coupled to the drain of the first latch NMOS, and the drain of the second latch NMOS is coupled to the drain of the second latch PMOS and coupled to the intermediate stage positive output terminal.

11. The fully differential DFF trigger according to claim 9, characterized in that: The first negative latch circuit comprises: a third latch PMOS, wherein a gate of the third latch PMOS is coupled to the negative clock terminal, and a source of the third latch PMOS is coupled to a power supply; a fourth latch PMOS, wherein a gate of the fourth latch PMOS is coupled to the intermediate stage positive output terminal, and a source of the fourth latch PMOS is coupled to a drain of the third latch PMOS; a third latch NMOS, wherein a gate of the third latch NMOS is coupled to the positive clock terminal, and a source of the third latch NMOS is grounded; A fourth latch NMOS, wherein the gate of the fourth latch NMOS is coupled to the intermediate stage positive output terminal, the source of the fourth latch NMOS is coupled to the drain of the third latch NMOS, and the drain of the fourth latch NMOS is coupled to the drain of the fourth latch PMOS and coupled to the intermediate stage negative output terminal.

12. The fully differential DFF trigger according to claim 8, characterized in that: The second latch circuit comprises: a second positive latch circuit, the second positive latch circuit being coupled to the differential clock terminal, the final negative output terminal of the final differential output terminals, and the final positive output terminal of the final differential output terminals, and being configured to latch the final positive output signal of the final differential output signal generated by the final positive output terminal according to the differential clock signal and the final negative output signal of the final differential output signal received from the final negative output terminal; A second negative latch circuit, the second negative latch circuit is coupled to the differential clock terminal, the final stage negative output terminal and the final stage positive output terminal, and is used to latch the final stage negative output signal in the final stage differential output signal generated by the final stage negative output terminal according to the differential clock signal and the final stage positive output signal received from the final stage positive output terminal.

13. The fully differential DFF trigger according to claim 12, characterized in that: The second positive latch circuit comprises: a fifth latch PMOS, wherein a gate of the fifth latch PMOS is coupled to the positive clock terminal, and a source of the fifth latch PMOS is coupled to a power supply; a sixth latch PMOS, wherein a gate of the sixth latch PMOS is coupled to the final negative output terminal, and a source of the sixth latch PMOS is coupled to a drain of the fifth latch PMOS; a fifth latch NMOS, wherein a gate of the fifth latch NMOS is coupled to the negative clock terminal, and a source of the fifth latch NMOS is grounded; A sixth latch NMOS, wherein the gate of the sixth latch NMOS is coupled to the final stage negative output terminal, the source of the sixth latch NMOS is coupled to the drain of the fifth latch NMOS, and the drain of the sixth latch NMOS is coupled to the drain of the sixth latch PMOS and coupled to the final stage positive output terminal.

14. The fully differential DFF trigger according to claim 12, characterized in that: The second negative latch circuit comprises: a seventh latch PMOS, wherein a gate of the seventh latch PMOS is coupled to the positive clock terminal, and a source of the seventh latch PMOS is coupled to a power supply; an eighth latch PMOS, wherein a gate of the eighth latch PMOS is coupled to the final-stage positive output terminal, and a source of the eighth latch PMOS is coupled to a drain of the seventh latch PMOS; a seventh latch NMOS, wherein a gate of the seventh latch NMOS is coupled to the negative clock terminal, and a source of the seventh latch NMOS is grounded; An eighth latch NMOS, wherein the gate of the eighth latch NMOS is coupled to the final stage positive output terminal, the source of the eighth latch NMOS is coupled to the drain of the seventh latch NMOS, and the drain of the eighth latch NMOS is coupled to the drain of the eighth latch PMOS and coupled to the final stage negative output terminal.

15. An odd-number frequency division circuit, characterized in that: include: A clock signal transmission circuit, comprising a signal transmission chain consisting of at least two coupled fully differential DFF triggers as claimed in any one of claims 1 to 14, wherein in the signal transmission chain, the differential input terminal of the latter fully differential DFF trigger between two adjacent fully differential DFF triggers is coupled to the final differential output terminal of the former fully differential DFF trigger, and the differential clock terminal of each of the fully differential DFF triggers in the clock signal transmission circuit receives a system differential clock signal; a first NOR gate, wherein one input terminal of the first NOR gate is coupled to a positive input terminal among differential input terminals of a last fully differential DFF flip-flop in the signal transmission chain, another input terminal of the first NOR gate is coupled to a final positive output terminal among final differential output terminals of the last fully differential DFF flip-flop, and an output terminal of the first NOR gate is coupled to a positive input terminal among differential input terminals of a first fully differential DFF flip-flop in the signal transmission chain; a first NAND gate, wherein one input terminal of the first NAND gate is coupled to a negative input terminal of the differential input terminals of the last fully differential DFF trigger, another input terminal of the first NAND gate is coupled to a final negative output terminal of a final differential output terminal of the last fully differential DFF trigger, and an output terminal of the first NAND gate is coupled to a negative input terminal of the differential input terminals of the first fully differential DFF trigger; A fully differential output stage circuit, wherein the fully differential output stage circuit is coupled to the final differential output terminal and the intermediate differential output terminal of the last fully differential DFF trigger, and outputs an odd-numbered frequency-divided differential clock signal associated with the system differential clock signal according to the final differential output signal and the intermediate differential output signal output by the last fully differential DFF trigger.

16. The odd-number frequency division circuit according to claim 15, characterized in that: The fully differential output stage circuit comprises: a second NOR gate, wherein one input terminal of the second NOR gate is coupled to a final positive output terminal of a final differential output terminal of the last fully differential DFF flip-flop, another input terminal of the second NOR gate is coupled to an intermediate negative output terminal of an intermediate differential output terminal of the last fully differential DFF flip-flop, and an output terminal of the second NOR gate outputs a positive clock signal of the odd-numbered frequency-divided differential clock signal; A second NAND gate, one input end of the second NAND gate is coupled to the final negative output end of the final differential output end of the last fully differential DFF trigger, the other input end of the second NAND gate is coupled to the intermediate positive output end of the intermediate differential output end of the last fully differential DFF trigger, and the output end of the second NAND gate outputs the negative clock signal of the odd-numbered frequency-divided differential clock signal.

17. The odd-number frequency division circuit according to claim 16, characterized in that: The fully differential output stage circuit further includes: A cross-coupling pair is coupled between an output terminal of the second NOR gate and an output terminal of the second NAND gate.

18. The odd-number frequency division circuit according to claim 17, characterized in that: The cross-coupling pair comprises: A first inverter, wherein an input terminal of the first inverter is coupled to an output terminal of the second NOR gate, and an output terminal of the first inverter is coupled to an output terminal of the second NAND gate; A second inverter, wherein an input terminal of the second inverter is coupled to an output terminal of the second NAND gate, and an output terminal of the second inverter is coupled to an output terminal of the second NOR gate.

19. A chip, characterized in that: The method comprises the odd-number frequency dividing circuit as claimed in any one of claims 15 to 18.

20. An electronic device, characterized in that: Comprising the chip as claimed in claim 19.

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