A method and device for encoding and reading rotation factors, a medium and a chip

Abstract

The present application discloses a device and method for encoding and reading rotation factors, a medium and a chip. The encoding device includes: a first acquisition module, used to obtain the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation; determine the various rotation factors required for the data to be processed in each stage of the inverse number theory transformation; obtain the target storage rotation factor of each stage; an encoding module, used to construct a storage mapping relationship between the target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to preset conditions. After the encoding device in the present application constructs the storage mapping relationship, when storing each rotation factor based on the storage mapping relationship, it can exclude redundant rotation factors in each stage, thereby reducing the storage space overhead of the rotation factor.

Description

Technical Field

[0001] The present application relates to the field of data processing, and in particular to a method and device for encoding and reading a rotation factor, a medium and a chip. Background Art

[0002] With the continuous development of artificial intelligence and big data algorithms, protecting data security and privacy is becoming increasingly important. Using encryption algorithms to encrypt data is an important way to protect data security. At present, mainstream privacy computing technologies such as Fully Homomorphic Encryption (FHE) and Zero Knowledge Proof (ZKP) involve a large number of polynomial multiplication calculations. If calculated directly, the complexity is relatively high. For example, the time complexity of multiplying two polynomials of length N is O(N²). The Inverse Fast Number Theoretic Transform (INTT) can optimize the calculation of polynomial multiplication and reduce its time complexity to O(Nlog2N). Among them, INTT is an equivalent form of Fast Fourier Transform (FFT) in the field of number theory, which performs transformations under finite fields.

[0003] The calculation speed of INTT is an important factor affecting the efficiency of privacy computing. Currently, most hardware circuits are used to accelerate INTT in parallel. For example, field programmable gate arrays (FPGAs) are used to accelerate INTT in parallel. However, the on-chip resources of mainstream FPGA products on the market are limited. For large integer and large-scale INTT calculations, storage resources are often the bottleneck for improving their calculation speed. Static random access memory (SRAM) on FPGA can be divided into single-port and dual-port. Single-port SRAM has higher area efficiency. Therefore, under the premise of limited resources, single-port SRAM is usually used. However, single-port SRAM can only be read and written once in the same clock cycle, and cannot be read and written multiple times, so the serial calculation speed is slow.

[0004] In order to improve the calculation speed and reduce the calculation cycle, the prior art often adopts a method of parallel operation of multiple single-port SRAMs. When parallel operation is performed, each single-port SRAM needs to obtain a rotation factor. Therefore, the rotation factor required for K parallelism is K times that of serial calculation. In the case of high parallelism, the storage space overhead of the rotation factor is huge. Summary of the invention

[0005] The main purpose of this application is to propose a method and device for encoding and reading rotation factors, a medium and a chip, aiming to solve the problem of large storage space overhead of rotation factors in the current inverse number theory transformation.

[0006] To achieve the above object, the present application proposes a rotation factor encoding device for an inverse number theory transformation circuit, the encoding device comprising:

[0007] A first acquisition module is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation;

[0008] Based on the operation information, determining each rotation factor required for each stage of the inverse number theory transformation of the data to be processed;

[0009] Determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtain the target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage;

[0010] The encoding module is used to construct a storage mapping relationship between a target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to preset conditions.

[0011] In an embodiment of the present application, the first acquisition module is configured to determine each rotation factor in any polynomial group in any stage according to the following formula:

[0012] ;

[0013] Wherein, N represents the sequence length of the data to be processed, r represents the stage of the inverse number theory transformation of the data to be processed, j represents the j-th butterfly calculation in any polynomial group in the stage r of the inverse number theory transformation of the data to be processed, Represents the rotation factors required for the j-th butterfly calculation in any polynomial group in stage r of the inverse number theory transformation of the data to be processed.

[0014] In an embodiment of the present application, the first acquisition module is configured to determine the redundant rotation factors of the to-be-processed data in each stage of the inverse number theory transformation based on the following method, and obtain the target storage rotation factor of each stage:

[0015] In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage;

[0016] If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

[0017] In an embodiment of the present application, the encoding module is configured to construct a storage mapping relationship based on the following method:

[0018] Get candidate twiddle factors from the target stored twiddle factors of each stage;

[0019] Converting the index of the candidate conversion factor into a binary code;

[0020] Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed;

[0021] Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

[0022] In an embodiment of the present application, the encoding module is configured to determine the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed based on the following method:

[0023] Determine the number of bits of the first code 1 from the low bit to the high bit of the binary code, where the number of bits starts from zero;

[0024] The number of bits is used as the candidate rotation factor to participate in the highest stage of the operation, and the rotation factors are all involved in the operation from the highest stage to the lowest stage.

[0025] In the embodiment of the present application, the encoding module is configured as follows:

[0026] When r∈[0,b-1], x_w=(i_rev>>r)>>(nbr-1), y_w= +(i_rev>>r)% ;

[0027] When r∈[b,n-1], x_w=( )>>(n- )+(( i_rev>>r)>>(n- )),

[0028] like >>(n- )=0, then y_w= +(i_rev >> r);

[0029] like >>(n- )≠0, then y_w=(i_rev>>r)% ;

[0030] Wherein, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the stage of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

[0031] The embodiment of the present application further provides a method for encoding a rotation factor, which is used in the device for encoding the rotation factor described in any of the above embodiments. The encoding method includes:

[0032] Based on the first acquisition module, obtaining operation information of the data to be processed, the operation information including the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation;

[0033] Based on the operation information, determining each rotation factor required for each stage of the inverse number theory transformation of the data to be processed;

[0034] Determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtain the target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage;

[0035] Based on the encoding module, a storage mapping relationship between a target storage twiddle factor in each stage and each static random access memory for storing the twiddle factor is constructed according to preset conditions.

[0036] In an embodiment of the present application, determining the various rotation factors required for the data to be processed in various stages of the inverse number theory transformation based on the operation information includes:

[0037] The rotation factors in any polynomial group at any stage are determined as follows:

[0038] ;

[0039] Wherein, N represents the sequence length of the data to be processed, r represents the stage of the inverse number theory transformation of the data to be processed, j represents the j-th butterfly calculation in any polynomial group in the stage r of the inverse number theory transformation of the data to be processed, Represents the rotation factors required for the j-th butterfly calculation in any polynomial group in stage r of the inverse number theory transformation of the data to be processed.

[0040] In an embodiment of the present application, determining the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation and obtaining the target storage rotation factors of each stage includes:

[0041] In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage;

[0042] If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

[0043] In the embodiment of the present application, the step of constructing a storage mapping relationship between a target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to a preset condition includes:

[0044] Get candidate twiddle factors from the target stored twiddle factors in each stage;

[0045] Converting the index of the candidate conversion factor into a binary code;

[0046] Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed;

[0047] Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

[0048] In the embodiment of the present application, the determining, based on the binary code, of the candidate rotation factors participating in the various stages of the operation in the inverse number theory transformation of the data to be processed includes:

[0049] Determine the number of bits of the first code 1 from the low bit to the high bit of the binary code, where the number of bits starts from zero;

[0050] The number of bits is used as the candidate rotation factor to participate in the highest stage of the operation, and the rotation factors are all involved in the operation from the highest stage to the lowest stage.

[0051] In the embodiment of the present application, the storage mapping relationship corresponding to the candidate rotation factor at each stage is constructed based on the stages in which the candidate rotation factor participates in the operation, including:

[0052] When r∈[0,b-1], x_w=(i_rev>>r)>>(nbr-1), y_w= +(i_rev>>r)% ;

[0053] When r∈[b,n-1], x_w=( )>>(n- )+(( i_rev>>r)>>(n- )),

[0054] like >>(n- )=0, then y_w= +(i_rev >> r);

[0055] like >>(n- )≠0, then y_w=(i_rev>>r)% ;

[0056] Wherein, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the stage of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

[0057] The present application also proposes a reading device of a rotation factor, which is used in an inverse number theory transformation circuit, wherein the rotation factor is stored in each static random access memory based on a storage mapping relationship constructed by the encoding device of the rotation factor described in any of the above embodiments, and the reading device includes:

[0058] The second acquisition module is used to determine the parallelism and stage of the inverse number theory transformation of the data to be processed;

[0059] Determine the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located;

[0060] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory;

[0061] The reading module is used to read the rotation factors corresponding to each polynomial pair based on the codes of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage addresses in the corresponding static random access memory.

[0062] In an embodiment of the present application, the second acquisition module is configured to determine the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage address in the static random access memory in the following manner:

[0063] When r=0, x_r=t, y_r= +p;

[0064] When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ;

[0065] When r∈[b,n-1], x_r=( +p) / / ,y_r= +p-x_r* ;

[0066] Among them, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

[0067] The present application also proposes a method for reading a rotation factor, which is used in the device for reading the rotation factor described in the above embodiment. The method comprises:

[0068] Based on the second acquisition module, determining the parallelism and the stage of the inverse number theory transformation of the data to be processed;

[0069] Determine the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located;

[0070] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory;

[0071] Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage address in the corresponding static random access memory, the rotation factors corresponding to each polynomial pair are read.

[0072] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the parallel operation are located, and the storage address in the corresponding static random access memory based on the static random access memory order corresponding to each polynomial pair participating in the operation in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, includes:

[0073] When r=0, x_r=t, y_r= +p;

[0074] When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ;

[0075] When r∈[b,n-1], x_r=( +p) / / ,y_r= +p-x_r* ;

[0076] Among them, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

[0077] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements any of the above-described methods when executed by a processor.

[0078] An embodiment of the present application further provides a chip, which includes the rotation factor encoding device or the rotation factor reading device described in any one of the above embodiments.

[0079] In the embodiment of the present application, the encoding device using the rotation factor excludes at least one redundant rotation factor in each stage when constructing a storage mapping relationship. Therefore, when storing each rotation factor based on the storage mapping relationship, the storage space overhead of the rotation factor can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0081] Figure 1 is a module diagram of a rotation factor encoding device in an embodiment of the present application;

[0082] Figure 2 A schematic diagram of the reverse number theory transformation of the data to be processed in one embodiment of the present application;

[0083] Figure 3 is a module diagram of a device for reading rotation factors in one embodiment of the present application;

[0084] Figure 4 is a step diagram of a method for encoding a rotation factor in an embodiment of the present application;

[0085] Figure 5 is a step diagram of a method for reading a rotation factor in an embodiment of the present application;

[0086] Figure 6 This is a module diagram of a computer-readable storage medium in one embodiment of the present application.

[0087] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0088] The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided only to enable those skilled in the art to better understand and implement the present application, and are not intended to limit the scope of the present application in any way. On the contrary, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0089] Those skilled in the art know that the embodiments of the present application can be implemented as a system, device, method or computer program product. Therefore, the present disclosure can be specifically implemented in the following forms, namely: complete hardware, complete software (including firmware, resident software, microcode, etc.), or a combination of hardware and software.

[0090] According to an embodiment of the present application, a method, device, medium and chip for encoding and reading rotation factors are proposed.

[0091] It should be understood herein that any number of elements in the drawings is for illustration rather than limitation, and any naming is only for distinction rather than having any limiting meaning.

[0092] The principles and spirit of the present application are explained in detail below with reference to several representative implementations of the present application.

[0093] Exemplary Devices

[0094] like Figure 1 As shown, the embodiment of the present application proposes a rotation factor encoding device 100, which is used in an inverse number theory transformation circuit. The encoding device 100 includes:

[0095] A first acquisition module 110 is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation;

[0096] Based on the operation information, determining each rotation factor required for each stage of the inverse number theory transformation of the data to be processed;

[0097] Determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtain the target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage;

[0098] The encoding module 120 is used to construct a storage mapping relationship between the remaining rotation factors and each static random access memory for storing the rotation factors according to a preset condition.

[0099] In an embodiment of the present application, the data to be processed for inverse number theory encoding includes multiple polynomials, and the number of polynomials is the sequence length of the data to be processed. The number of static random access memories (SRAMs) on the FPGA (field programmable logic circuit) used for inverse number theory transformation determines the degree of parallelism. For example, if there are two SRAMs on the FPGA used for inverse number theory transformation, the degree of parallelism is 2, and if there are four SRAMs on the FPGA used for inverse number theory transformation, the degree of parallelism is 4.

[0100] In addition, in the embodiment of the present application, the SRAM on the FPGA used for inverse number theory transformation can adopt a single-port SRAM, thereby having a larger area utilization rate.

[0101] In addition, the inverse number theory transformation usually needs to go through multiple stages, and each stage performs multiple butterfly calculations. After multiple stages, the result of the inverse number theory transformation is finally obtained. Among them, the number of stages required for the inverse number theory transformation is related to the sequence length of the data to be processed. For example, in the embodiment of the present application, it is assumed that the sequence length of the data to be processed by the inverse number theory transformation is N, , the degree of parallelism is K, K , then the data to be processed requires n stages to complete the inverse number theory transformation, the number of stages is r, then r∈[0,n-1].

[0102] In addition, in the inverse number theory transformation, at stage r, the data to be processed has polynomial groups, each with butterfly calculations, each butterfly calculation requires a rotation factor, for j∈[0, ), the rotation factor W required for the jth butterfly calculation can be determined based on the following formula (1):

[0103] (1)

[0104] Among them, during the inverse number theory transformation, the calculation of each stage is carried out in the order of the value of the stage number r from large to small. For example, for the data to be processed with a sequence length of 8 and a parallelism of 4, N=8, K=4, n=3, then, a total of n stages, that is, 3 stages, are carried out during the inverse number theory transformation. At this time, r∈[0,2]. In addition, during the inverse number theory transformation, the data to be processed first performs stage r=2, then stage r=1, and finally stage r=0.

[0105] like Figure 2 As shown, Figure 2 A schematic diagram of the rotation factors required at each stage of the inverse number theory transformation of the data to be processed with a sequence length of 8 and a parallelism of 4 is shown. Among them, x[0]- x[7] are 8 polynomials of the inverse number theory transformation stage 2 of the data to be processed, that is, the original sequence, and x[0]- x[7] are located in four polynomial groups; - are 8 polynomials in stage 1 of the inverse number theory transformation of the data to be processed, in two polynomial groups; - These are 8 polynomials at stage 0 of the inverse number theory transformation of the data to be processed, and are in the same polynomial group.

[0106] In stage 2, r=2, the initial data to be processed is the original sequence, and each polynomial is in four polynomial groups, each of which has = butterfly computations, i.e., j∈[0,1).

[0107] x[0] and x[4] are a polynomial group with only one butterfly calculation, j=0. Based on the above formula 1, it can be determined that the rotation factors involved in the butterfly calculation of x[0] and x[4] in stage 2 are ;

[0108] x[2] and x[6] are a polynomial group with only one butterfly calculation, j=0. Based on the above formula 1, it can be determined that the rotation factors involved in the butterfly calculation of x[2] and x[6] in stage 2 are ;

[0109] x[1] and x[5] are a polynomial group with only one butterfly calculation, j=0. Based on the above formula 1, it can be determined that the rotation factors involved in the butterfly calculation of x[1] and x[5] in stage 2 are ;

[0110] x[3] and x[7] are a polynomial group with only one butterfly calculation, j=0. Based on the above formula 1, it can be determined that the rotation factors involved in the butterfly calculation of x[3] and x[7] in stage 2 are .

[0111] In stage 1, r = 1, each polynomial is divided into two polynomial groups, each with = butterfly calculations, i.e. j∈[0,2).

[0112] , is a polynomial group, is a polynomial pair, corresponding to a butterfly calculation, is a polynomial pair, corresponding to a butterfly calculation. The corresponding butterfly calculation order j=0, The corresponding butterfly calculation order j=1.

[0113] Based on the above formula (1), it can be calculated that:

[0114] The corresponding rotation factor , The corresponding rotation factor is .

[0115] Similarly, the rotation factors of another polynomial group can be calculated as follows:

[0116] is another polynomial group, is a polynomial pair, corresponding to a butterfly calculation, is a polynomial pair, corresponding to a butterfly calculation. The corresponding butterfly calculation order j=0, The corresponding butterfly calculation order j=1. The corresponding rotation factor , The corresponding rotation factor is .

[0117] At stage 0, r = 0, the polynomials are in the same polynomial group, which has = butterfly calculations, i.e. j∈[0,4).

[0118] , For the butterfly calculation with j=0, based on formula (1), the corresponding rotation factor can be calculated as ;

[0119] For the butterfly calculation with j=1, based on formula (1), the corresponding rotation factor can be calculated as ;

[0120] For the butterfly calculation with j=2, based on formula (1), the corresponding rotation factor can be calculated as ;

[0121] For the butterfly calculation with j=3, based on formula (1), the corresponding rotation factor can be calculated as .

[0122] This allows the determination of the various rotation factors required for the data to be processed.

[0123] In the embodiment of the present application, the first acquisition module 110 is configured to determine the redundant rotation factors of the to-be-processed data in each stage of the inverse number theory transformation based on the following method, and obtain the target storage rotation factor of each stage:

[0124] In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage;

[0125] If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

[0126] Reference Figure 2 As shown, based on the above calculation, when r=2, there are 4 polynomial groups in total, and the rotation factors of each polynomial group are the same, that is, they are redundant with each other; when r=1, there are two polynomial groups in total, and the rotation factors of each polynomial group are the same, that is, they are redundant with each other; when r=0, there is only one polynomial group, and the rotation factors are different, and there is no redundancy.

[0127] Therefore, in the reverse number theory transformation, when r=0, each polynomial is in a polynomial group, and the rotation factors required for each butterfly calculation in the polynomial group are different. That is, when r=0, there is no polynomial group whose rotation factors are redundant with each other, so all the rotation factors are the target storage rotation factors of stage 0.

[0128] When r∈[1,n-1], each polynomial is evenly divided into various polynomial groups, the number of butterfly calculations in each polynomial group is the same, and the rotation factors involved in each polynomial group are also the same. Figure 2 As shown, when r=2, the rotation factors in the four polynomial groups are , that is, the rotation factors in the four polynomial groups are redundant with each other, and the rotation factor in any polynomial group is the target storage rotation factor in stage 2; for example, when r=1, the rotation factors in the two polynomial groups are That is, the rotation factors in the two polynomial groups are redundant with each other, and the rotation factors in any polynomial group are the target storage rotation factors of stage 1.

[0129] For another example, taking the data to be processed with a sequence length of 64 and a parallelism of 4 as an example, as shown in Table 1, the 64 polynomials of the original sequence are F1-F64, and the polynomial groups in each stage of the inverse number theory transformation according to the parallelism of 4 are shown in Table 1 below, where the parallelism of 4 means that four SRAMs are set on the FPGA for number theory transformation, and the four SRAMs are numbered 0-3, as shown in Table 1 below:

[0130] Table 1

[0131]

[0132] Among them, in Table 1, 0-5 represent various stages of the inverse number theory transformation, SRAM0-SRAM3 represent four single-port SRAMs for parallel computing, F1-F64 represent 64 polynomials in stage 5 of the inverse number theory transformation, which are in thirty-two polynomial groups; E1-E64 represent 64 polynomials in stage 4 of the inverse number theory transformation, which are in sixteen polynomial groups; D1-D64 represent 64 polynomials in stage 3 of the inverse number theory transformation, which are in eight polynomial groups; C1-C64 represent 64 polynomials in stage 2 of the inverse number theory transformation, which are in four polynomial groups; B1-B64 represent 64 polynomials in stage 1 of the inverse number theory transformation, which are in two polynomial groups; A1-A64 represent 64 polynomials of the original sequence, which are in the same polynomial group.

[0133] Based on the above calculation method of the rotation factor, the rotation factor corresponding to each polynomial pair in each parallel operation at each stage of the inverse number theory transformation can be determined, as shown in Table 2 below:

[0134] Table 2

[0135]

[0136] Among them, referring to Table 1 and Table 2, each stage of each inverse number theory transformation requires eight parallel operations, and each parallel operation requires four rotation factors. In addition, Table 2 only uses the exponents of each rotation factor as an example.

[0137] Continuing to refer to Table 2, at stage r=5, all rotation factors are the same, at stages r=4, r=3, r=2 and r=1, there are also redundant rotation factors, and only at stage r=0, the rotation factors are different. If all the rotation factors corresponding to each polynomial pair in Table 2 are stored, a large amount of storage space is required.

[0138] Referring to Table 1 and Table 2, when at stage r=0, each polynomial is in a polynomial group, so each rotation factor is different. Therefore, all rotation factors at stage r=0 can be retained, that is, all rotation factors are target storage rotation factors at stage 0.

[0139] When the stage r∈[1,n-1], each polynomial is divided into different multiple polynomial groups, and the rotation factors corresponding to each polynomial group are the same. Therefore, in the stage r∈[1,n-1], the rotation factors in each polynomial group are redundant with each other. Therefore, only the rotation factor corresponding to one of the polynomial groups can be retained, that is, the rotation factor in any polynomial group is the target storage rotation factor of the corresponding stage, thereby reducing the storage space overhead of the rotation factor.

[0140] In the embodiment of the present application, after determining the target storage rotation factor of each stage, the encoding module 120 is configured to construct a mapping relationship based on the following method:

[0141] Get candidate twiddle factors from the target stored twiddle factors of each stage;

[0142] Converting the index of the candidate conversion factor into a binary code;

[0143] Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed;

[0144] Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

[0145] Based on the above description, for the data to be processed with a length of 64, N=64, n=6, r∈[0,5]. Therefore, when r∈[1,5], it is only necessary to save the rotation factors corresponding to any polynomial group in each stage, and all the rotation factors of r=0 are saved. And based on the above formula (1), the rotation factors required to be stored in each stage can be calculated, that is, the target storage rotation factors of each stage, as shown in Table 3 below:

[0146] Table 3

[0147]

[0148] After determining the rotation factors that need to be stored in each stage, in the embodiment of the present application, first, candidate rotation factors are obtained from the target storage rotation factors of each stage.

[0149] Taking the above Table 3 as an example, Table 3 determines the various rotation factors that need to be stored in each stage when the data to be processed is subjected to inverse number theory transformation. Therefore, it is only necessary to traverse the above Table 3 to obtain each candidate rotation factor.

[0150] Then, the obtained exponents of the candidate conversion factors are converted into binary codes.

[0151] In the embodiment of the present application, the rotation factor is , where N represents the sequence length of the data to be processed, This is the exponent of the rotation factor, which is a decimal number. For example, the rotation factor The exponent is 3, the rotation factor The exponent of is 2.

[0152] After converting the exponent of the candidate rotation factor into a binary code, various stages in which the candidate rotation factor participates in the inverse number theory transformation of the data to be processed are determined based on the binary code.

[0153] In an embodiment of the present application, the number of bits of the first code 1 from the low bit to the high bit of the binary code can be first determined, where the number of bits starts from zero; and the number of bits is used as the highest stage of the operation of the candidate rotation factor, and the rotation factors participate in the operation from the highest stage to the lowest stage.

[0154] For example, to select the rotation factor For example, the binary code corresponding to the exponent 30 is 11110. It should be noted that the number of bits is determined starting from 0, that is, the "0" in 11110 is the 0th bit from right to left, the first "1" from right to left in 11110 is the 1st bit, and so on. Then, the first code from low to high in 11110 is 1, and the number of bits from low to high is 1, which represents the rotation factor The highest stage involved in the operation is r=1, and all stages from r=1 to the lowest stage r=0 participate in the operation, as shown in Table 3 above. When r=1 and 0, both need to be stored, that is, verified to be correct.

[0155] After determining the various stages in which the candidate rotation factors participate in the inverse number theory transformation, the storage mapping relationship corresponding to the candidate rotation factors in the various stages can be constructed based on the stages in which the candidate rotation factors participate in the calculation.

[0156] For example, in an embodiment of the present application, the encoding module 120 is configured to construct a storage mapping relationship corresponding to the candidate rotation factor at each stage based on the stages in which the candidate rotation factor participates in the operation according to the following method:

[0157] When r∈[0,b-1], x_w=(i_rev>>r)>>(nbr-1), y_w= +(i_rev>>r)% ;

[0158] When r∈[b,n-1], x_w=( )>>(n- )+(( i_rev>>r)>>(n- )),

[0159] like >>(n- )=0, then y_w= +(i_rev >> r);

[0160] like >>(n- )≠0, then y_w=(i_rev>>r)% ;

[0161] Wherein, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the number of stages of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

[0162] Among them, “>>” is the right shift in the bit operation. For example, the binary code 1100>>2 means shifting 1100 to the right by two bits to get 11.

[0163] In the embodiment of the present application, For example, i=30, its corresponding binary code is 11110, and it can be seen that the stages involved in the operation are r=1 and r=0.

[0164] And N=64, K=4, so we can know n=6, b=2, r∈[0,5];

[0165] Therefore, when r=1, that is, r∈[0,b-1], we can get:

[0166] x_w=(i_rev>>r)>>(nbr-1)=((11110)>>1)>>(6-2-1-1)

[0167] =(1111)>>2

[0168] =(11)

[0169] =3;

[0170] y_w= +(i_rev>>r)%

[0171] = +((11110)>>1)%

[0172] =4+(1111)%4

[0173] =4+15%4

[0174] =4+3

[0175] =7.

[0176] That is, when r=1, x_w=3, y_w=7;

[0177] When r=0, that is, r∈[0,b-1], we can get:

[0178] x_w=(i_rev>>r)>>(nbr-1)=((11110)>>0)>>(6-2-0-1)

[0179] =(11110)>>3

[0180] =(11)

[0181] =3;

[0182] y_w= +(i_rev>>r)%

[0183] = +((11110)>>0)%

[0184] =8+(11110)%8

[0185] =8+30%8

[0186] =8+6

[0187] =14

[0188] That is, when r=1, x_w=3, y_w=14.

[0189] Therefore, it can be seen that for the rotation factor For example, the storage mapping relationship between the storage of each static random access memory is x_w=3, y_w=7 and x_w=3, y_w=14. The storage mapping relationship represents that based on the storage mapping relationship, When it is needed, it needs to be stored in the storage space at address 7 and address 14 in the static random access memory numbered 3.

[0190] As shown in Table 4 below, Table 4 is a schematic diagram of various static random access memories and their internal storage addresses:

[0191] Table 4

[0192]

[0193] Among them, SRAM0-SRAM3 in Table 4 represent four parallel static random access memories, and 0-15 in each static random access memory represents the storage address of the storage space in each static random access memory.

[0194] Therefore, based on the above storage mapping relationship, according to the address table of each SRAM shown in Table 4 above, Stored in the storage space of the corresponding address in the corresponding SRAM.

[0195] For example, the rotation factor is calculated In phase 1, the SRAM code is 3 and the storage address is 7. Stored in the storage space of address 7 in SRAM3; the SRAM code at stage 0 is 3, and the storage address is 15, that is, Stored in the storage space at address 15 of SRAM3.

[0196] In addition, when r∈[b, n-1], x_w and y_w are calculated using a different method from that when r∈[0, b-1].

[0197] For example, for the rotation factor , its index i is 8, the corresponding binary code i_rev is 1000, the number of bits of the code 1 from low to high is 3, and represents The stages involved in the operation include 3, 2, 1, and 0.

[0198] When r=3, that is, r∈[b,n-1],

[0199] x_w= ( )>>(n- ) + ((i_rev>>r)>>(n- ))

[0200] = (4) >> 2 + (((1000)) >> 3) >> 2

[0201] = (100) >> 2 + (1) >> 2

[0202] = (1) + 0

[0203] =1

[0204] When calculating y_w, first determine >>(n- ) and 0 are as follows:

[0205] >>(n- )

[0206] =(4)>>2

[0207] =(10)

[0208] =2≠0

[0209] Therefore, y_w=(i_rev>>r)%

[0210] =((1000)>>3)%4

[0211] =1%4

[0212] =1

[0213] That is, when r=3, x_w=1, y_w=1;

[0214] Similarly, we can calculate that when r=2, x_w=2, y_w=2;

[0215] When r=1, that is, r∈[0,b-1], we can calculate x_w=1,y_w=4;

[0216] When r=0, that is, r∈[0,b-1], we can calculate x_w=1,y_w=8.

[0217] Right now, The corresponding storage mapping relationship is x_w=1, y_w=1; x_w=2, y_w=2; x_w=1, y_w=4; x_w=1, y_w=8. It represents that based on this mapping relationship When stored in each static random access memory, it needs to be stored in the storage space of addresses 1, 4, and 8 of the static random access memory numbered 1, and in the storage space of address 2 of the static random access memory numbered 2.

[0218] According to the above method, the rotation factor can be determined - The corresponding SRAM encoding and storage address storage mapping relationship, according to the mapping relationship between each rotation factor and the SRAM encoding and storage address, each rotation factor is stored in the storage space of the storage address corresponding to the SRAM, and the following Table 5 is obtained:

[0219] Table 5

[0220]

[0221] As shown in Table 5 above, Table 5 shows a schematic diagram of storing various rotation factors using a storage mapping relationship constructed by the rotation factor encoding method in the embodiment of the present application. In the same stage of the inverse number theory transformation, only the rotation factors corresponding to one polynomial group are stored. At stage r, the data to be processed has polynomial groups, each with The butterfly calculation corresponds to butterfly calculations, so the sum is . That is, a total of ( -1) rotation factor, in order to facilitate encoding, it can be added at the first address of the static random access memory encoded as 0 , each storage address of each static random access memory can be filled up, and after filling up, the following Table 6 is obtained:

[0222] Table 6

[0223]

[0224] Add at the first address of SRAM0 After that, the total storage In the prior art, when all the rotation factors are stored, when the degree of parallelism is K, a total of K*N / 2 rotation factors are required, that is, the storage space of the rotation factors required by this solution is reduced to 2 / K of the original. Therefore, when the rotation factor encoding method in the embodiment of the present application is used to store the rotation factors, it is not necessary to store the redundant rotation factors at each stage, thereby reducing the storage space overhead of the rotation factors.

[0225] In addition, the above is only an example of a number theory transformation with a length of 64 and a parallelism of 4. In actual operations, the length of the data to be processed is longer and the corresponding parallelism is higher. As the parallelism increases, the effect of the encoding method of the present application in reducing the storage space overhead of the rotation factors is more significant.

[0226] like Figure 3 As shown, the present application further proposes a twiddle factor reading device 200, which is used in an inverse number theory transformation circuit. The twiddle factor is stored in each static random access memory based on the storage mapping relationship constructed by the twiddle factor encoding device 100 described in any of the above embodiments. In the embodiment of the present application, the twiddle factor reading device 200 includes:

[0227] The second acquisition module 210 is used to determine the parallelism and the stage of the inverse number theory transformation of the data to be processed;

[0228] Determine the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located;

[0229] Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory;

[0230] The reading module 220 is used to read the rotation factors corresponding to each polynomial pair based on the codes of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage addresses in the corresponding static random access memory.

[0231] In the embodiment of the present application, the degree of parallelism during the inverse number theory transformation of the data to be processed is determined based on the number of static random access memories used to store the rotation factors, and the number of stages of the inverse number theory transformation is determined based on the sequence length of the data to be processed. Taking the data to be processed shown in Table 1 above as an example, the length is 64, including stages 0-5, four static random access memories SRAM0-SRAM3, and the degree of parallelism is 4.

[0232] The stages of the inverse number theory transformation are determined. For example, the data to be processed described in Table 1 above first undergoes stage 5, and then sequentially undergoes stages 4, 3, 2, 1, and 0. Continuing to refer to Table 1, it can be seen that in stage 5, the data to be processed is divided into 32 polynomial groups, and the 32 polynomial groups are evenly distributed to four static random access memories, among which the eight polynomial groups F1-F16 correspond to SRAM0, the eight polynomial groups F17-F32 correspond to SRAM1, the eight polynomial groups F33-F48 correspond to SRAM2, and the eight polynomial groups F49-F64 correspond to SRAM3. In the same parallel operation, it is necessary to select a polynomial pair from the polynomial groups corresponding to the four static random access memories.

[0233] For example, in the first parallel operation of stage 5, the polynomial pair F1&F2 is selected from SRAM0, the polynomial pair F17&F18 is selected from SRAM1, the polynomial pair F33&F34 is selected from SRAM2, and the polynomial pair F49&F50 is selected from SRAM3.

[0234] During the second parallel operation of stage 5, polynomial pair F3&F4 is selected from SRAM0, polynomial pair F19&F20 is selected from SRAM1, polynomial pair F35&F36 is selected from SRAM2, and polynomial pair F51&F52 is selected from SRAM3.

[0235] By analogy, in the eighth parallel operation of stage 5, the polynomial pair F15&F16 is selected from SRAM0, the polynomial pair F31&F32 is selected from SRAM1, the polynomial pair F47&F48 is selected from SRAM2, and the polynomial pair F63&F64 is selected from SRAM3.

[0236] In addition, each polynomial group is evenly distributed to each SRAM, and the SRAM code corresponding to any polynomial is the SRAM order corresponding to it. For example, in the first parallel operation of stage 5, F1&F2 corresponds to SRAM0, and its corresponding SRAM order is 0, F17&F18 corresponds to SRAM1, and its corresponding SRAM order is 1, F33&F34 corresponds to SRAM2, and its corresponding SRAM order is 2, F49&F50 corresponds to SRAM3, and its corresponding SRAM order is 3.

[0237] In the embodiment of the present application, the second acquisition module 210 is configured to determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial in the parallel operation is located, and the storage address in the corresponding static random access memory in the following manner:

[0238] When r=0, x_r=t, y_r= +p;

[0239] When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ;

[0240] When r∈[b,n-1], (x_r= +p) / / ,y_r= +p-x_r* ;

[0241] Among them, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

[0242] In the embodiment of the present application, the methods for reading the rotation factor are different at different stages, and can be divided into r=0, r∈[1, b-1] and r∈[b, n-1] according to the stage. The following describes the methods for reading the rotation factor according to scenario 1: r=0; scenario 2: r∈[1, b-1]; scenario 3: r∈[b, n-1].

[0243] For scenario 1: r=0

[0244] Still taking the data to be processed shown in Table 1 as an example, N=64, n=6, K=4, b=2, r=0.

[0245] When r = 0, all 64 polynomials of B1-B64 are in the same polynomial group, and the 64 polynomials are evenly distributed to 4 static random access memories, with a parallelism of 4. Therefore, in the same parallel operation, a polynomial pair needs to be selected from each of the 4 static random access memories.

[0246] Therefore, the polynomial pairs participating in the first parallel operation include: A1&A17, A9&A25, A33&A49, A41&A57;

[0247] The polynomial pairs participating in the second parallel operation include: A2&A18, A10&A26, A34&A50, A42&A58;

[0248] By analogy, the polynomial pairs participating in the eighth parallel operation include: A8&A24, A16&A32, A40&B56, A48&B64.

[0249] Taking the first parallel operation when r=0 as an example, that is, p=0, the polynomial pairs participating in the first parallel operation include: A1&A17, A9&A25, A33&A49, A41&A57, among which the static random access memory order corresponding to A1&A17 is t=0, the static random access memory order corresponding to A9&A25 is t=1, the static random access memory order corresponding to A33&A49 is t=2, and the static random access memory order corresponding to A41&A57 is t=3.

[0250] The read address of the rotation factor corresponding to the polynomial pair A1&A17 is calculated as follows:

[0251] x_r=t=0

[0252] y_r= +p

[0253] = +0

[0254] =8

[0255] That is, in stage 0, the code of the static random access memory in which the polynomial A1&A17 corresponding rotation factors are stored is 0, and the storage address in the static random access memory code is 8. Based on Table 6, it can be seen that the rotation factors are , which is verified to be correct based on the above Table 3.

[0256] The read address of the rotation factor corresponding to the polynomial pair A9&A25 is calculated as follows:

[0257] x_r=t=1

[0258] y_r= +p

[0259] = +0

[0260] =8

[0261] That is, in stage 0, the code of the SRAM in which the polynomial corresponding to the rotation factor A9 & A25 is stored is 1, and the storage address in the SRAM code is 8. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 3.

[0262] The read address of the rotation factor corresponding to the polynomial pair A33 & A49 is calculated as follows:

[0263] x_r=t=2

[0264] y_r= +p

[0265] = +0

[0266] =8

[0267] That is, in stage 0, the code of the SRAM in which the polynomial corresponding to the rotation factor A33 & A49 is stored is 2, and the storage address in the SRAM code is 8. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 3.

[0268] The read address of the rotation factor corresponding to the polynomial pair A41&A57 is calculated as follows:

[0269] x_r=t=3

[0270] y_r= +p

[0271] = +0

[0272] =8

[0273] That is, in stage 0, the code of the SRAM in which the polynomial corresponding to the rotation factor A41 & A57 is stored is 3, and the storage address in the SRAM code is 8. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 3.

[0274] Based on this method, the code of the static random access memory and the storage address of the rotation factor corresponding to each polynomial pair in each parallel operation can be calculated at stage r=0. After determining the code of the static random access memory corresponding to the rotation factor and the storage address of the static random access memory, the rotation factor stored at the address can be read based on the reading module 220.

[0275] For scenario 2: r∈[1,b-1]

[0276] Still taking the data to be processed shown in Table 1 as an example, N=64, n=6, K=4, b=2, r∈[1, b-1], that is, r=1.

[0277] When r=1, all 64 polynomials B1-B64 are divided into 2 polynomial groups, B1-B32 is one polynomial group, B33-B64 is another polynomial group, and the 64 polynomials are evenly distributed to 4 static random access memories, with a parallelism of 4. Therefore, in the same parallel operation, a polynomial pair needs to be selected from each of the 4 static random access memories, and the two polynomials in each polynomial pair belong to the same polynomial group.

[0278] Therefore, the polynomial pairs participating in the first parallel operation include: B1&B17, B9&B25, ​​B33&B49, B41&B57;

[0279] The polynomial pairs participating in the second parallel operation include: B2&B18, B10&B26, B34&B50, B42&B58;

[0280] By analogy, the polynomial pairs participating in the eighth parallel operation include: B8&B24, B16&B32, B40&B56, B48&B64.

[0281] Taking the first parallel operation when r=1 as an example, that is, p=0, the polynomial pairs participating in the first parallel operation include: B1&B17, B9&B25, ​​B33&B49, B41&B57, among which the static random access memory order corresponding to B1&B17 is t=0, the static random access memory order corresponding to B9&B25 is t=1, the static random access memory order corresponding to B33&B49 is t=2, and the static random access memory order corresponding to B41&B57 is t=3.

[0282] The read address of the rotation factor corresponding to the polynomial pair B1&B17 is calculated as follows:

[0283] x_r=(t% )* +(p / / )

[0284] =(0% )*2+(0 / / )

[0285] =0+0

[0286] =0

[0287] y_r= +p-(p / / )*

[0288] = +0-(0 / / )*

[0289] =4+0-0

[0290] =4

[0291] That is, in stage 1, the code of the static random access memory in which the twiddle factors corresponding to the polynomial pair B1 & B17 are stored is 0, and the storage address in the static random access memory code is 4. Based on Table 6, it can be seen that the twiddle factors are , which is verified to be correct based on the above Table 2.

[0292] The read address of the rotation factor corresponding to the polynomial pair B9&B25 is calculated as follows:

[0293] x_r=(t% )* +(p / / )

[0294] =(1% )*2+(0 / / )

[0295] =2+0

[0296] =2

[0297] y_r= +p-(p / / )*

[0298] = +0-(0 / / )*

[0299] =4+0-0

[0300] =4

[0301] That is, in stage 1, the code of the static random access memory in which the twiddle factors corresponding to the polynomial B9 & B25 are stored is 2, and the storage address in the static random access memory code is 4. Based on Table 6, it can be seen that the twiddle factors are , which is verified to be correct based on the above Table 2.

[0302] The read address of the rotation factor corresponding to the polynomial pair B33&B49 is calculated as follows:

[0303] x_r=(t% )* +(p / / )

[0304] =(2% )*2+(0 / / )

[0305] =0+0

[0306] =0

[0307] y_r= +p-(p / / )*

[0308] = +0-(0 / / )*

[0309] =4+0-0

[0310] =4

[0311] That is, in stage 1, the code of the static random access memory in which the twiddle factors corresponding to the polynomial B33 & B49 are stored is 2, and the storage address in the static random access memory code is 4. Based on Table 6, it can be seen that the twiddle factors are , which is verified to be correct based on the above Table 2.

[0312] The read address of the rotation factor corresponding to the polynomial pair B41&B57 is calculated as follows:

[0313] x_r=(t% )* +(p / / )

[0314] =(3% )*2+(0 / / )

[0315] =2+0

[0316] =2

[0317] y_r= +p-(p / / )*

[0318] = +0-(0 / / )*

[0319] =4+0-0

[0320] =4

[0321] That is, in stage 1, the code of the SRAM in which the polynomial corresponding to the rotation factor B41 & B57 is stored is 2, and the storage address in the SRAM code is 4. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 2.

[0322] Based on this method, the code of the static random access memory and the storage address of the rotation factor corresponding to each polynomial pair in each parallel operation at stage r∈[1, b-1] can be calculated. After determining the code of the static random access memory corresponding to the rotation factor and the storage address of the static random access memory, the rotation factor stored at the address can be read based on the reading module 220.

[0323] For scenario three: r∈[b,n-1]

[0324] Still taking the data to be processed shown in Table 1 as an example, N=64, n=6, K=4, b=2, so r∈[2,5].

[0325] Taking r=5 as an example, when r=5, F1-F64 is located in 32 polynomial groups, evenly distributed to 4 static random access memories, and the degree of parallelism is 4. Therefore, in the same parallel operation, a polynomial pair needs to be selected from each of the 4 static random access memories. Based on step S600, it can be seen that a total of 8 parallel operations are required in stage 5, that is, p∈[0,7].

[0326] r=5, p=0 in the first parallel operation, the polynomial pairs participating in the first parallel operation include: F1&F2, F17&F18, F33&F34 and F49&F50. Among them, the static random access memory order corresponding to F1&F2 is t=0, the static random access memory order corresponding to F17&F18 is t=1, the static random access memory order corresponding to F33&F34 is t=2, and the static random access memory order corresponding to F49&F50 is t=3.

[0327] Then, the read address of the rotation factor corresponding to the polynomial pair F1&F2 is calculated as follows:

[0328] x_r=( +p) / /

[0329] =( +0) / /

[0330] = 0

[0331] y_r= +p-x_r*

[0332] = +0-0*

[0333] =0

[0334] That is, in stage 5, the code of the static random access memory in which the twiddle factors corresponding to the polynomial pair F1 & F2 are stored is 0, and the storage address in the static random access memory code is 0. Based on Table 6, it can be seen that the twiddle factors are , which is verified to be correct based on the above Table 3.

[0335] The read address of the rotation factor corresponding to the polynomial pair F17 & F18 is calculated as follows:

[0336] x_r=( +p) / /

[0337] =( +0) / /

[0338] = 0

[0339] y_r= +p-x_r*

[0340] = +0-0*

[0341] =0

[0342] That is, in stage 5, the code of the static random access memory in which the twiddle factors corresponding to the polynomial F17 & F18 are stored is 0, and the storage address in the static random access memory code is 0. Based on Table 6, it can be seen that the twiddle factors are , which is verified to be correct based on the above Table 3.

[0343] The read address of the rotation factor corresponding to the polynomial pair F33 & F34 is calculated as follows:

[0344] x_r=( +p) / /

[0345] =( +0) / /

[0346] = 0

[0347] y_r= +p-x_r*

[0348] = +0-0*

[0349] =0

[0350] That is, in stage 5, the code of the static random access memory in which the polynomial corresponding to the rotation factor F33 & F34 is stored is 0, and the storage address in the static random access memory code is 0. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 3.

[0351] The read address of the rotation factor corresponding to the polynomial pair F49 & F50 is calculated as follows:

[0352] x_r=( +p) / /

[0353] =( +0) / /

[0354] = 0

[0355] y_r= +p-x_r*

[0356] = +0-0*

[0357] =0

[0358] That is, in stage 5, the code of the static random access memory in which the polynomial corresponding to the rotation factor F49 & F50 is stored is 0, and the storage address in the static random access memory code is 0. Based on Table 6, it can be seen that the rotation factor is , which is verified to be correct based on the above Table 3.

[0359] Based on this method, the code of the static random access memory stored in the corresponding rotation factor of each polynomial pair in each parallel operation at stage r∈[b, n-1] and the storage address of the static random access memory can be calculated. After determining the code of the static random access memory corresponding to the rotation factor and the storage address of the static random access memory, the rotation factor stored at the changed address can be read based on the reading module 220.

[0360] In the embodiment of the present application, after the data to be processed is stored according to the storage mapping relationship constructed by the above-mentioned rotation factor encoding device 100, the rotation factor reading device 200 in the embodiment of the present application can be used to determine the storage address of the required rotation factor based on the corresponding static random access memory order and the order of parallel operations of the polynomials involved in the operation in each stage of the inverse number theory transformation of the data to be processed, and then the corresponding rotation factor can be obtained from the storage address.

[0361] Exemplary Methods

[0362] like Figure 4 As shown, this exemplary embodiment proposes a method for encoding a rotation factor, which is used in the rotation factor encoding device 100 described in any of the above embodiments. The encoding method includes the following steps S100-S400:

[0363] Step S100: Based on the first acquisition module, the operation information of the data to be processed is acquired, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation;

[0364] Step S200: Based on the operation information, determine the various rotation factors required for the data to be processed in various stages of the inverse number theory transformation;

[0365] Step S300: determining redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtaining a target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage;

[0366] Step S400: Based on the encoding module, a storage mapping relationship between a target storage twiddle factor in each stage and each static random access memory for storing the twiddle factor is constructed according to preset conditions.

[0367] The specific implementation methods of steps S100-S400 may refer to the specific implementation methods of the encoding devices of the rotation factors in the above embodiments, which will not be described in detail here.

[0368] In an embodiment of the present application, determining the various rotation factors required for the data to be processed in various stages of the inverse number theory transformation based on the operation information includes:

[0369] The rotation factors in any polynomial group at any stage are determined as follows:

[0370] ;

[0371] Wherein, N represents the sequence length of the data to be processed, r represents the stage of the inverse number theory transformation of the data to be processed, j represents the j-th butterfly calculation in any polynomial group in the stage r of the inverse number theory transformation of the data to be processed, Represents the rotation factors required for the j-th butterfly calculation in any polynomial group in stage r of the inverse number theory transformation of the data to be processed.

[0372] In an embodiment of the present application, determining the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation and obtaining the target storage rotation factors of each stage includes:

[0373] In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage;

[0374] If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

[0375] In the embodiment of the present application, the step of constructing a storage mapping relationship between a target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to a preset condition includes:

[0376] Get candidate twiddle factors from the target stored twiddle factors in each stage;

[0377] Converting the index of the candidate conversion factor into a binary code;

[0378] Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed;

[0379] Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

[0380] In the embodiment of the present application, the determining, based on the binary code, of the candidate rotation factors participating in the various stages of the operation in the inverse number theory transformation of the data to be processed includes:

[0381] Determine the number of bits of the first code 1 from the low bit to the high bit of the binary code, where the number of bits starts from zero;

[0382] The number of bits is used as the candidate rotation factor to participate in the highest stage of the operation, and the rotation factors are all involved in the operation from the highest stage to the lowest stage.

[0383] In the embodiment of the present application, the storage mapping relationship corresponding to the candidate rotation factor at each stage is constructed based on the stages in which the candidate rotation factor participates in the operation, including:

[0384] When r∈[0,b-1], x_w=(i_rev>>r)>>(nbr-1), y_w= +(i_rev>>r)% ;

[0385] When r∈[b,n-1], x_w=( )>>(n- )+(( i_rev>>r)>>(n- )),

[0386] like >>(n- )=0, then y_w= +(i_rev >> r);

[0387] like >>(n- )≠0, then y_w=(i_rev>>r)% ;

[0388] Wherein, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the stage of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

[0389] In the embodiment of the present application, when constructing a storage mapping relationship using the encoding method of the rotation factor, at least one redundant rotation factor in each stage is excluded. Therefore, when storing each rotation factor based on the storage mapping relationship, the storage space overhead of the rotation factor can be reduced.

[0390] like Figure 5As shown, the embodiment of the present application further proposes a method for reading a rotation factor, which is applied to the rotation factor reading device 200 described in any of the above embodiments. The reading method includes the following steps S500-S800:

[0391] Step S500: determining the parallelism and stage of the inverse number theory transformation of the data to be processed;

[0392] Step S600: determining the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation phase in which it is located;

[0393] Step S700: Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory;

[0394] Step S800: Read the twiddle factors corresponding to each polynomial pair based on the codes of the static random access memories where the twiddle factors corresponding to each polynomial pair in the same parallel operation are located and the storage addresses in the corresponding static random access memories.

[0395] The specific implementation methods of steps S500 to S800 may refer to the specific implementation methods of the reading devices of the rotation factors in the above embodiments, which will not be described in detail here.

[0396] In an embodiment of the present application, the method of determining the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the parallel operation are located, and the storage address in the corresponding static random access memory based on the static random access memory order corresponding to each polynomial pair participating in the operation in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, includes:

[0397] When r=0, x_r=t, y_r= +p;

[0398] When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ;

[0399] When r∈[b,n-1], x_r=( +p) / / ,y_r= +p-x_r* ;

[0400] Among them, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

[0401] In the embodiment of the present application, after the data to be processed is stored based on the storage mapping relationship constructed by the encoding device of the above-mentioned rotation factor, the method for reading the rotation factor in the embodiment of the present application can be used to determine the storage address of the required rotation factor based on the static random access memory order corresponding to the polynomial pair involved in the operation and the butterfly calculation order of the polynomial group in which it belongs in each stage of the inverse number theory transformation of the data to be processed, and then the corresponding rotation factor can be obtained from the storage address.

[0402] Exemplary Media

[0403] After introducing the method, medium and system of the exemplary embodiments of the present application, next, reference is made to Figure 6 For a description of the computer-readable storage medium of the exemplary embodiment of the present application, please refer to Figure 6, the computer-readable storage medium shown is a CD-ROM 70, on which a computer program (i.e., a program product) is stored. When the computer program is executed by the processor, the steps described in the above method implementation are implemented, for example, based on the first acquisition module, the operation information of the data to be processed is obtained, the operation information includes the sequence length of the data to be processed and the parallelism during the inverse number theory transformation; based on the operation information, the various rotation factors required for the data to be processed in each stage of the inverse number theory transformation are determined; the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation are determined, and the target storage rotation factor of each stage is obtained, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage; based on the encoding module, the storage mapping relationship between the target storage rotation factor in each stage and each static random access memory for storing the rotation factor is constructed according to preset conditions. Alternatively, determine the parallelism and stage of the inverse number theory transformation of the data to be processed; determine the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located; based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located, determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory; based on the encoding of the static random access memory where the rotation factor corresponding to each polynomial pair in the same parallel operation is located, and the storage address in the corresponding static random access memory, read the rotation factor corresponding to each polynomial pair. The specific implementation method of each step will not be repeated here. It should be noted that examples of the computer-readable storage medium may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0404] Exemplary Chips

[0405] After introducing the method, system and medium of the exemplary embodiment of the present application, the chip of the exemplary embodiment of the present application is introduced next.

[0406] In an embodiment of the present application, a chip is proposed, including the rotation factor encoding device or the rotation factor reading device described in any of the above embodiments, and therefore has all the beneficial effects of the rotation factor encoding device or the rotation factor reading device described in the above embodiments, which are not described one by one here.

[0407] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present application, which are used to illustrate the technical solutions of the present application, rather than to limit them. The protection scope of the present application is not limited thereto. Although the present application is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present application, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

[0408] In addition, although the operations of the method of the present application are described in a specific order in the drawings, this does not require or imply that the operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

Claims

1. A twiddle factor encoding device for an inverse number theory transform circuit, the encoding device include: A first acquisition module is used to acquire operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation; Based on the operation information, determining each rotation factor required for each stage of the inverse number theory transformation of the data to be processed; Determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtain the target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage; The encoding module is used to construct a storage mapping relationship between a target storage rotation factor in each stage and each static random access memory for storing the rotation factor according to preset conditions.

2. The device for encoding a rotation factor according to claim 1, wherein the first acquisition module is configured to determine each rotation factor in any polynomial group in any stage according to the following formula: ； in, N represents the sequence length of the data to be processed, r represents the stage of the inverse number theory transformation of the data to be processed, j represents the j-th butterfly calculation in any polynomial group in the stage r of the inverse number theory transformation of the data to be processed, Represents the rotation factors required for the j-th butterfly calculation in any polynomial group in stage r of the inverse number theory transformation of the data to be processed.

3. The device for encoding a rotation factor according to claim 1, wherein the first acquisition module is configured to determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation based on the following method, and obtain the target storage rotation factor of each stage: In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage; If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

4. The device for encoding a rotation factor according to claim 1, wherein the encoding module is configured to construct a storage mapping relationship based on the following method: Get candidate twiddle factors from the target stored twiddle factors of each stage; Converting the exponent of the candidate rotation factor into a binary code; Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed; Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

5. The device for encoding a rotation factor according to claim 4, wherein the encoding module is configured to determine the stages in which the candidate rotation factor participates in the inverse number theory transformation of the data to be processed based on the following method: Determine the number of bits of the first code 1 from the low bit to the high bit of the binary code, where the number of bits starts from zero; The number of bits is used as the candidate rotation factor to participate in the highest stage of the operation, and the rotation factors are all involved in the operation from the highest stage to the lowest stage.

6. The apparatus for encoding a rotation factor according to claim 4, wherein the encoding module is configured to: When r ∈ [0, b - 1], x_w = (i_rev >> r) >> (n - b - r - 1), y_w = + (i_rev >> r) % ; When r∈[b,n-1], x_w=( )>>(n- )+(( i_rev>>r)>>(n- )), like >>(n- )=0, then y_w= +(i_rev >> r); like >>(n- )≠0, then y_w=(i_rev>>r)% ; in, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the stage of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

7. A method for encoding a rotation factor, used in the device for encoding a rotation factor according to any one of claims 1 to 6, wherein the encoding method include: Based on the first acquisition module, obtain operation information of the data to be processed, wherein the operation information includes the sequence length of the data to be processed and the degree of parallelism during the inverse number theory transformation; Based on the operation information, determining each rotation factor required for each stage of the inverse number theory transformation of the data to be processed; Determine the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation, and obtain the target storage rotation factor of each stage, wherein the target storage rotation factor of each stage excludes at least one redundant rotation factor of the stage; Based on the encoding module, a storage mapping relationship between a target storage twiddle factor in each stage and each static random access memory for storing the twiddle factor is constructed according to preset conditions.

8. The method for encoding rotation factors according to claim 7, wherein the rotation factors required for the data to be processed in each stage of the inverse number theory transformation are determined based on the operation information. include: The rotation factors in any polynomial group at any stage are determined as follows: ； Wherein, N represents the sequence length of the data to be processed, r represents the stage of the inverse number theory transformation of the data to be processed, j represents the j-th butterfly calculation in any polynomial group in the stage r of the inverse number theory transformation of the data to be processed, Represents the rotation factors required for the j-th butterfly calculation in any polynomial group in stage r of the inverse number theory transformation of the data to be processed.

9. The method for encoding rotation factors according to claim 7, wherein the redundant rotation factors of the data to be processed in each stage of the inverse number theory transformation are determined, and the target storage rotation factors of each stage are obtained. include: In any stage of the inverse number theory transformation, if there is only one polynomial group in the stage, all the rotation factors are retained as the target storage rotation factors of the stage; If there are multiple polynomial groups in this stage, only the rotation factor corresponding to one polynomial group is retained as the target storage rotation factor of this stage.

10. The method for encoding a rotation factor according to claim 7, wherein the storage mapping relationship between the target storage rotation factor in each stage and each static random access memory for storing the rotation factor is constructed according to a preset condition, include: Get candidate twiddle factors from the target stored twiddle factors in each stage; Converting the exponent of the candidate rotation factor into a binary code; Determine, based on the binary code, the various stages in which the candidate rotation factors participate in the inverse number theory transformation of the data to be processed; Based on the stages in which the candidate rotation factors participate in the calculation, a storage mapping relationship corresponding to the candidate rotation factors in the stages is constructed.

11. The method for encoding a rotation factor according to claim 10, wherein the stages in which the candidate rotation factor participates in the inverse number theory transformation of the data to be processed are determined based on the binary code. include: Determine the number of bits of the first code 1 from the low bit to the high bit of the binary code, where the number of bits starts from zero; The number of bits is used as the candidate rotation factor to participate in the highest stage of the operation, and the rotation factors are all involved in the operation from the highest stage to the lowest stage.

12. The method for encoding a rotation factor according to claim 10, wherein the storage mapping relationship corresponding to the candidate rotation factor at each stage is constructed based on the stages in which the candidate rotation factor participates in the operation, include: When r ∈ [0, b - 1], x_w = (i_rev >> r) >> (n - b - r - 1), y_w = + (i_rev >> r) % ; When r∈[b,n-1], x_w=( )>>(n- )+((i_rev>>r)>>(n- )), like >>(n- )=0, then y_w= +(i_rev >> r); like >>(n- )≠0, then y_w=(i_rev>>r)% ; Wherein, N represents the sequence length of the data to be processed, N= , K represents the parallelism of the inverse number theory transformation of the data to be processed, K= , r represents the stage of the inverse number theory transformation of the data to be processed, r∈[0,n-1], i is the index of the candidate rotation factor, i_rev is the binary code of i, >> represents a right shift in a bit operation, % represents modulo, x_w represents the number of the static random access memory corresponding to the candidate rotation factor, and y_w represents the storage address of the candidate rotation factor in the static random access memory.

13. A device for reading a rotation factor, used in an inverse number theory transformation circuit, in, The twiddle factors are stored in respective static random access memories using a storage mapping relationship constructed by the twiddle factor encoding device according to any one of claims 1 to 6, and the reading device comprises: The second acquisition module is used to determine the parallelism and stage of the inverse number theory transformation of the data to be processed; Determine the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located; Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory; The reading module is used to read the rotation factors corresponding to each polynomial pair based on the codes of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located and the storage addresses in the corresponding static random access memory.

14. The apparatus for reading a rotation factor according to claim 13, wherein the second acquisition module is configured to determine the encoding of the static random access memory where the rotation factor corresponding to each polynomial in the same parallel operation is located, and the storage address in the static random access memory by the following method: When r=0, x_r=t, y_r= +p; When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ; When r∈[b,n-1], x_r=( +p) / / ,y_r= +p-x_r* ; in, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

15. A method for reading a rotation factor, used in the device for reading a rotation factor according to claim 13 or 14, wherein the method include: Based on the second acquisition module, determining the parallelism and the stage of the inverse number theory transformation of the data to be processed; Determine the static random access memory order corresponding to each polynomial pair involved in the same parallel operation, and the operation order of the parallel operation in the operation stage in which it is located; Based on the static random access memory order corresponding to each polynomial pair participating in the same parallel operation and the operation order of the parallel operation in the operation stage in which it is located, determine the code of the static random access memory where the rotation factor corresponding to each polynomial pair in the parallel operation is located, and the storage address in the corresponding static random access memory; Based on the reading module, the encoding of the static random access memory where the rotation factors corresponding to each polynomial pair in the same parallel operation are located, and the storage address in the corresponding static random access memory, the rotation factors corresponding to each polynomial pair are read.

16. The method for reading a rotation factor according to claim 15, wherein the encoding of the rotation factor corresponding to each polynomial pair in the parallel operation and the storage address in the corresponding static random access memory are determined based on the static random access memory order corresponding to each polynomial pair participating in the operation in the same parallel operation and the operation order of the parallel operation in the operation stage in which the parallel operation is located, include: When r=0, x_r=t, y_r= +p; When r∈[1,b-1], x_r=(t% )* +(p / / )、y_r= +p-(p / / )* ; When r∈[b,n-1], x_r=( +p) / / ,y_r= +p-x_r* ; Among them, r represents the stage of the inverse number theory transformation, t represents the static random access memory order corresponding to each polynomial pair in the same parallel operation, t∈[0,K), p represents the operation order of the parallel operation in its inverse number theory transformation stage, x_r is the static random access memory code, and y_r is the storage address in the static random access memory.

17. A computer-readable storage medium comprising instructions, which, when executed on a computer, causes the computer to execute the method according to any one of claims 7 to 12 or 15 to 16.

18. A chip comprising the device according to any one of claims 1-6 or 13-14.

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